CN115547994A - Three-dimensional silicon capacitor integrated structure, integrated passive device and preparation method thereof - Google Patents
Three-dimensional silicon capacitor integrated structure, integrated passive device and preparation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 122
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 122
- 239000010703 silicon Substances 0.000 title claims abstract description 122
- 239000003990 capacitor Substances 0.000 title claims abstract description 105
- 238000002360 preparation method Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 238000003491 array Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 229910002804 graphite Inorganic materials 0.000 claims description 2
- 239000010439 graphite Substances 0.000 claims description 2
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims 1
- 230000010354 integration Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Inorganic materials [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- AQCDIIAORKRFCD-UHFFFAOYSA-N cadmium selenide Chemical compound [Cd]=[Se] AQCDIIAORKRFCD-UHFFFAOYSA-N 0.000 description 2
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- -1 cdS Chemical compound 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001773 titanium mineral Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a three-dimensional silicon capacitor integrated structure, which belongs to the technical field of integrated circuit manufacturing, and comprises a groove structure etched on a silicon substrate, wherein the groove structure comprises a silicon column array and a groove between the silicon column array, the integrated structure also comprises a conducting layer and a dielectric layer which are alternately deposited on the silicon column array in sequence and an isolating layer filled in the groove, each silicon column forms a minimum capacitor unit with at least one conducting layer-dielectric layer-conducting layer structure, and the bottom of each minimum capacitor unit is connected in series or in parallel through a redistribution layer and an electrode layer so as to achieve the required capacitance value. According to the scheme, the plurality of minimum capacitance units are integrated on the same silicon substrate, and the capacitors with required capacitance values are formed by connecting the plurality of minimum capacitance units in series or in parallel, so that the size and the manufacturing cost of the large-capacity capacitor can be reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a three-dimensional silicon capacitor integrated structure, an integrated passive device and a preparation method thereof.
Background
Most of the traditional capacitors are discrete devices, one capacitor only comprises one capacitor, the capacitance value of a unit volume is small, and the space occupied by the capacitor device is large in a high-voltage high-power scene. The requirements of integration and miniaturization of electronic products cannot be met. At present, the research on integrated circuits mainly focuses on the integration of active devices, while the integration of passive devices is relatively delayed, and capacitors, which are important passive devices, have the functions of storing electric charges, smoothly changing voltage, blocking direct current and alternating current, bypassing high-frequency noise and the like. Therefore, the integration design of the capacitor is beneficial to further development towards miniaturization and high integration.
Silicon capacitors, as a new type of electronic component, are fabricated using silicon materials using semiconductor fabrication processes. Because the silicon material has good stability, the silicon capacitor also has good high-frequency characteristic and temperature characteristic, extremely low bias characteristic and high reliability. And most of the applications in the semiconductor industry are silicon-based integrated circuits, so that the integration of the capacitor based on the silicon capacitor can be better suitable for the packaging requirements of the capacitor in the integrated circuit.
Therefore, it is desirable to provide a three-dimensional silicon capacitor integrated structure, which can integrate the minimum capacitor unit on the same silicon substrate, thereby reducing the volume of the capacitor when the same capacitance value is achieved.
Disclosure of Invention
In view of the above problems, the present invention has been made in order to provide a three-dimensional silicon capacitor integrated structure, an integrated passive device, and a method of manufacturing the same.
According to one aspect of the invention, a three-dimensional silicon capacitor integrated structure is provided, which comprises a trench structure etched on a silicon substrate, wherein the trench structure comprises a silicon pillar array and a trench between the silicon pillar array, the integrated structure further comprises a conductive layer and a dielectric layer which are alternately deposited on the silicon pillar array in sequence and an isolation layer filled at the trench, each silicon pillar forms a minimum capacitor unit with a single or multiple conductive layer-dielectric layer-conductive layer structure, and the bottoms of the minimum capacitor units are connected in series or in parallel through a redistribution layer and an electrode layer to form a capacitor with a required capacitance value.
According to the three-dimensional silicon capacitor structure provided by the scheme, the plurality of minimum capacitor units formed on the same silicon substrate have certain capacitance values, and different minimum capacitor units are connected in series or in parallel through the connection mode of the bonding wires, so that the capacitance value with large capacity is required. Therefore, the size and the manufacturing cost of the large-capacity capacitor can be reduced.
Optionally, in the three-dimensional silicon capacitor integrated structure, a conductive layer and a dielectric layer are alternately deposited on the silicon pillar array in sequence, the conductive layer completely covers the silicon pillar array, and the dielectric layer completely covers the conductive layer.
Alternatively, in the three-dimensional silicon capacitor integrated structure, the aspect ratio value of the trench structure may be etched to be 2.
Optionally, in the three-dimensional silicon capacitor integrated structure, the conductive layer or the electrode layer is made of a composite material formed by any one or more of Cu, al, ta, graphite, cdS, and CdSe.
Optionally, in the three-dimensional silicon capacitor integrated structure, the dielectric constant of the dielectric layer or the isolation layer is higher than a predetermined value, and a material with a high dielectric constant, such as SiO, is selected 2 、BaO、HfO 2 、ZrO 2 、Al 2 O 3 、BaZrO 3 、BaTiO 3 Any one or more of them.
According to another aspect of the present invention, there is provided an integrated passive device comprising a three-dimensional silicon capacitor integration structure as described above, a resistor and/or a semiconductor device disposed on the back side of the silicon substrate of the three-dimensional silicon capacitor integration structure.
Alternatively, the resistor or the semiconductor device is formed by ion implantation doping with different concentrations on the back surface of the silicon substrate, and the doping parameters (depth and doping amount) of the resistor and the semiconductor device such as a transistor can be the same.
According to yet another aspect of the present invention, there is provided a method of manufacturing an integrated passive device, comprising:
etching a groove structure containing a silicon column array and a groove between the silicon column arrays on the surface of the silicon substrate;
depositing a conducting layer on the surface of the silicon pillar array, depositing a dielectric layer on the surface of the conducting layer to enable the dielectric layer to completely cover the surface of the conducting layer, depositing a conducting layer on the surface of the dielectric layer to enable the conducting layer to completely cover the surface of the dielectric layer, and enabling each silicon pillar to form a minimum capacitor unit with at least one conducting layer-dielectric layer-conducting layer structure;
filling an insulating material in the groove to serve as an isolation layer, and depositing a metal electrode on the top of the minimum capacitor unit to enable the metal electrode to form ohmic contact with the outermost conductive layer of the minimum capacitor unit;
connecting the minimum capacitance unit to the metal electrode in a series or parallel mode by etching a redistribution layer to obtain a capacitor unit with a certain capacitance value;
ion implantation doping is carried out on the back side of the silicon substrate so as to integrate a resistor and/or a semiconductor device on the back side of the silicon substrate, and an integrated passive device is formed by combining a capacitor on the front side of the silicon substrate.
Alternatively, the cross section of the silicon pillars in the trench structure may have any one shape of a circle, a triangle, a diamond, a honeycomb, and the like, and the silicon pillars are spaced at the same distance.
Alternatively, in the above method, the conductive layer and the dielectric layer are deposited by any one of physical vapor deposition, atomic layer deposition, high-density plasma enhanced chemical vapor deposition, and plasma enhanced chemical vapor deposition.
According to the scheme of the invention, a plurality of minimum capacitance units are etched on the same silicon substrate through a semiconductor etching process, each minimum capacitance unit is provided with at least one conducting layer-dielectric layer-conducting layer structure, and the effective area of a capacitor electrode is greatly increased, so that the charge capacity of a unit area is improved, the breakdown voltage of the capacitor is improved, and a higher capacitance value can be ensured while the size of the capacitor is reduced; the capacitance value actually required is achieved by connecting a plurality of minimum capacitance units in series or in parallel, and the size and the manufacturing cost of the large-capacity capacitor are reduced; and because of the compatibility of the surface silicon process and the integrated circuit process, the integrated passive device with the three-dimensional silicon capacitor integrated structure can be directly attached in the integrated circuit, and the anti-interference capability of the circuit is improved.
The above description is only an overview of the technical solutions of the present invention, and the present invention can be implemented in accordance with the content of the description so as to make the technical means of the present invention more clearly understood, and the above and other objects, features, and advantages of the present invention will be more clearly understood.
Drawings
Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 illustrates a schematic diagram of a three-dimensional silicon capacitive integrated structure 100 having one conductive layer-dielectric layer-conductive layer structure, according to one embodiment of the present invention;
FIG. 2 illustrates a schematic diagram of a three-dimensional silicon capacitive integrated structure 200 having two conductive layer-dielectric layer-conductive layer structures, according to one embodiment of the present invention;
FIG. 3 illustrates a schematic top view of a three-dimensional silicon capacitor 300 according to one embodiment of the present invention;
fig. 4 shows a flow diagram of a method 400 of fabricating an integrated passive device according to one embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As is well known, the capacitance of a capacitor is determined by the following equation:
wherein epsilon 0 Is a vacuum dielectric constant of ∈ r For the relative dielectric constant, A is the effective area of the capacitor and d is the distance between the two plates of the capacitor. To increase the capacitance, three angles can be considered: selecting a material with high relative dielectric constant; increasing the effective area between the conductive layers per unit area; the distance between the two conductive layers is reduced. The silicon capacitor is manufactured by using a semiconductor manufacturing process and a silicon material, so that the integration of a capacitor device is facilitated. Reducing the size of the capacitor may allow the capacitor to be placed in close proximity to highly integrated high performance system semiconductors, which may be advantageous for optimizing power. In order to realize integration of a capacitor device and guarantee capacitance values of capacitors, the scheme provides a three-dimensional silicon capacitor integrated structure based on silicon capacitors, and integrates a plurality of minimum capacitor units on the same silicon substrate, wherein each minimum capacitor unit is provided with at least one conducting layer-dielectric layer-conducting layer structure, so that the effective area of a capacitor electrode can be greatly increased, the charge capacity of a unit area is improved, the breakdown voltage of the capacitor is improved, a plurality of capacitors are connected in series-parallel connection to achieve a higher capacitance value actually required, and the size and the manufacturing cost of a large-capacity capacitor can be reduced.
Fig. 1 shows a schematic diagram of a three-dimensional silicon capacitor integrated structure 100 having a conductive layer-dielectric layer-conductive layer structure, according to one embodiment of the present invention. It should be noted that the three-dimensional silicon capacitor integrated structure is a side view of a microstructure, as shown in fig. 1, the three-dimensional silicon capacitor integrated structure 100 having a conductive layer-dielectric layer-conductive layer structure includes a trench structure etched on a silicon substrate, a top electrode, a back electrode, and an RDL layer (redistribution layer), the trench structure includes a silicon pillar array and a trench between the silicon pillar arrays, and the silicon pillar array may be in various forms such as a cylinder, a diamond column, a star column, a honeycomb column, and may also include silicon pillars with various shapes. In the embodiment of the invention, the aspect ratio of the trench structure is (2-50): 1, namely, the height-width ratio of the silicon columns is (2-50): 1, and the spacing distances between the adjacent silicon columns in the silicon column array are the same. As shown in FIG. 1, the three-dimensional silicon capacitor integrated structure further comprises a conductive layer alternately deposited on the silicon pillar array in sequenceThe layers and the dielectric layer and the isolation layer filled in the groove enable each silicon column to form a minimum capacitance unit with a conductive layer-dielectric layer-conductive layer structure, and the bottoms of the minimum capacitance units are connected in series or in parallel through the redistribution layer and the electrode layer to form a capacitor with a required capacitance value. The insulating material and the dielectric layer material filled between the trenches may be the same or different, and the metal electrode material and the conductive layer material deposited on the top of each minimum capacitance unit may be the same or different, where the materials of the conductive layer and the electrode layer may be metal materials such as Cu (copper), al (aluminum), ta (tantalum), or alloy materials such as copper alloy, aluminum alloy, or cadmium sulfide (CdS), cadmium selenide (CdSe), or a composite material of a combination of multiple metal materials, or the like. The dielectric layer and the isolation layer can be made of high dielectric constant (high dielectric constant indicates poor conductivity and good insulation), such as SiO 2 (silicon dioxide), baO (barium oxide), hfO 2 (hafnium oxide), zrO 2 (zirconium dioxide) and Al 2 O 3 (alumina), baZrO 3 、BaTiO 3 Barium titanate-based and lead titanate-based materials having a titanium-mineral phase structure. The dielectric layer can isolate different conductive layers, and the conductive layers and the dielectric layers alternately deposited on each silicon pillar form a minimum capacitance unit with a conductive layer-dielectric layer-conductive layer structure.
Figure 2 shows a schematic diagram of a three-dimensional silicon capacitive integrated structure 200 with two conductive layer-dielectric layer-conductive layer structures, according to one embodiment of the present invention. As shown in fig. 2, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer are sequentially deposited on each silicon pillar to form a minimum capacitance unit having two conductive layer-dielectric layer-conductive layer structures. In order to enable the conductive layer to form an ohmic contact with the electrode layer of the top layer or the bottom layer, a contact hole may be etched at the trench and then filled with a metal material so that the middle conductive layer can form an ohmic contact with the external electrode.
According to the actual capacitance value requirement, a minimum capacitance unit with a multi-layer conducting layer-dielectric layer-conducting layer structure can be formed on each silicon column of the same silicon substrate, the capacitance value is increased as much as possible by depositing the dielectric layer and the conducting layer of the high-dielectric material for many times, and the expected capacitance range can reach 5nF-5uF. Different minimum capacitance units can be connected in series or in parallel by etching the redistribution layer to form a capacitor unit with a certain capacitance value.
Fig. 3 shows a schematic top view of a three-dimensional silicon capacitor 300 according to one embodiment of the invention. As shown in fig. 3, there is one electrode above each capacitor unit, i.e. one electrode corresponds to each capacitor unit, and further, different capacitor units can be connected in series or in parallel through bonding wires so as to achieve a capacitor with a desired capacitance value. When capacitors formed by different silicon columns are connected in parallel, the capacitance value of the integrated capacitor can be increased; when capacitors formed by different silicon columns are connected in series, the voltage resistance value of the integrated capacitor can be increased.
According to an embodiment of the invention, a doped resistor or a semiconductor device such as a PiN diode or a schottky diode can be formed on the back surface of the silicon substrate of the three-dimensional silicon capacitor integrated structure through a doping process, so that an integrated passive device is realized. The resistor or semiconductor device may be formed by ion implantation doping on the back side of the silicon substrate. The resistivity of a resistor or a semiconductor device is determined by carrier concentration and mobility, and the higher the concentration of doped impurities, the smaller the resistivity. The semiconductor device can comprise a silicon substrate, a PN junction and a high-doped resistance region, and the resistance region and the semiconductor device region can be in circuit connection through a redistribution layer to form a passive device with a specific function.
Fig. 4 shows a flow diagram of a method 400 of fabricating an integrated passive device according to one embodiment of the invention. As shown in fig. 4, the method 400 begins with step S410, etching a trench structure on a surface of a silicon substrate, the trench structure including an array of silicon pillars and a trench between the array of silicon pillars.
In order to increase the effective area of the capacitor, the silicon substrate may be etched to form a trench structure, and in general, the deep etching of the surface of the silicon material may be achieved by several times of plasma etching. The aspect ratio of the groove structure can reach (2-50): the trench structure with the high aspect ratio is beneficial to the three-dimensional integration design of a silicon capacitor integration structure, so that the volume of the capacitor is reduced, and the high capacitance value of the capacitor is ensured.
Then, step S420 is performed to deposit a conductive layer on the surface of the silicon pillar array, deposit a dielectric layer on the surface of the conductive layer, so that the dielectric layer completely covers the surface of the conductive layer, deposit a conductive layer on the surface of the dielectric layer, so that the conductive layer completely covers the surface of the dielectric layer, and form a minimum capacitance unit having at least one conductive layer-dielectric layer-conductive layer structure for each silicon pillar. The capacitance value can be increased as much as possible by depositing the high dielectric material dielectric layer and the conductive layer for a plurality of times, and the expected capacitance range can reach 5nF-5uF. The conductive layer and the dielectric layer may be deposited by Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), high density plasma enhanced chemical vapor deposition (HPECVD), plasma Enhanced Chemical Vapor Deposition (PECVD), or the like.
Step S430 is performed, an insulating material is filled in the trench to serve as an isolation layer, and a metal electrode is deposited on top of the minimum capacitance unit, so that the metal electrode forms an ohmic contact with the outermost conductive layer of the minimum capacitance unit.
Step S440 is performed to manufacture a redistribution layer by etching to connect the minimum capacitance unit to the metal electrode in series or in parallel, so as to obtain a capacitor unit with a certain capacitance value.
Finally, step S450 is performed, ion implantation doping is performed on the back surface of the silicon substrate, so as to integrate the resistor and/or the semiconductor device on the back surface of the silicon substrate, and the integrated passive device is formed by combining the capacitor on the front surface of the silicon substrate. For example, RC (resistive-capacitive) or RCD (resistive, capacitive, diode) integrated passive devices may be formed. The resistivity of a resistor or a semiconductor device is determined by the carrier concentration and mobility, and the higher the concentration of doped impurities, the smaller the resistivity. The semiconductor device can comprise a silicon substrate, a PN junction and a high-doped resistance region, and the resistance region and the semiconductor device region can be electrically connected through a redistribution layer to form an integrated passive device with a specific function.
According to the scheme, a plurality of minimum capacitor units are etched on the same silicon substrate through a semiconductor etching process, each minimum capacitor unit is provided with at least one conducting layer-dielectric layer-conducting layer structure, and the effective area of a capacitor electrode is greatly increased, so that the charge capacity per unit area is improved, the breakdown voltage of the capacitor is improved, and a higher capacitance value can be ensured while the size of the capacitor is reduced; the actually required capacitance value is achieved by connecting a plurality of minimum capacitance units in series or in parallel, and the size and the manufacturing cost of the large-capacity capacitor are reduced; and because of the compatibility of the surface silicon process and the integrated circuit process, the integrated passive device with the three-dimensional silicon capacitor integrated structure can be directly attached in the integrated circuit, and the anti-interference capability of the circuit is improved.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed to reflect the intent: rather, the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in a device as described in this embodiment or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may additionally be divided into multiple sub-modules.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Moreover, those skilled in the art will appreciate that although some embodiments described herein include some features included in other embodiments, not others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
Additionally, some of the embodiments are described herein as a method or combination of method elements that can be implemented by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purpose of carrying out the invention.
As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present invention has been disclosed by way of illustration and not limitation with respect to the scope of the invention, which is defined by the appended claims.
Claims (10)
1. A three-dimensional silicon capacitor integrated structure comprises a trench structure etched on a silicon substrate, wherein the trench structure comprises a silicon pillar array and a trench between the silicon pillar array, and the three-dimensional silicon capacitor integrated structure is characterized by further comprising a conducting layer and a dielectric layer which are alternately deposited on the silicon pillar array in sequence and an isolating layer filled in the trench, so that each silicon pillar forms a minimum capacitor unit with a single or multiple conducting layer-dielectric layer-conducting layer structures, and the bottom of each minimum capacitor unit is connected in series or in parallel through a redistribution layer and an electrode layer to form a capacitor with a required capacitance value.
2. The three-dimensional silicon capacitor integrated structure as claimed in claim 1, wherein the silicon pillar array is deposited with conductive layers and dielectric layers alternately in sequence, the conductive layers completely cover the silicon pillar array, and the dielectric layers completely cover the conductive layers.
3. The three-dimensional silicon capacitor integrated structure as claimed in claim 1, wherein the aspect ratio of the trench structure is (2-50): 1.
4. The three-dimensional silicon capacitor integrated structure according to claim 1, wherein the material of the electrode layer or the conductive layer is any one or more of Cu, al, ta, graphite, cdS and CdSe.
5. The three-dimensional silicon capacitor integrated structure as claimed in claim 1, wherein the dielectric constant of the dielectric layer is higher than a predetermined value, and the material of the dielectric layer or the isolation layer is SiO 2 、BaO、HfO 2 、ZrO 2 、Al 2 O 3 、BaZrO 3 、BaTiO 3 Any one or more of them.
6. An integrated passive device, characterized in that it comprises a three-dimensional silicon capacitive integrated structure as claimed in any one of claims 1 to 5, a resistor and/or a semiconductor device arranged on the back of the silicon substrate of said three-dimensional silicon capacitive integrated structure.
7. An integrated passive device according to claim 6, characterized in that the resistor or semiconductor device is created by ion implantation doping of different concentrations at the back side of the silicon substrate.
8. A method of fabricating an integrated passive device, the method comprising:
etching a groove structure containing a silicon column array and a groove between the silicon column arrays on the surface of the silicon substrate;
depositing a conducting layer on the surface of the silicon column array, depositing a dielectric layer on the surface of the conducting layer to enable the dielectric layer to completely cover the surface of the conducting layer, depositing a conducting layer on the surface of the dielectric layer to enable the conducting layer to completely cover the surface of the dielectric layer, and enabling each silicon column to form a minimum capacitor unit with at least one conducting layer-dielectric layer-conducting layer structure;
filling an insulating material at the groove to serve as an isolation layer, and depositing a metal electrode on the top of the minimum capacitance unit to enable the metal electrode to form ohmic contact with the outermost conductive layer of the minimum capacitance unit;
manufacturing a redistribution layer by etching to connect the minimum capacitance unit to the metal electrode in a series or parallel mode;
ion implantation doping is carried out on the back surface of the silicon substrate so as to integrate a resistor and/or a semiconductor device on the back surface of the silicon substrate, and an integrated passive device is formed by combining a capacitor on the front surface of the silicon substrate.
9. The method of claim 8, wherein the cross section of the silicon pillars in the trench structure is any one of circular, diamond, triangular and honeycomb, and the spacing distance between two adjacent silicon pillars is the same.
10. The method of claim 8, wherein the method comprises:
and depositing the conducting layer and the dielectric layer by any one of physical vapor deposition, atomic layer deposition, high-density plasma enhanced chemical vapor deposition and plasma enhanced chemical vapor deposition.
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| CN117878106A (en) * | 2024-03-12 | 2024-04-12 | 苏州苏纳光电有限公司 | Silicon capacitor electrode structure and silicon capacitor |
| CN117878106B (en) * | 2024-03-12 | 2024-05-28 | 苏州苏纳光电有限公司 | Silicon capacitor electrode structure and silicon capacitor |
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