CN115547995A - Three-dimensional silicon-based capacitor, preparation method thereof and integrated passive device - Google Patents
Three-dimensional silicon-based capacitor, preparation method thereof and integrated passive device Download PDFInfo
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- CN115547995A CN115547995A CN202211234477.7A CN202211234477A CN115547995A CN 115547995 A CN115547995 A CN 115547995A CN 202211234477 A CN202211234477 A CN 202211234477A CN 115547995 A CN115547995 A CN 115547995A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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Abstract
The invention discloses a three-dimensional silicon-based capacitor, which comprises a groove structure etched on a silicon substrate, wherein conducting layers and dielectric layers are alternately deposited on the groove structure, different conducting layers are completely isolated by the dielectric layers, the groove structure comprises a silicon column array and a groove between the silicon column arrays, an isolating layer is filled in the groove, a first electrode layer is deposited on a top conducting layer and the isolating layer, and an outermost conducting layer deposited on the groove structure is in ohmic contact with the first electrode layer; and a redistribution layer is etched on the back of the silicon substrate, a second electrode layer is deposited, and the innermost conductive layer deposited on the groove structure forms ohmic contact with the second electrode layer through the redistribution layer. The scheme can ensure that the capacitor outputs higher capacitance value or bears higher voltage while reducing the volume of the capacitor.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a three-dimensional silicon-based capacitor, a preparation method thereof and an integrated passive device.
Background
With the increasing integration degree of electronic products, the traditional capacitor mostly adopts discrete devices, and the capacitance value is lower, so that the application occasions of high voltage and high power cannot be met. At present, the research on integrated circuits mainly focuses on the integration of active devices, while the integration of passive devices is relatively delayed, and capacitors are used as important passive devices, and the integrated design of the capacitors is beneficial to further reduction of the volume of the integrated circuits.
Silicon capacitors, as a new type of electronic component, are fabricated using silicon materials using semiconductor fabrication processes. Because the silicon material has good stability, the silicon capacitor also has good high-frequency characteristic and temperature characteristic, extremely low bias characteristic and high reliability. And most of the applications in the semiconductor industry are silicon-based integrated circuits, so that the integration of the capacitor based on the silicon capacitor can be better suitable for the packaging requirements of the capacitor in the integrated circuit. Most of the existing silicon capacitors are only suitable for the condition of low voltage, and the breakdown voltage is lower.
Therefore, a three-dimensional silicon-based capacitor is needed to be provided, which can improve the breakdown voltage of the capacitor, reduce the size of the capacitor, ensure a higher capacitance value, and adapt to a high-voltage and high-power use scenario, so as to solve the problems existing in the prior art.
Disclosure of Invention
In view of the above, the present invention has been made to provide a three-dimensional silicon-based capacitor and a method of fabricating the same and an integrated passive device that overcome or at least partially solve the above problems.
According to one aspect of the invention, a three-dimensional silicon-based capacitor is provided, which comprises a groove structure etched on a silicon substrate, wherein conductive layers and dielectric layers are alternately deposited on the groove structure, different conductive layers are completely isolated by the dielectric layers, the groove structure comprises a silicon column array and a groove between the silicon column arrays, an isolation layer is filled in the groove, a first electrode layer is deposited on a top conductive layer and the isolation layer, and an outermost conductive layer deposited on the groove structure and the first electrode layer form ohmic contact; the back of the silicon substrate is etched with a redistribution layer and deposited with a second electrode layer, so that the innermost conductive layer deposited on the trench structure forms ohmic contact with the second electrode layer through the redistribution layer.
The effective area of a capacitor plate can be increased and the capacitance value per unit area can be improved by etching a trench structure with a deep trench ratio on a silicon substrate and alternately depositing a conducting layer-dielectric layer-conducting layer structure on the trench structure; by depositing a high dielectric constant dielectric layer between the conductive layers, the breakdown voltage of the capacitor can be increased, and the capacitance of the capacitor can be increased without increasing the volume of the capacitor.
Optionally, in the three-dimensional silicon-based capacitor, the aspect ratio of the trench structure is (2-50): 1.
Optionally, in the three-dimensional silicon-based capacitor, the conductive layer is made of any one of Cu, al, ta, graphite, cdS, cdSe, and a composite material.
Optionally, in the three-dimensional silicon-based capacitor, the dielectric constant of the dielectric layer is higher than a predetermined value, and the materials of the dielectric layer and the isolation layer are one or more of SiO2, baO, hfO2, zrO2, al2O3, baZrO3, and BaTiO 3.
According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional silicon-based capacitor, comprising: etching a groove structure on the surface of the silicon substrate, wherein the groove structure comprises a silicon column array and a groove between the silicon column arrays; depositing a conducting layer on the surface of the groove structure, depositing a dielectric layer on the surface of the conducting layer to enable the dielectric layer to completely cover the surface of the conducting layer, depositing a conducting layer on the surface of the dielectric layer to enable the conducting layer to completely cover the surface of the dielectric layer, and forming at least one conducting layer-dielectric layer-conducting layer structure; and depositing a first electrode layer on the top conducting layer and the isolating layer, etching the redistribution layer at the bottom of the silicon substrate and depositing a second electrode layer, so that the outermost conducting layer deposited on the groove structure forms ohmic contact with the first electrode layer, and the innermost conducting layer deposited on the groove structure forms ohmic contact with the second electrode layer, thereby obtaining the three-dimensional silicon-based capacitor with the preset capacitance value.
Alternatively, in the above method, the conductive layer and the dielectric layer are deposited by any one of physical vapor deposition, atomic layer deposition, high-density plasma enhanced chemical vapor deposition, and plasma enhanced chemical vapor deposition.
According to another aspect of the present invention, there is provided an integrated passive device comprising a three-dimensional silicon-based capacitor as defined above and a resistor and/or a semiconductor device disposed on the back side of the silicon substrate of the three-dimensional silicon-based capacitor, the resistor or the semiconductor device being produced by ion implantation doping of different concentrations on the back side of the silicon substrate.
According to the scheme of the invention, the three-dimensional capacitor microstructure with at least one conducting layer-dielectric layer-conducting layer structure is formed on the silicon substrate through a mature semiconductor etching process, so that the effective area of the capacitor electrode can be greatly increased, the capacitance of a unit area is improved, the size of the capacitor can be reduced, a higher capacitance value can be ensured, and the three-dimensional capacitor microstructure can adapt to the use scenes of high voltage and high power; and because of the compatibility of the surface silicon process and the integrated circuit process, the integrated passive device with the three-dimensional silicon-based capacitor can be directly attached in the integrated circuit, and the anti-interference capability of the circuit is improved. And the preparation process of the three-dimensional silicon-based capacitor is simple, and the production cost of the capacitor can be reduced.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a schematic microstructure diagram of a three-dimensional silicon-based capacitor 100 having a conductive layer-dielectric layer-conductive layer structure according to an embodiment of the present invention;
FIG. 2 illustrates a schematic microstructure diagram of a three-dimensional silicon-based capacitor 200 having two conductive layer-dielectric layer-conductive layer structures according to one embodiment of the present invention;
FIG. 3 illustrates a schematic top view of a three-dimensional silicon-based capacitor 300 according to one embodiment of the invention;
fig. 4 shows a schematic flow diagram of a method 400 for fabricating a three-dimensional silicon-based capacitor according to an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As is well known, the capacitance of a capacitor is determined by the following equation:
wherein epsilon 0 Is a vacuum dielectric constant of ∈ r For the relative dielectric constant, A is the effective area of the capacitor and d is the distance between the two plates of the capacitor. If the capacitance is to be increased, three angles can be used: selecting a material with high relative dielectric constant; increasing the effective area between the conductive layers per unit area; the distance between the two conductive layers is reduced. The silicon capacitor is manufactured by using a semiconductor manufacturing process and a silicon material, so that the integration of a capacitor device is facilitated. Reducing the size of the capacitor may allow the capacitor to be placed in close proximity to highly integrated high performance system semiconductors, which may be advantageous for optimizing power. In order to realize integration of a capacitor device and improve the capacitance value of the capacitor under the condition of not increasing the volume of the capacitor, the scheme provides a three-dimensional silicon-based capacitor and a preparation method thereof.
Fig. 1 shows a schematic microstructure diagram of a three-dimensional silicon-based capacitor 100 having a conducting layer-dielectric layer-conducting layer structure according to an embodiment of the present invention. As shown in fig. 1, a side view of a microstructure of the three-dimensional silicon-based capacitor 100 includes a trench structure etched on a silicon substrate, wherein a conductive layer, a dielectric layer and a conductive layer are alternately deposited on the trench structure, different conductive layers are completely isolated by the dielectric layer, the trench structure includes a silicon pillar array and a trench between the silicon pillar arrays, an isolation layer is filled in the trench, a first electrode layer is deposited on a top conductive layer and the isolation layer, and an outermost conductive layer deposited on the trench structure forms ohmic contact with the first electrode layer; the back of the silicon substrate is etched with a redistribution layer and deposited with a second electrode layer, so that the innermost conductive layer deposited on the trench structure forms ohmic contact with the second electrode layer through the redistribution layer. The silicon column array can be in various forms such as a cylinder, a diamond column, a star column and a honeycomb column, and can also comprise silicon columns in various shapes, and the spacing distances between adjacent silicon columns in the silicon column array are the same. In the embodiment of the present invention, the aspect ratio of the trench structure is between 2 and 50, that is, the height-to-width ratio of the silicon pillar is between 2 and 50.
The materials of the conductive layer, the first electrode layer and the second electrode layer may be metal materials such as Cu (copper), al (aluminum), ta (tantalum), or alloy materials such as copper alloy and aluminum alloy, cadmium sulfide (CdS) and cadmium selenide (CdSe), or composite materials of a combination of multiple metal materials, and the dielectric layer and the isolation layer may be selected from materials with high dielectric constant (high dielectric constant indicates poor conductivity and good insulation), such as barium titanate and lead titanate materials with titanium ore phase structure, such as SiO2 (silicon dioxide), baO (barium oxide), hfO2 (hafnium dioxide), zrO2 (zirconium dioxide), al2O3 (aluminum oxide), baZrO3, baTiO3, and the like. The dielectric layer may prevent interconnection between different conductive layers. The etched conductive lines in the redistribution layer enable the innermost conductive layer to form an ohmic contact with the second conductive layer.
Fig. 2 shows a schematic microstructure diagram of a three-dimensional silicon-based capacitor 200 with two conductive layer-dielectric layer-conductive layer structures according to an embodiment of the present invention. As shown in fig. 2, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer are sequentially deposited on the trench structure to form two conductive layer-dielectric layer-conductive layer structures, a redistribution layer is etched on the bottom of the silicon substrate, and a wire in the redistribution layer can connect the first conductive layer to the second electrode layer. It should be noted that the microstructure of the three-dimensional silicon-based capacitor shown in fig. 1 and 2 is merely exemplary, and the number of conductive layer-dielectric layer-conductive layer structures can be increased according to the actual required capacitance value, and the expected capacitance value range can reach 5nF-5uF.
Figure 3 illustrates a schematic top view of a three-dimensional silicon-based capacitor 300 according to one embodiment of the invention. As shown in fig. 3, the three-dimensional silicon-based capacitor 300 can be connected in series or in parallel on a silicon substrate by wire bonding to achieve a desired capacitance.
According to an embodiment of the invention, a doped resistor or a semiconductor device such as a PiN diode or a schottky diode can be formed on the back surface of the silicon substrate of the three-dimensional silicon-based capacitor through a doping process, so that an integrated passive device is realized. The resistor or semiconductor device may be formed by ion implantation doping on the back side of the silicon substrate. The resistivity of a resistor or a semiconductor device is determined by the carrier concentration and mobility, and the higher the concentration of doped impurities, the smaller the resistivity. The semiconductor device can comprise a silicon substrate, a PN junction and a high-doped resistance region, and the resistance region and the semiconductor device region can be connected through a redistribution layer in a circuit mode to form a passive device with functions.
Fig. 4 shows a flow diagram of a method 400 for fabricating a three-dimensional silicon-based capacitor according to an embodiment of the invention. As shown in fig. 4, the method 400 begins with etching a trench structure on a surface of a silicon substrate, the trench structure including an array of silicon pillars and a trench between the array of silicon pillars at step S410.
In order to increase the effective area of the capacitor, the silicon substrate may be etched to form a trench structure, and in general, the deep etching of the surface of the silicon material may be achieved by several times of plasma etching. The aspect ratio of the groove structure can reach (2-50): 1, the high aspect ratio trench structure of 50.
Then, step S420 is performed to deposit a conductive layer on the surface of the trench structure, deposit a dielectric layer on the surface of the conductive layer to completely cover the surface of the conductive layer, and deposit a conductive layer on the surface of the dielectric layer to completely cover the surface of the dielectric layer to form at least one conductive layer-dielectric layer-conductive layer structure. The conductive layer and the dielectric layer can be deposited by Physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), high density plasma enhanced chemical vapor deposition (HPECVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.
And finally, executing a step S430, depositing a first electrode layer on the top conducting layer and the isolating layer, etching the redistribution layer at the bottom of the silicon substrate and depositing a second electrode layer, so that the outermost conducting layer deposited on the trench structure forms ohmic contact with the first electrode layer, and the innermost conducting layer deposited on the trench structure forms ohmic contact with the second electrode layer, thereby obtaining the three-dimensional silicon-based capacitor with the preset capacitance value.
According to the scheme, the three-dimensional capacitor microstructure with at least one conducting layer-dielectric layer-conducting layer structure is formed on the silicon substrate through a mature semiconductor etching process, so that the effective area of a capacitor electrode can be greatly increased, the capacitance of a unit area is improved, the size of the capacitor can be reduced, a higher capacitance value can be ensured, and the three-dimensional capacitor microstructure can be suitable for use scenes of high voltage and high power; and because of the compatibility of the surface silicon process and the integrated circuit process, the integrated passive device with the three-dimensional silicon-based capacitor can be directly attached in the integrated circuit, and the anti-interference capability of the circuit is improved. And the preparation process of the three-dimensional silicon-based capacitor is simple, and the production cost of the capacitor can be reduced.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the device in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore, may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Moreover, those skilled in the art will appreciate that although some embodiments described herein include some features included in other embodiments, not others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
Additionally, some of the embodiments are described herein as a method or combination of method elements that can be implemented by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the means for performing the functions performed by the elements for the purpose of carrying out the invention.
As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as described herein. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present invention has been disclosed in an illustrative rather than a restrictive sense with respect to the scope of the invention, as defined in the appended claims.
Claims (8)
1. A three-dimensional silicon-based capacitor comprises a groove structure etched on a silicon substrate, and is characterized in that conducting layers and dielectric layers are alternately deposited on the groove structure, different conducting layers are completely isolated through the dielectric layers, the groove structure comprises a silicon column array and a groove between the silicon column arrays, an isolation layer is filled in the groove, a first electrode layer is deposited on a top conducting layer and the isolation layer, and an outermost conducting layer deposited on the groove structure and the first electrode layer form ohmic contact; the back of the silicon substrate is etched with a redistribution layer and deposited with a second electrode layer, so that the innermost conductive layer deposited on the trench structure forms ohmic contact with the second electrode layer through the redistribution layer.
2. The three-dimensional silicon-based capacitor according to claim 1, wherein the trench structure has an aspect ratio of (2-50): 1.
3. The three-dimensional silicon-based capacitor according to claim 1, wherein the conductive layer and the electrode layer are made of any one or more of Cu, al, ta, graphite, cdS, cdSe and a composite material.
4. The three-dimensional silicon-based capacitor according to claim 1, wherein the material of the dielectric layer and the isolation layer is SiO 2 、BaO、HfO 2 、ZrO 2 、Al 2 O 3 、BaZrO 3 、BaTiO 3 One or more of them.
5. A method of fabricating a three-dimensional silicon-based capacitor, the method comprising:
etching a groove structure on the surface of the silicon substrate, wherein the groove structure comprises a silicon column array and a groove between the silicon column arrays;
depositing a conducting layer on the surface of the groove structure, depositing a dielectric layer on the surface of the conducting layer to enable the dielectric layer to completely cover the surface of the conducting layer, depositing a conducting layer on the surface of the dielectric layer to enable the conducting layer to completely cover the surface of the dielectric layer, and forming at least one conducting layer-dielectric layer-conducting layer structure;
and depositing a first electrode layer on the top conducting layer and the isolation layer, etching the redistribution layer at the bottom of the silicon substrate and depositing a second electrode layer, so that the outermost conducting layer deposited on the trench structure forms ohmic contact with the first electrode layer, and the innermost conducting layer deposited on the trench structure forms ohmic contact with the second electrode layer, thereby obtaining the three-dimensional silicon-based capacitor.
6. The method of claim 5, wherein the method comprises:
and depositing the conducting layer and the dielectric layer by any one method of physical vapor deposition, atomic layer deposition, high-density plasma enhanced chemical vapor deposition and plasma enhanced chemical vapor deposition.
7. An integrated passive device, characterized in that it comprises a three-dimensional silicon-based capacitor as claimed in any one of claims 1 to 5 and a resistor and/or a semiconductor device arranged on the back of the silicon substrate of said three-dimensional silicon-based capacitor.
8. The integrated passive device of claim 7, wherein the resistor or semiconductor device is created by ion implantation doping of different concentrations at the back side of the silicon substrate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117577449A (en) * | 2024-01-16 | 2024-02-20 | 宜确半导体（苏州）有限公司 | Three-dimensional structure capacitor and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117577449A (en) * | 2024-01-16 | 2024-02-20 | 宜确半导体（苏州）有限公司 | Three-dimensional structure capacitor and preparation method thereof |
| CN117577449B (en) * | 2024-01-16 | 2024-04-05 | 宜确半导体（苏州）有限公司 | Three-dimensional structure capacitor and preparation method thereof |
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