CN115542110A - Multi-temperature automatic test system and method for semiconductor chip - Google Patents
Multi-temperature automatic test system and method for semiconductor chip Download PDFInfo
- Publication number
- CN115542110A CN115542110A CN202211109485.9A CN202211109485A CN115542110A CN 115542110 A CN115542110 A CN 115542110A CN 202211109485 A CN202211109485 A CN 202211109485A CN 115542110 A CN115542110 A CN 115542110A
- Authority
- CN
- China
- Prior art keywords
- test
- temperature
- semiconductor chip
- testing
- sorting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/34—Sorting according to other particular properties
- B07C5/344—Sorting according to other particular properties according to electric or electromagnetic properties
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/36—Sorting apparatus characterised by the means used for distribution
- B07C5/38—Collecting or arranging articles in groups
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2877—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to cooling
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a semiconductor chip multi-temperature automatic test system and a test method, wherein the system comprises a sorting machine and a testing machine, and further comprises the following steps: high and low temperature equipment, and the high and low temperature equipment is installed in the separator; the high-low temperature equipment is used for providing various different testing temperatures for the semiconductor chip; the tester is used for testing the semiconductor chips at different testing temperatures respectively; the sorting machine is used for sorting the semiconductor chips, and the sorting basis is the test data output by the testing machine. According to the invention, the high-low temperature equipment is arranged on the sorting machine, so that the sorting machine can control the testing temperature while testing and sorting the semiconductor chips, the automatic temperature scanning test of the semiconductor chips is realized, the labor cost is saved, and the testing efficiency is improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a semiconductor chip multi-temperature automatic testing system and a testing method.
Background
In the prior art, semiconductor chip test equipment, such as a sorting machine and a testing machine, are directly connected through a cable, a semiconductor chip sends a test starting signal to the testing machine once after reaching a test position of the sorting machine, and the testing machine tests once and returns a signal to complete a test process.
However, the semiconductor chip can only be tested at one temperature, if the performance of the chip at high temperature and low temperature needs to be tested at the same time, the test at one temperature needs to be performed, then the chip is loaded again and then the test at another temperature needs to be performed, that is, each time the chip is loaded, only one set temperature can be tested, for example, when 85 ℃, the performance of the chip at one temperature of 85 ℃ can be tested, and the test at other temperatures cannot be realized, so that a lot of time is consumed when the chip is required to be subjected to the temperature scanning test.
Disclosure of Invention
In view of this, embodiments of the present invention provide a semiconductor chip multi-temperature automatic test system and a test method thereof, so as to solve the problem that the current semiconductor chip test technology can only test the performance at one temperature by one-time loading.
The embodiment of the invention provides a semiconductor chip multi-temperature automatic test system, which comprises a sorting machine and a testing machine, and further comprises: high and low temperature equipment, and the high and low temperature equipment is installed in the separator; wherein, the first and the second end of the pipe are connected with each other,
the high-low temperature equipment is used for providing various different testing temperatures for the semiconductor chip;
the tester is used for testing the semiconductor chips at different testing temperatures respectively;
the sorting machine is used for sorting the semiconductor chips, and the sorting basis is the test data output by the testing machine.
Optionally, the semiconductor chip multi-temperature automatic test system further includes: a main control panel;
the main control board is used for controlling the high-low temperature equipment, the sorting machine and/or the testing machine.
Optionally, the main control board controls the temperature of the high and low temperature devices according to a first test temperature and a step temperature input from the outside or preset inside so as to provide a plurality of different test temperatures for the semiconductor chip; and/or the presence of a gas in the atmosphere,
the main control board controls the tester to test the semiconductor chip in the high-low temperature equipment; and/or the presence of a gas in the atmosphere,
and the main control board obtains the sorting basis of the semiconductor chip according to the test data output by the test machine, and controls the sorting machine to sort the semiconductor chip based on the sorting basis.
The embodiment of the invention also provides a semiconductor chip multi-temperature automatic test method, which is applied to a semiconductor chip multi-temperature automatic test system, the system comprises a sorting machine and a test machine, the system also comprises high-low temperature equipment, and the high-low temperature equipment is arranged in the sorting machine, and the method comprises the following steps:
s201: the sorting machine directly or indirectly sends a first instruction to the high-low temperature equipment after detecting that the semiconductor chip is located at the test position in the high-low temperature equipment;
s202: the high-low temperature equipment adjusts the current test temperature to a first test temperature according to the first instruction;
s203: the testing machine tests the semiconductor chip at the current testing temperature to obtain testing data at the current testing temperature;
s204: if the test for the semiconductor chip is not finished, the high-low temperature equipment adjusts the current test temperature to another new test temperature;
repeating steps S203 and S204 until the test for the semiconductor chip is ended;
s205: the sorting machine sorts the semiconductor chips according to test data obtained by testing the semiconductor chips by the testing machine.
Optionally, the semiconductor chip multi-temperature automatic test system further includes a main control board;
after detecting that a semiconductor chip is located at a test position in the high-low temperature equipment, the sorting machine indirectly sends a first instruction to the high-low temperature equipment, and the method comprises the following steps:
after detecting that a semiconductor chip is located at a test position in the high-low temperature equipment, the sorting machine sends the corresponding first instruction to the main control board;
the main control board forwards the first instruction to the high-low temperature equipment, or generates a new first instruction based on the first instruction and then sends the new first instruction to the high-low temperature equipment.
Optionally, the condition of ending the test is as follows: the completed test temperature satisfies the test requirements for the semiconductor chip, or the test data from the completed test indicates that the semiconductor chip fails.
Optionally, the first test temperature is greater than 20 ℃ and less than 30 ℃; the highest test temperature meeting the test requirements of the semiconductor chip is a first temperature, the lowest test temperature is a second temperature, the first temperature is higher than the first test temperature, and the second temperature is lower than the first test temperature; after the current testing temperature of the high-low temperature equipment is adjusted to the first testing temperature, the high-low temperature equipment is adjusted to the second temperature firstly, and then the high-low temperature equipment is adjusted to the first temperature according to a preset stepping temperature.
Optionally, the temperature between the second temperature and the first temperature is divided into at least two temperature ranges, where the lowest temperature in the first temperature range is the second temperature, and the highest temperature is greater than or equal to the first test temperature;
the sorter sorts the semiconductor chips, including:
the sorting machine obtains a sorting basis; the sorting criterion is determined at least based on a grading result of the semiconductor chip, and the grading result is determined according to test data obtained by testing the semiconductor chip by the testing machine;
the sorting machine sorts the semiconductor chips according to the sorting basis;
if the test temperature of the last test is not within the first temperature range after the test of the semiconductor chip is finished, the grading result of the semiconductor chip is obtained according to the judgment result of each test of the semiconductor chip.
Optionally, the determination result includes a level a, a level B, and a level C, and the levels of the level a, the level B, and the level C are sequentially reduced;
when a classification result of the semiconductor chip is obtained from a judgment result for each test of the semiconductor chip: if the judgment result of at least N times of tests is A level, the grading result of the semiconductor chip is A level; if the judgment result of at least N times of tests is C level, the grading result of the semiconductor chip is C level; in other cases, the grading result of the semiconductor chip is B grade;
and N is a positive integer, and is greater than or equal to a preset value, wherein the preset value is greater than or equal to half of the number of completed tests.
Optionally, if the test temperature of the last test is not within the first temperature range when the test of the semiconductor chip is finished, the sorting criterion used when the semiconductor chip is sorted is determined according to the grading result of the semiconductor chip and the failure temperature, and the failure temperature is determined according to the test temperature of the semiconductor chip when the test is finished and the reason of the test finish.
Optionally, the judgment result for each test of the semiconductor chip is obtained according to the following method:
for each test, respectively judging whether the test data of each test item is in the corresponding reference range;
if the test data of one test item is not in the corresponding reference range, the judgment result of the current test is unqualified;
if the test data of all the test items are in the corresponding reference range, respectively calculating the difference value between the test data of each test item and the corresponding optimal reference value; determining the score of each test item according to the difference value, wherein the larger the difference value is, the smaller the score is; calculating a sum of the scores for each of the test items; and according to the total sum of the scores, the judgment result of the current test is the A level, the B level or the C level, and the total sums of the scores required by the A level, the B level and the C level are sequentially decreased.
Optionally, the reference range varies with the test temperature.
According to the semiconductor chip multi-temperature automatic test system and the test method provided by the embodiment of the invention, the high-low temperature equipment is arranged on the sorting machine, namely the high-low temperature equipment and the sorting machine are designed into an integrated structure, so that the sorting machine can test and sort the semiconductor chips and control the test temperature of the semiconductor chips, namely the semiconductor chips can be kept still on the test position after reaching the test position in the high-low temperature equipment on the sorting machine, and then the sorting machine controls the test temperature of the semiconductor chips through the high-low temperature equipment, so that the semiconductor chips can be tested at different temperatures respectively, the automatic temperature scanning test of the semiconductor chips is realized, the labor cost is saved, and the test efficiency is improved.
In addition, the semiconductor chip multi-temperature automatic test system provided by the embodiment of the invention can obtain the temperature characteristics of a plurality of parameters of the semiconductor chip by one-time scanning, and is convenient for carrying out temperature-related analysis on a plurality of performances of the semiconductor chip at a later stage. In addition, in the embodiment of the invention, the sorting machine stores the semiconductor chips according to the sorting basis, and the sorting basis is related to the temperature grade of the semiconductor chips (determined based on the temperature range where the failure temperature of the semiconductor chips is located), so that the convenience of screening the semiconductor chips with different temperature grades is improved.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:
fig. 1 is a schematic structural diagram of a semiconductor chip multi-temperature automatic test system according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a semiconductor chip multi-temperature automatic testing method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises that element. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate a number of the indicated technical features. In the description of the following examples, "plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, an embodiment of the invention provides a semiconductor chip multi-temperature automatic test system, which includes a handler 101 and a tester 102, and further includes: the high-low temperature equipment 103 is arranged in the sorting machine 101, that is, the high-low temperature equipment 103 is arranged on the sorting machine 101, or the high-low temperature equipment 103 and the sorting machine 101 are of an integral structure; wherein the content of the first and second substances,
the high-low temperature equipment 103 is used for providing various different testing temperatures for the semiconductor chip; that is, the temperature controller is configured to control a test temperature of the semiconductor chip, or control a temperature of the high/low temperature device 103, so that the semiconductor chip reaches a temperature required for the test; specifically, the semiconductor chip under test at present is placed in the high-low temperature apparatus 103 on the handler 101;
the tester 102 is configured to test the semiconductor chips at different test temperatures respectively; the method is particularly used for testing various performances of the semiconductor chip; the semiconductor chip placed in the high and low temperature equipment 103 can be connected with the testing machine 102 through an external connecting wire, and the testing machine 102 provides power supply required by testing for the semiconductor chip through the external connecting wire and obtains various outputs of the semiconductor chip during testing; the outputs can include voltage and current magnitude, voltage and current frequency, withstand voltage value and the like, and test data of corresponding items can be obtained according to the outputs;
the sorting machine 101 is configured to sort the semiconductor chips, where the sorting basis is test data output by the testing machine 102, that is, the sorting basis is test data obtained by testing the semiconductor chips by the testing machine 102. The test data may specifically include accuracy of output current, accuracy of output voltage, chip withstand voltage, failure temperature, and the like.
Specifically, the sorting of the semiconductor chips by the sorter 101 includes marking and storing the semiconductor chips into a material pipe, and marking is to mark the semiconductor chips. In addition, the marking identification and the test data of the chip can be stored in an associated mode, so that all the test data of the semiconductor chip can be obtained in the later period by scanning the identification, and the test data can be conveniently extracted and analyzed in the later period. The sorter 101 stores the semiconductor chips in the corresponding feed tubes after the marking is completed. The sorting machine 101 may sort the semiconductor chips according to the test data output by the testing machine 102, or may obtain, by another device (e.g., a main control board), a sorting criterion (determined at least according to the sorting result) of the semiconductor chips according to the test data output by the testing machine 102, and then the sorting machine 101 sorts the semiconductor chips according to the sorting criterion.
Regarding the high-low temperature equipment 103, in the embodiment of the present invention, the functions of heating and cooling can be simultaneously realized, and the sealing equipment that can be mounted on the sorting machine 101 can be all used as the high-low temperature equipment 103 in the present application.
In the embodiment of the invention, the high-low temperature equipment 103 is arranged on the sorting machine 101, namely the high-low temperature equipment 103 and the sorting machine 101 are designed into an integral structure, so that the sorting machine 101 can test and sort the semiconductor chips and control the test temperature of the semiconductor chips, namely the semiconductor chips can be kept at the test position after reaching the test position in the high-low temperature equipment 103 on the sorting machine 101, and then the sorting machine 101 controls the test temperature of the semiconductor chips through the high-low temperature equipment 103, so that the semiconductor chips can be tested at different temperatures respectively, the automatic temperature scanning test of the semiconductor chips is realized, the labor cost is saved, and the test efficiency is improved.
In addition, each test of the semiconductor chip can be performed on a plurality of parameters of the semiconductor chip, so that the temperature characteristics of the plurality of parameters of the semiconductor chip can be obtained by one-time scanning by using the semiconductor chip multi-temperature automatic test system provided by the embodiment of the invention, and the later-stage temperature-related analysis on the plurality of performances of the semiconductor chip is facilitated.
In some embodiments, the semiconductor chip multi-temperature automatic test system further comprises: a main control panel;
the main control board is configured to control the high and low temperature equipment 103, the handler 101, and/or the tester 102.
Specifically, the main control board may be located in an independent upper computer, or may be integrated in a control computer of the sorting machine 101. When the master control board is located in an independent upper computer, the master control board and the sorting machine 101 can communicate with each other in a wireless or wired manner. The main control board and the high and low temperature devices 103 can communicate with each other in a wireless or wired manner. The main control board and the test machine 102 may communicate with each other wirelessly or by wire.
In some specific embodiments, the main control board controls the temperature of the high and low temperature device 103 according to a first test temperature and a step temperature input from the outside or preset inside to provide a plurality of different test temperatures for the semiconductor chip;
and/or the presence of a gas in the gas,
the main control board controls the tester 102 to test the semiconductor chips in the high-low temperature equipment 103; of course, the temperature in the high-low temperature equipment 103 needs to reach the temperature required by the current test;
and/or the presence of a gas in the gas,
the main control board obtains the sorting basis of the semiconductor chip according to the test data output by the test machine 102, and controls the sorting machine 101 to sort the semiconductor chip based on the sorting basis. Specifically, the tester 102 may send test data obtained by each test to the main control board after each test (the test for the semiconductor chip is a single test after each test temperature is adjusted) is completed. After all tests aiming at the semiconductor chip are finished, the main control board analyzes all test data of the semiconductor chip to obtain the sorting basis of the semiconductor chip.
The first test temperature may be a temperature at which the semiconductor chip is first tested, and may also be referred to as an initial test temperature.
Referring to fig. 2, an embodiment of the present invention provides a semiconductor chip multi-temperature automatic testing method, which is applied to a semiconductor chip multi-temperature automatic testing system, where the system includes a sorter 101 and a tester 102, the system further includes high and low temperature devices 103, and the high and low temperature devices 103 are installed in the sorter 101, that is, the high and low temperature devices 103 and the sorter 101 are integrated into an integrated structure, and the method includes:
s201: after detecting that a semiconductor chip is located at a test position in the high-low temperature equipment 103, the sorting machine 101 directly or indirectly sends a first instruction to the high-low temperature equipment 103; the first instruction may instruct the existing semiconductor chip to reach the test site, instruct the high-low temperature device 103 to start controlling the test temperature, or instruct the high-low temperature device 103 to adjust the current test temperature to the first test temperature;
specifically, a semiconductor chip to be tested may be placed in the high and low temperature device 103 on the handler 101 by a robot or manually, and may be specifically a test site in the high and low temperature device 103. A sensor may be provided in the high-low temperature apparatus 103 for detecting whether or not a semiconductor chip is placed on its test site;
s202: the high-low temperature equipment 103 adjusts the current test temperature to a first test temperature according to the first instruction; specifically, the adjustment may be heating or cooling; the first test temperature may be specified or preset;
of course, if the current temperature is already the first test temperature, then no adjustment is needed for the high and low temperature device 103, for example, if the first test temperature is 25 ℃, and the current temperature in the high and low temperature device 103 is exactly 25 ℃, then no temperature adjustment is needed, and only a temperature maintenance is needed.
For another example, the first test temperature may not be a fixed value, but only needs to be within a certain range, for example, any temperature value within 20 ℃ to 25 ℃ may be used as the first test temperature, and at this time, the current temperature in the high and low temperature device 103 is well within this range, so that temperature adjustment is not needed, and only temperature maintenance is needed. The next temperature adjustment may be made based on the current actual first test temperature, e.g., the current temperature is 26.1 ℃ and the step temperature is 2 ℃, then the temperature needs to be adjusted to 24.1 ℃ or 28.1 ℃ the next time;
s203: the testing machine 102 tests the semiconductor chip at the current testing temperature to obtain testing data at the current testing temperature;
s204: if the test for the semiconductor chip is not finished, the high-low temperature device 103 adjusts the current test temperature to another new test temperature; specifically, the new test temperature may be obtained by adding or subtracting a preset step temperature to or from the first test temperature;
repeating steps S203 and S204 until the test for the semiconductor chip is ended;
s205: the sorter 101 sorts the semiconductor chips according to test data obtained by testing the semiconductor chips by the tester 102.
The semiconductor chip multi-temperature automatic test system in the embodiment of the present invention may be any one of the semiconductor chip multi-temperature automatic test systems described in the above system embodiments, and therefore specific structures, functions, and the like may refer to the above system embodiments, which are not described herein again.
In the embodiment of the invention, the high-low temperature equipment 103 is arranged on the sorting machine 101, namely the high-low temperature equipment 103 and the sorting machine 101 are designed into an integral structure, so that the sorting machine 101 can test and sort the semiconductor chips and control the test temperature of the semiconductor chips, namely the semiconductor chips can be kept at the test position after reaching the test position in the high-low temperature equipment 103 on the sorting machine 101, and then the sorting machine 101 controls the test temperature of the semiconductor chips through the high-low temperature equipment 103, so that the semiconductor chips can be tested at different temperatures respectively, the automatic temperature scanning test of the chips is realized, the labor cost is saved, and the test efficiency is improved.
In some specific embodiments, the semiconductor chip multi-temperature automatic test system further comprises a main control board;
after detecting that a semiconductor chip is located in a test site in the high-temperature and low-temperature equipment 103, the handler 101 indirectly sends a first instruction to the high-temperature and low-temperature equipment 103, including:
after detecting that a semiconductor chip is located at a test position in the high-low temperature equipment 103, the sorting machine 101 sends the corresponding first instruction to the main control board; the first instruction may indicate that the existing semiconductor chip reaches the test bit;
the main control board forwards the first instruction to the high-low temperature equipment 103, or generates a new first instruction based on the first instruction and then sends the new first instruction to the high-low temperature equipment 103. Specifically, the new first instruction may instruct the high-low temperature device 103 to start controlling the testing temperature, or instruct the high-low temperature device 103 to adjust the current testing temperature to the first testing temperature.
In some other specific embodiments, in a case that the semiconductor chip multi-temperature automatic test system further includes a main control board, after the high-low temperature device 103 adjusts the current test temperature to the first test temperature according to the first instruction, the high-low temperature device 103 sends a signal that the current test temperature has been adjusted to the first test temperature to the main control board, and after the main control board receives the signal, the main control board sends an instruction to start testing to the test machine 102, and after the test machine 102 receives the instruction, the test machine 102 starts testing the semiconductor chip, so as to complete testing the semiconductor chip at the current test temperature (i.e., the first test temperature).
In some specific embodiments, in the case that the semiconductor chip multi-temperature automatic test system further includes a main control board, the tester 102 sends a first test end signal and various test data to the main control board after completing the test of the semiconductor chip at the current test temperature.
In addition, after the tester 102 completes testing the semiconductor chip at the current testing temperature and sends the first test end signal and various test data to the main control board, the main control board may send an instruction to adjust to another new testing temperature to the high and low temperature device 103.
In some specific embodiments, the main control board may determine whether the performance of the semiconductor chip at the current testing temperature is qualified according to the test data obtained by the current testing, that is, according to the test data obtained by the testing machine 102 testing the semiconductor chip at the current testing temperature, and if the performance of the semiconductor chip at the current testing temperature is judged to be unqualified, determine that the testing for the semiconductor chip is ended. Specifically, the main control board may determine whether the performance of the semiconductor chip at the current test temperature is qualified after receiving a first test end signal (indicating that the test at the current test temperature is completed) and various test data sent by the test machine 102. And when judging whether the performance of the semiconductor chip at the current test temperature is qualified or not, if the test data of one test item is not in the corresponding reference range, judging that the judgment result of the current test is unqualified.
In some embodiments, the conditions for ending the test are: the test data from the completed test indicates that the semiconductor chip is not acceptable or the completed test temperature satisfies the test requirements for the semiconductor chip (i.e., not because the semiconductor chip is not acceptable, but the test data from all tests indicates that the semiconductor chip is acceptable, but only because the test at all required test temperatures is completed). If only one of the two conditions is satisfied, the condition for ending the test is satisfied.
Specifically, if the semiconductor chip needs to be scan-tested within a certain temperature range (for example, -40 ℃ to 150 ℃), once the current testing temperature is changed by a preset step temperature until all selectable temperatures within the temperature range are used as the testing temperature to complete the testing of the semiconductor chip, the completed testing temperature is considered to meet the testing requirements of the semiconductor chip. For example, the temperature required for testing a semiconductor chip ranges from-40 ℃ to 150 ℃, and if the current testing temperature is gradually increased with-40 ℃ as the first testing temperature and 2 ℃ as the step temperature, the completed testing temperature is considered to satisfy the testing requirements of the semiconductor chip when the current testing temperature is increased to 150 ℃. For another example, the temperature required for testing the semiconductor chip ranges from-40 ℃ to 150 ℃, and if 30 ℃ is used as the first test temperature and 2 ℃ is used as the step temperature, the current test temperature is gradually decreased to-40 ℃, and then gradually increased to 150 ℃, and then when the current test temperature is increased to 150 ℃, the completed test temperature is considered to meet the test requirement of the semiconductor chip.
In some specific embodiments, the first test temperature is greater than 20 ℃ and less than 30 ℃; the highest test temperature meeting the test requirements of the semiconductor chip is a first temperature, the lowest test temperature is a second temperature, the first temperature is higher than the first test temperature, and the second temperature is lower than the first test temperature; after the current testing temperature of the high and low temperature equipment 103 is adjusted to the first testing temperature, the current testing temperature is first adjusted to the second temperature, and then the current testing temperature is adjusted to the first temperature according to a preset step temperature.
Optionally, each time the high-low temperature device 103 adjusts the current test temperature, the adjustment is performed according to an instruction of the main control board, that is, the instruction sent by the main control board indicates to which temperature the high-low temperature device 103 adjusts, and to which temperature the high-low temperature device 103 adjusts.
In the embodiment of the invention, each adjustment of the current test temperature requires testing the semiconductor chip at the adjusted test temperature. Specifically, after the current test temperature is adjusted to the first test temperature, the semiconductor chip at the first test temperature needs to be tested. After the current test temperature is adjusted to the second temperature, the semiconductor chip at the second temperature needs to be tested, and then, each time the temperature is adjusted according to the preset step temperature (for example, 2 ℃), the semiconductor chip at the current temperature needs to be tested once.
In the embodiment of the invention, in order to improve the efficiency of the temperature scan test, the first test temperature, that is, the initial test temperature of the semiconductor chip, is set to a temperature value greater than 20 ℃ and less than 30 ℃, specifically, the normal temperature is 25 ℃, because if the test result of the semiconductor chip at this temperature is not qualified, it is not necessary to perform high and low temperature tests on the semiconductor chip.
In addition, in the embodiment of the present invention, after adjusting the current test temperature to the first test temperature, the high-low temperature device 103 first adjusts to the second temperature, and then adjusts to the first temperature according to the preset step temperature, that is, the temperature is gradually raised from the lowest temperature to perform the temperature scanning test until reaching the highest temperature, which is for the reason that: at the lowest temperature (second temperature), the semiconductor chip may be frosted or water drops may be condensed on the surface of the chip, so that when a high-temperature test is performed later, the semiconductor chip and the sealed cavity of the high-low temperature device 103 are all baked, the frosting of the semiconductor chip or the condensation of the water drops caused by low temperature is avoided, and the safety and the reliability of the semiconductor chip test are improved.
In some specific embodiments, the temperature between the second temperature and the first temperature is divided into at least two temperature ranges, wherein the lowest temperature of the first temperature range is the second temperature, and the highest temperature is greater than or equal to the first test temperature;
the sorter 101 sorts the semiconductor chips, and includes:
the sorting machine 101 obtains a sorting basis; the sorting criterion is determined based at least on a grading result of the semiconductor chip, and the grading result is determined according to test data obtained by testing the semiconductor chip by the tester 102;
the sorting machine 101 sorts the semiconductor chips according to the sorting criterion;
and if the test temperature of the last test is not in the first temperature range when the test for the semiconductor chip is finished, obtaining the grading result of the semiconductor chip according to the judgment result of each test for the semiconductor chip. Specifically, first, a judgment result of each test is obtained according to test data obtained by each test of the semiconductor chip, and then a classification result of the semiconductor chip is obtained based on the judgment result of each test.
In addition, when the test temperature at the time of the last test is within the first temperature range (which indicates that the semiconductor chip is defective due to the test data obtained at the last test) at the time of the end of the test on the semiconductor chip, the classification result of the semiconductor chip may be considered to be defective. Specifically, the test temperature varies in the following manner: the test temperature of the first test is the first test temperature, and the subsequent test temperature is changed from the lowest second temperature to the highest first temperature, so that if the semiconductor chip is tested and failed at the lower test temperature, the semiconductor chip can be directly determined to be failed.
Specifically, the sorting criterion may be determined by the sorter 101 itself based on test data of the semiconductor chip.
Under the condition that the semiconductor chip multi-temperature automatic test system further comprises a main control board, the sorting basis can be obtained by analyzing the test data of the semiconductor chip by the main control board, and the main control board sends the sorting basis obtained by analysis to the sorting machine 101, so that the sorting machine 101 sorts the semiconductor chip according to the sorting basis. Alternatively, the specific form of the sorting basis sent by the main control board to the sorting machine 101 may be a marking identifier, that is, the marking identifier may indicate the sorting basis (the sorting basis may indicate the grading result). The judgment basis of the sorting criterion is all the test data of the semiconductor chip, so that the main control board can obtain the sorting criterion only after the test for the semiconductor chip is finished, and then the sorting criterion is sent to the sorter 101. In addition, the main control board may transmit a second test end signal indicating the end of the test on the semiconductor chip, simultaneously with the transmission of the marking flag to the handler 101.
After receiving the marking identifier and the second test end signal, the sorting machine 101 marks the semiconductor chip and stores the semiconductor chip in a corresponding material pipe, thereby completing the test and sorting of the semiconductor chip.
In some specific embodiments, the determination result includes a level a, a level B, and a level C, and the levels of the level a, the level B, and the level C decrease in sequence;
when obtaining a classification result of the semiconductor chip from a determination result for each test of the semiconductor chip: if the judgment result of at least N times of tests is A level, the grading result of the semiconductor chip is A level; if the judgment result of at least N times of tests is C grade, the grading result of the semiconductor chip is C grade; in other cases, the grading result of the semiconductor chip is B grade;
and N is a positive integer, and is greater than or equal to a preset value, wherein the preset value is greater than or equal to half of the number of completed tests.
For example, N may be two-thirds of the number of tests completed. The number of completed tests refers to the number of completed tests for the currently tested semiconductor chip.
In the embodiment of the invention, only when the test temperature in the last test is not in the first temperature range, the grading result of the semiconductor chip is obtained according to the judgment result of each test on the semiconductor chip, which indicates that the temperature scanning test at the moment scans the first temperature range, that is, the test on the semiconductor chip is carried out for a plurality of times.
In some specific embodiments, if the testing temperature at the last testing for the semiconductor chip is not within the first temperature range at the end of the testing for the semiconductor chip, the sorting criterion used for sorting the semiconductor chip is determined according to the grading result of the semiconductor chip and a failure temperature, and the failure temperature is determined according to the testing temperature at the end of the testing for the semiconductor chip and the reason for the end of the testing (that is, which condition for the end of the testing is satisfied causes the end of the testing). The test temperature at the end of the test of the semiconductor chip, that is, the test temperature at the time of the last test performed on the semiconductor chip.
As for the failure temperature of the semiconductor chip, there are two cases corresponding to two causes of the end of the test: 1. the condition of test ending is that the finished test temperature meets the test requirement of the semiconductor chip, and the failure temperature of the semiconductor chip is considered to be out of the test temperature range of all tests at the moment; 2. and the condition of the test ending is that the test data obtained by the finished test indicates that the semiconductor chip is unqualified, specifically, the test data obtained by the last test indicates that the semiconductor chip is unqualified, and at the moment, the test temperature at the test ending is the failure temperature of the semiconductor chip.
In some embodiments of the present invention, after a first test is performed on a semiconductor chip at a preset first test temperature, the test temperature of the semiconductor chip is reduced to a minimum test temperature (i.e., a second temperature), and then the temperature is slowly increased from the minimum test temperature according to a step temperature, so as to implement a temperature scan test on the semiconductor chip, thereby accurately obtaining a failure temperature of the semiconductor chip.
Specifically, all test temperatures required for the test, that is, temperatures between the second temperature and the first temperature, may be sequentially divided into four temperature ranges in the order from low to high: a first temperature range, a second temperature range, a third temperature range, and a fourth temperature range.
For example, when a semiconductor chip is tested, the test temperature of the semiconductor chip is generally designed to be-40 ℃ to 150 ℃. All test temperatures required for this test can be divided into a first temperature range [ -40 ℃,85 ℃ ], a second temperature range (85 ℃,105 ℃), a third temperature range (105 ℃,125 ℃), and a fourth temperature range (125 ℃,150 ℃).
The temperature level of the semiconductor chip may be classified into the following several levels according to the failure temperature of the semiconductor chip:
first-stage: the failure temperature of the semiconductor chip is out of the test temperature range of all tests, namely the test data of all tests which are completed indicate that the semiconductor chip is qualified;
and (2) second stage: a failure temperature in the fourth temperature range described above, e.g., between 125 ℃ and 150 ℃ (excluding 125 ℃ but including 150 ℃);
third-stage: a failure temperature within the third temperature range described above, e.g., between 105 ℃ and 125 ℃ (excluding 105 ℃ but including 125 ℃);
four stages: a failure temperature within the second temperature range described above, e.g., between 85 ℃ and 105 ℃ (excluding 85 ℃ but including 105 ℃);
and (5) fifth stage: the failure temperature is within the first temperature range described above, such as between-40 ℃ and 85 ℃ (including-40 ℃ and 85 ℃).
Sorting criteria for semiconductor chips: if the failure temperature is within the first temperature range, namely the temperature grade is five grades, the sorting criterion is directly unqualified (if the failure temperature is within the first temperature range, namely the testing temperature at the last test is within the first temperature range, the grading result of the semiconductor chip can be considered to be unqualified); if the failure temperature is in the other temperature range than the first temperature range, that is, if the temperature level of the semiconductor chip is any of the other four levels than the five levels, it is necessary to determine the sorting criterion in association with the sorting result and the temperature level of the semiconductor chip.
Specifically, when the sorting criterion is determined by combining the classification result and the temperature level of the semiconductor chip, if the temperature level is one level and the classification result is a level, the sorting criterion may be, for example, "1" or "a" or the like, and the sorter 101 may store the semiconductor chip in the first hopper; if the temperature grade is one grade and the grading result is grade B, the sorting machine 101 may store the semiconductor chip into a second material tube according to the sorting criterion, which may be "2" or "one B", for example; if the temperature grade is one grade and the grading result is grade C, the sorting machine 101 may store the semiconductor chip into a third material tube according to the sorting criterion, which may be "3" or "one C", for example; if the temperature grade is two grades and the grading result is a grade a, the sorting criterion may be, for example, "4" or "two a", etc., and the sorter 101 may store the semiconductor chip into the fourth material pipe, and so on, and store the semiconductor chips with the temperature grades from one grade to four grades into twelve corresponding material pipes, respectively. And if the temperature grade of the semiconductor chip is five grade, the sorter 101 stores it in the thirteenth material pipe.
In the embodiment of the invention, the sorting machine 101 stores the semiconductor chips according to the sorting basis, and the sorting basis is related to the temperature grades of the semiconductor chips, so that the convenience of sorting the semiconductor chips with different temperature grades is improved.
In some specific embodiments, the judgment result for each test of the semiconductor chip is obtained according to the following method:
for each test, respectively judging whether the test data of each test item is in the corresponding reference range;
if the test data of one test item is not in the corresponding reference range, the judgment result of the current test is unqualified; in the embodiment of the invention, the judgment result of only one test at most for the test of the semiconductor chip is unqualified, in particular, the judgment result of only the last test is possibly unqualified, because the test for the semiconductor chip is finished as long as the judgment result of one test is unqualified;
if the test data of all the test items are in the corresponding reference range, respectively calculating the difference value between the test data of each test item and the corresponding optimal reference value; determining a score for each of the test items according to the magnitude of the difference, the score being smaller the larger the difference (here, the absolute value); calculating a sum of the scores for each of the test items; and according to the total sum of the scores, the judgment result of the current test is the A level, the B level or the C level, and the total sums of the scores required by the A level, the B level and the C level are sequentially decreased. In the embodiment of the invention, for each test, if the test data of all the test items are in the corresponding reference range, the test result is considered to be qualified, or the judgment result of the test is considered to be qualified.
Specifically, when the score of each test item is determined according to the magnitude of the difference, if the difference is less than or equal to a first threshold, the score of the test item is a first score S1, if the difference is greater than the first threshold and less than or equal to a second threshold, the score of the test item is a second score S2, and if the difference is greater than the second threshold and less than or equal to a third threshold, the score of the test item is a third score S3. The first threshold, the second threshold and the third threshold are sequentially increased, and the first score S1, the second score S2 and the third score S3 are sequentially decreased, for example, the first score S1 is 3, the second score S2 is 2, and the third score S3 is 1.
When determining whether the judgment result of the current test is the A-stage, the B-stage or the C-stage according to the sum of the scores, if the sum of the scores is equal to M S1, the judgment result is the A-stage, if the sum of the scores is less than M S1 and greater than or equal to M S2, the judgment result is the B-stage, if the sum of the scores is less than M S2 and greater than or equal to M S3, the judgment result is the C-stage, wherein M is the number of the test items.
Optionally, the first threshold, the second threshold and the third threshold are different according to different test temperatures. Specifically, for each test (the test temperature for each test is different), the first threshold, the second threshold and the third threshold may be different when determining the score of each test item according to the magnitude of the difference.
The first threshold, the second threshold and the third threshold of each test item corresponding to different test temperatures can be set in the main control board in advance, and the main control board only needs to call the corresponding first threshold, the corresponding second threshold and the corresponding third threshold (including the first threshold, the corresponding second threshold and the corresponding third threshold of each test item) according to the current test temperature.
In some embodiments, the reference range varies with the test temperature. That is, the reference range corresponding to the test data of each test item obtained in each test is related to the test temperature during the test. This is because the test data of the semiconductor chip usually changes with the temperature change, such as the leakage voltage of the semiconductor chip, at low temperature, the leakage voltage is also lower due to the reduced electronic activity, and at high temperature, the leakage voltage is higher due to the improved electronic activity, so if only one reference range of the test data is set at all test temperatures, the test result will be deviated, therefore, in order to improve the test accuracy, better reflect the temperature characteristics of each item of test data of the semiconductor chip, and different reference ranges of the test data can be set according to the different test temperatures.
In addition, regardless of the reason why the test for the semiconductor chip is finished, the temperature of the semiconductor chip needs to be adjusted to a preset temperature, which may be 20 to 30 ℃, before the sorter 101 marks the semiconductor chip. This is because if the semiconductor chip is marked while it is at a high temperature, a further increase in the temperature of the semiconductor chip may result, possibly damaging the chip. Of course, in some alternative embodiments, the temperature of the semiconductor chip may be adjusted to the preset temperature only when the testing temperature at the end of the testing is greater than the preset temperature, and at this time, the preset temperature may be set to 30 ℃ in order to improve the efficiency of the whole testing process (including marking).
Specifically, after the test for the semiconductor chip is completed, the main control board may first send an instruction for adjusting the temperature to the preset temperature to the high-low temperature device 103. The high-low temperature equipment 103 adjusts the temperature to a preset temperature after receiving the instruction, and then sends a signal indicating that the temperature has been adjusted to the preset temperature to the main control board. After receiving the signal, the main control board sends a second test end signal to the high-low temperature equipment 103, and after receiving the second test end signal, the high-low temperature equipment 103 automatically opens the upper cover of the sealed cavity of the high-low temperature equipment 103 to expose the semiconductor chip, so that subsequent marking and taking-out operations are facilitated. Thereafter, the main control board sends a second test end signal and a marking flag to the handler 101.
Alternatively, after the test for the semiconductor chip is completed, the main control board may first send a command for adjusting the temperature to the preset temperature to the high-low temperature device 103. The high-low temperature equipment 103 adjusts the temperature to a preset temperature after receiving the instruction, and then sends a signal indicating that the temperature has been adjusted to the preset temperature to the main control board. The main control board sends a second test end signal and a marking identifier to the handler 101 after receiving the signal. After receiving the second test end signal and the marking identifier, the sorter 101 opens the upper cover of the sealed cavity of the high and low temperature device 103 through the mechanical arm, and exposes the semiconductor chip.
The semiconductor chip multi-temperature automatic test method according to the embodiment of the invention is described for one semiconductor chip, and the above method flow is repeatedly executed for testing other semiconductor chips, which is not described herein again.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (12)
1. The utility model provides a semiconductor chip multiple temperature automatic test system, includes sorter and test machine, its characterized in that still includes: high and low temperature equipment, and the high and low temperature equipment is installed in the separator; wherein the content of the first and second substances,
the high-low temperature equipment is used for providing various different testing temperatures for the semiconductor chip;
the tester is used for testing the semiconductor chips at different testing temperatures respectively;
the sorting machine is used for sorting the semiconductor chips, and the sorting basis is the test data output by the testing machine.
2. The system of claim 1, further comprising: a main control panel;
the main control board is used for controlling the high-low temperature equipment, the sorting machine and/or the testing machine.
3. The system of claim 2, wherein the main control board controls the temperature of the high and low temperature devices according to a first test temperature and a step temperature input from outside or preset inside to provide a plurality of different test temperatures for the semiconductor chip; and/or the presence of a gas in the atmosphere,
the main control board controls the tester to test the semiconductor chip in the high-low temperature equipment; and/or the presence of a gas in the gas,
the main control board obtains the sorting basis of the semiconductor chips according to the test data output by the testing machine, and controls the sorting machine to sort the semiconductor chips based on the sorting basis.
4. A semiconductor chip multi-temperature automatic test method is characterized in that the method is applied to a semiconductor chip multi-temperature automatic test system, the system comprises a sorting machine and a testing machine, the system also comprises high-low temperature equipment, and the high-low temperature equipment is arranged in the sorting machine, and the method comprises the following steps:
s201: the sorting machine directly or indirectly sends a first instruction to the high-low temperature equipment after detecting that the semiconductor chip is located at the test position in the high-low temperature equipment;
s202: the high-low temperature equipment adjusts the current test temperature to a first test temperature according to the first instruction;
s203: the testing machine tests the semiconductor chip at the current testing temperature to obtain testing data at the current testing temperature;
s204: if the test for the semiconductor chip is not finished, the high-low temperature equipment adjusts the current test temperature to another new test temperature;
repeating steps S203 and S204 until the test for the semiconductor chip is ended;
s205: the sorting machine sorts the semiconductor chips according to test data obtained by testing the semiconductor chips by the testing machine.
5. The method of claim 4, wherein the semiconductor chip multi-temperature automated test system further comprises a main control board;
after detecting that a semiconductor chip is located at a test position in the high-low temperature equipment, the sorting machine indirectly sends a first instruction to the high-low temperature equipment, and the method comprises the following steps:
after detecting that a semiconductor chip is located at a test position in the high-low temperature equipment, the sorting machine sends the corresponding first instruction to the main control board;
the main control board forwards the first instruction to the high and low temperature equipment, or generates a new first instruction based on the first instruction and then sends the first instruction to the high and low temperature equipment.
6. The method according to claim 4, characterized in that the conditions for the end of the test are: the completed test temperature satisfies the test requirements for the semiconductor chip or the test data from the completed test indicates that the semiconductor chip is not acceptable.
7. The method of claim 6, wherein the first test temperature is greater than 20 ℃ and less than 30 ℃; the highest test temperature meeting the test requirements of the semiconductor chip is a first temperature, the lowest test temperature is a second temperature, the first temperature is higher than the first test temperature, and the second temperature is lower than the first test temperature; after the current testing temperature of the high-low temperature equipment is adjusted to the first testing temperature, the high-low temperature equipment is firstly adjusted to the second temperature, and then the high-low temperature equipment is adjusted to the first temperature according to a preset stepping temperature.
8. The method of claim 7, wherein the temperature between the second temperature and the first temperature is divided into at least two temperature ranges, wherein the lowest temperature of the first temperature range is the second temperature and the highest temperature is greater than or equal to the first test temperature;
the sorter sorts the semiconductor chips, including:
the sorting machine obtains a sorting basis; the sorting criterion is determined at least based on a grading result of the semiconductor chip, and the grading result is determined according to test data obtained by testing the semiconductor chip by the testing machine;
the sorting machine sorts the semiconductor chips according to the sorting basis;
if the test temperature of the last test is not within the first temperature range after the test of the semiconductor chip is finished, the grading result of the semiconductor chip is obtained according to the judgment result of each test of the semiconductor chip.
9. The method according to claim 8, wherein the determination result includes a level a, a level B, and a level C, and the levels of the level a, the level B, and the level C decrease in order;
when obtaining a classification result of the semiconductor chip from a determination result for each test of the semiconductor chip: if the judgment result of at least N times of tests is A level, the grading result of the semiconductor chip is A level; if the judgment result of at least N times of tests is C level, the grading result of the semiconductor chip is C level; in other cases, the grading result of the semiconductor chip is grade B;
and N is a positive integer, and N is greater than or equal to a preset value, wherein the preset value is greater than or equal to half of the number of completed tests.
10. The method according to claim 8, wherein if the test temperature at the last test for the semiconductor chip is not within the first temperature range at the end of the test, the sorting criterion used in sorting the semiconductor chips is determined according to the result of the sorting of the semiconductor chips and a failure temperature determined according to the test temperature at the end of the test of the semiconductor chips and the reason for the end of the test.
11. The method of claim 8, wherein the determination result for each test of the semiconductor chip is obtained according to the following method:
for each test, respectively judging whether the test data of each test item is in the corresponding reference range;
if the test data of one test item is not in the corresponding reference range, the judgment result of the current test is unqualified;
if the test data of all the test items are in the corresponding reference ranges, respectively calculating the difference value between the test data of each test item and the corresponding optimal reference value; determining the score of each test item according to the difference, wherein the larger the difference is, the smaller the score is; calculating a sum of the scores for each of the test items; and according to the total sum of the scores, judging whether the current test result is the grade A, the grade B or the grade C, and sequentially decreasing the total sum of the scores required by the grade A, the grade B and the grade C.
12. The method of claim 11, wherein the reference range varies with test temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211109485.9A CN115542110A (en) | 2022-09-13 | 2022-09-13 | Multi-temperature automatic test system and method for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211109485.9A CN115542110A (en) | 2022-09-13 | 2022-09-13 | Multi-temperature automatic test system and method for semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115542110A true CN115542110A (en) | 2022-12-30 |
Family
ID=84725139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211109485.9A Pending CN115542110A (en) | 2022-09-13 | 2022-09-13 | Multi-temperature automatic test system and method for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115542110A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116069085A (en) * | 2023-03-06 | 2023-05-05 | 杭州芯云半导体技术有限公司 | Temperature control device and method for centralized cooling of multiple groups of semiconductor test equipment |
| CN117686888A (en) * | 2024-01-24 | 2024-03-12 | 苏州贝克微电子股份有限公司 | Three-temperature test method, device, equipment and medium for semiconductor chip |
-
2022
- 2022-09-13 CN CN202211109485.9A patent/CN115542110A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116069085A (en) * | 2023-03-06 | 2023-05-05 | 杭州芯云半导体技术有限公司 | Temperature control device and method for centralized cooling of multiple groups of semiconductor test equipment |
| CN117686888A (en) * | 2024-01-24 | 2024-03-12 | 苏州贝克微电子股份有限公司 | Three-temperature test method, device, equipment and medium for semiconductor chip |
| CN117686888B (en) * | 2024-01-24 | 2024-05-07 | 苏州贝克微电子股份有限公司 | Three-temperature test method, device, equipment and medium for semiconductor chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115542110A (en) | Multi-temperature automatic test system and method for semiconductor chip | |
| US7633288B2 (en) | Method of testing semiconductor devices and handler used for testing semiconductor devices | |
| US5877419A (en) | Method for estimating the service life of a power semiconductor component | |
| CN109860069B (en) | Wafer testing method | |
| CN108445371B (en) | Method for pre-sorting service life of insulated gate bipolar transistor | |
| CN113656972B (en) | Sequence equivalence-based long-life acceleration verification method for single satellite-borne electronic machine | |
| US7230417B2 (en) | Test system of semiconductor device having a handler remote control and method of operating the same | |
| CN105203941B (en) | The method of inspection of wafer sort special pattern and probe card defect | |
| CN112871759B (en) | Lithium battery voltage drop evaluation method and system | |
| CN102053089A (en) | Automatic visual inspection method | |
| CN110244695A (en) | The ageing management system of frequency-variable controller | |
| JP3613596B2 (en) | Stability analysis method for semiconductor device inspection equipment | |
| US6600329B2 (en) | Method for inspecting electrical properties of a wafer and apparatus therefor | |
| US6483334B1 (en) | Method for reliability testing of semiconductor IC | |
| US11946978B2 (en) | Method, apparatus and computer program product for estimating the service life of battery storage systems | |
| US20070296430A1 (en) | Control method and control program for prober | |
| CN201716335U (en) | Ageing testing box and ageing testing system | |
| KR102546233B1 (en) | Wafer test apparatus and test method of the same | |
| CN115078922A (en) | MLCC pressure resistance testing method and MLCC testing machine | |
| US7408339B2 (en) | Test system of semiconductor device having a handler remote control and method of operating the same | |
| CN110879114B (en) | Vehicle-mounted air conditioner refrigerant filling detection method and system | |
| KR20050030346A (en) | Method and system for classification of defect | |
| CN102081138A (en) | Method for wafer-level burn-in test of semiconductor devices | |
| US6639418B2 (en) | Microelectronic fabrication die electrical probe apparatus electrical test method providing enhanced microelectronic fabrication die electrical test accuracy and efficiency | |
| US10794955B2 (en) | Methods and systems for testing a tester |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |