KR102546233B1 - Wafer test apparatus and test method of the same - Google Patents

Abstract

The present technology discloses a wafer test apparatus and a test method thereof. The wafer test apparatus according to the present technology supplies an electrical signal to a loaded wafer to interlock with a probe station and a test server that performs a plurality of processes on the wafer to check the test progress of the wafer loaded in the probe station. After selecting a subsequent process to be applied to the corresponding wafer, a test station may be included to control the operation of the probe station according to the selected process.

Description

Wafer test device and its test method {WAFER TEST APPARATUS AND TEST METHOD OF THE SAME}

The present invention relates to a wafer test apparatus and a test method thereof, and more particularly, to perform a wafer test while automatically selecting a subsequent process in conjunction with a server while continuously maintaining a wafer loading state in the same wafer test apparatus. It relates to a wafer test apparatus and method capable of continuously performing a plurality of processes for

BACKGROUND OF THE INVENTION [0002] In general, a process of inspecting whether or not electrical performance of semiconductor chips is abnormal is included in a process of manufacturing semiconductor chips from a wafer.

In order to increase the efficiency of such a test process, it is important to find ways to improve productivity, yield, and quality. In particular, it is important to discover methods for efficiently using test process equipment to improve productivity, and various methods are being reviewed.

An object of the present invention is to provide a new test device and test method capable of improving productivity by reducing TAT (Turn Around Time) by simplifying the test process by improving test process control at the wafer level.

A wafer test apparatus according to an embodiment of the present invention performs a plurality of processes on the wafer by supplying an electrical signal to the loaded wafer in conjunction with a probe station and a test server to test the wafer loaded in the probe station. A test station may include a test station that determines a progress state, selects a subsequent process to be applied to the corresponding wafer, and then controls an operation of the probe station according to the selected process.

A wafer test method of a wafer test apparatus according to an embodiment of the present invention includes performing a first process on a loaded wafer, generating a data file for a result of the first process and uploading it to a data server, The method may include selecting a second process that is a subsequent process of the first process in conjunction with the test server while maintaining a state in which the wafer is loaded, and performing the selected second process.

A wafer test method of a wafer test apparatus according to another embodiment of the present invention includes the steps of checking whether a log file for a first process for testing a currently loaded wafer exists in a test server and whether the log file exists. It may include selectively performing any one of the first process or a second process that is a subsequent process of the first process according to the above.

The present invention can improve productivity by reducing TAT (Turn Around Time) by simplifying the test process.

1 is a configuration diagram showing the configuration of a wafer test system according to an embodiment of the present invention.
Figure 2 is a view showing the configuration of any one of the wafer test apparatus of Figure 1 in more detail.
3 is a flowchart illustrating a test method of a test apparatus according to an embodiment of the present invention;

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing an embodiment of the present invention, if it is determined that a detailed description of a related known configuration or function hinders understanding of the embodiment of the present invention, the detailed description thereof will be omitted.

1 is a configuration diagram showing the configuration of a wafer test system according to an embodiment of the present invention.

The wafer test system of FIG. 1 includes a plurality of wafer test devices 110 , 120 , and 130 and a test server 200 .

The wafer test devices 110, 120, and 130 are connected to the test server 200 through the network 10, and interwork with the test server 200 through bi-directional data communication for information about the wafer to be tested loaded on the stage. It performs various processes for test and repair (eg, probe test, rupture, etc.). When the test process is completed, the wafer test devices 110 , 120 , and 130 generate data files (log files and memory repair data) for the test results and transmit them to the test server 200 . The wafer test devices 110, 120, and 130 first check the log file for the wafer stored in the test server 200 before performing a new process on the loaded wafer to check the test progress of the wafer. and, based on the result, a program (logic) to proceed with the next process is automatically selected and the corresponding process is executed. At this time, the wafer test devices 110 , 120 , and 130 may download and use the selected program from the test server 200 . In particular, when performing a smart selection function that automatically selects and proceeds with a subsequent process, the wafer test apparatus 100 may continue to perform the subsequent process without unloading the loaded wafer. That is, in the prior art, when a plurality of processes are continuously performed, when one process is completed, an operator unloads a wafer and manually selects a program for the next process, but the wafer test devices 110, 120, 130) may automatically select a program for a subsequent process in conjunction with the test server 200 in a state in which the wafer is loaded and proceed with the selected process.

The test server 200 performs bi-directional data communication with the wafer test devices 110, 120, and 130 through the network 10 to obtain information about test results of each wafer from the wafer test devices 110, 120, and 130. A data file is received and stored for each wafer ID, and necessary data is provided to the wafer test apparatus 100 through the network 10 according to a request of the wafer test apparatuses 110 , 120 , and 130 .

FIG. 2 is a diagram showing the configuration of one 110 of the wafer test apparatuses 110, 120, and 130 of FIG. 1 in more detail. For convenience of description, only one wafer test apparatus 110 is described in this embodiment, but other wafer test apparatuses 120 and 130 may have the same configuration.

The wafer test apparatus 110 includes a test station 112 and a probe station 114 .

The test station 112 interworks with the test server 200 to determine the test progress of the wafer currently loaded in the probe station 114 and automatically sets up a program for the subsequent process to be applied to the corresponding wafer accordingly. After selection, the probe station 114 is controlled according to the corresponding program to perform the corresponding subsequent process. For example, when a wafer is newly loaded into a chuck of the probe station 114 or when a specific process for a previously loaded wafer is completed, the test station 112 stores the corresponding wafer stored in the test server 200. It checks the log file for the wafer to understand the test progress for the wafer, and automatically selects the program (logic) to proceed with the subsequent process according to the result. To this end, when the process is completed, the test station 112 generates a data file (log file, memory repair data) for the result and transmits it to the test server 200. In particular, when several processes are continuously performed, the test station 112 continuously performs corresponding processes while the wafer is loaded in the probe station 114 without an unloading process. For example, when a wafer is loaded, the test station 112 tests whether or not there are defective cells for each chip on the wafer, and then ruptures the wafer according to the test result while maintaining the loading state of the wafer without unloading the wafer. It is possible to perform a rupture and test the repair result by the rupture while the corresponding wafer is also continuously loaded. When performing the rupture, the test station 112 receives memory repair data (MRD) from the test server 200 and performs the rupture according to the corresponding data.

The probe station 114 supplies electrical signals to the chip area of the wafer according to the test control signal from the test station 112 to perform a probe test and rupture on the chip area of the wafer. The probe station 114 may include a chuck for supporting and moving the loaded wafer and a probe card having probe needles electrically contacting a chip area of the wafer loaded on the chuck. At this time, the probes formed on the probe card have sharp ends so as to make point contact with the chip region of the wafer, are formed to have a predetermined elasticity, and are formed of a metal material having excellent electrical conductivity.

3 is a flow chart for explaining a wafer test method according to an embodiment of the present invention, and a test method for a wafer test apparatus having the above configuration will be described in more detail using this flow chart.

For convenience of explanation, in this embodiment, a case in which the wafer test apparatus 100 is a device capable of performing defect inspection (first process) and rupture and repair inspection (second process) will be exemplarily described.

When the wafer is loaded onto the chuck of the probe station 114, the test station 112 recognizes the ID of the loaded wafer (step 310).

When the wafer ID recognition is completed, the test station 112 checks whether a log file corresponding to the corresponding wafer ID exists in the test server 200 to determine the test progress of the corresponding wafer (step 320). ).

That is, the wafer loaded into the probe station 114 is a wafer first loaded into the wafer test equipment 100 according to the present embodiment, or a wafer loaded again after unloading and performing only the first process in the wafer test equipment 100 for convenience. It may be a wafer or a wafer that is waiting to proceed with a second process in a continuously loaded state without being unloaded after completing the first process. Therefore, the test station 112 uses the test server 200 to check whether the currently loaded wafer is a wafer loaded for the first time and should start with the first process or a wafer that has already undergone the first process. Connect to and check whether a log file for the wafer exists.

At this time, if the log file for the first process does not exist in the test server 200, the test station 112 determines that the corresponding wafer is the first loaded wafer, and if the log file for the first process exists In , since the corresponding wafer has already been subjected to the first process, it is determined that the wafer is to be subjected to the second process, which is a subsequent process.

As described above, when the log file for the first process does not exist in the test server 200, the test station 112 selects a program for executing the first process and then probes the probe station 114 according to the program. is controlled to perform the first process (step 330).

For example, the test station 112 controls the operation of the probe station 114 to apply test power to each chip of the wafer loaded in the probe station 114 and receives a result thereof to determine whether each chip operates normally. to test

When the first process is completed, the test station 112 generates a data file for test results and uploads the created data file to the test server 200 (step 340).

For example, the test station 112 generates a log file for the first process and memory repair data MRD for the test result and transmits them to the test server 200 .

After the test station 112 transmits the data file to the test server 200, it returns to step 310 described above.

That is, when the unloading of the corresponding wafer is not requested from the outside, the test station 112 returns to the above-described step 310 while basically maintaining the state in which the corresponding wafer is loaded in the probe station 114, and proceeds to the subsequent process. continue to

The test station 112 recognizes the ID of the wafer again while the wafer is still being loaded, and then connects to the test server 200 and checks whether a log file corresponding to the wafer ID exists to test the corresponding wafer. Keep track of your progress.

In this case, since the log file for the first process is uploaded to the test server 200 in step 340, that is, since the log file for the first process exists in the test server 200, the test station 112 It is known that the corresponding wafer is a wafer to be processed in the second process.

If it is determined that the corresponding wafer is a wafer to be subjected to the second process, the test station 112 selects a program for performing the second process and then proceeds with subsequent processes according to the corresponding program.

Accordingly, the test station 112 first checks whether the corresponding wafer is a repair target wafer (step 350).

For example, the test station 112 downloads memory repair data (MRD) for a corresponding wafer from the test server 200 and checks whether there are chips to be repaired in the corresponding wafer.

At this time, when the corresponding wafer is not a repair target, the test station 112 ends the test.

However, when the corresponding wafer is subject to repair, the test station 112 performs rupture on the corresponding chips using the memory repair data (step 360), and then repairs the repaired chips to check whether or not the repair has been performed normally. A test is performed on (step 370).

In the above-described embodiment, the case of performing the rupture and repair inspection is described as an example of the second process for convenience of explanation, but is not limited thereto. For example, the second process may include a contact check process, a process for changing a test environment such as prober temperature, and bias trimming.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present invention.

Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

10: network
110, 120, 130: wafer test device
112: test station
114: probe station
200: test server

Claims (17)

a probe station supplying electrical signals to the loaded wafer to perform a plurality of processes on the wafer; and
A test station interworking with a test server to determine the test progress of the wafer loaded in the probe station, select a subsequent process to be applied to the wafer, and then control the operation of the probe station according to the selected process;
The test station
The wafer test apparatus controls the probe station so that a second process proceeds after the first process, wherein the second process selectively proceeds according to whether a log file for the first process exists in the test server. delete ◈Claim 3 was abandoned when the registration fee was paid.◈ 2. The method of claim 1, wherein the test station
When the first process is completed, the wafer test apparatus, characterized in that for transmitting the data file for the first process execution result to the test server. ◈Claim 4 was abandoned when the registration fee was paid.◈ 4. The method of claim 3, wherein the test station
Wafer test apparatus characterized in that for transmitting a log file and memory repair data (MRD) for the first process execution as the data file to the test server. ◈Claim 5 was abandoned when the registration fee was paid.◈ 5. The method of claim 4, wherein the test station
When the second process is performed, the wafer test apparatus, characterized in that for receiving the memory repair data for the corresponding wafer from the test server and proceeding accordingly. ◈Claim 6 was abandoned when the registration fee was paid.◈ 2. The method of claim 1, wherein the test station
When the first process is completed, while the wafer is continuously loaded into the probe station, whether or not the second process is performed is checked to select a corresponding program, and the probe station is controlled according to the selected program to perform the second process. Wafer test apparatus, characterized in that in progress. ◈Claim 7 was abandoned when the registration fee was paid.◈ 2. The method of claim 1, wherein the test station
After recognizing the ID of the wafer loaded in the probe station, the wafer test apparatus is connected to the test server to check whether a log file corresponding to the ID exists. ◈Claim 8 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the probe station
Wafer test apparatus, characterized in that for performing a probe test and rupture on the wafer under the control of the test station. After recognizing the ID of the loaded wafer, using the recognized ID, checking whether a log file for the first process exists in the test server;
performing the first process when the log file does not exist;
generating a data file for the result of the first process and uploading it to the test server;
selecting a second process that is a successor process of the first process in conjunction with the test server while maintaining the state in which the wafer is loaded; and
A wafer test method of a wafer test apparatus comprising the step of performing the selected second process. delete ◈Claim 11 was abandoned when the registration fee was paid.◈ According to claim 9,
Uploading the data file to the test server
A wafer test method of a wafer test device, characterized in that for transmitting a log file and memory repair data (MRD) for the first process to the test server. ◈Claim 12 was abandoned when the registration fee was paid.◈ 10. The method of claim 9, wherein selecting the second process comprises:
In a state where the wafer that has completed the first process is loaded, the ID of the wafer is recognized, and the existence of the log file for the first process is checked in the test server using the recognized ID. A wafer test method of a wafer test apparatus, characterized in that the second process is selected. ◈Claim 13 was abandoned when the registration fee was paid.◈ According to claim 9,
Before performing the second process, the wafer test method of the wafer test apparatus, characterized in that it further comprises the step of receiving and confirming the memory repair data for the corresponding wafer from the test server. ◈Claim 14 was abandoned when the registration fee was paid.◈ 10. The method of claim 9, wherein the first process
A wafer test method of a wafer test apparatus, characterized in that the probe test for checking whether or not each chip of the wafer is defective. ◈Claim 15 was abandoned when the registration fee was paid.◈ 15. The method of claim 14, wherein the second process
A wafer test method of a wafer test apparatus, comprising a rupture for repairing a defective chip and a test after repair, a contact check process, a process of changing a test environment, and bias trimming. checking whether a log file for a first process for testing a currently loaded wafer exists in a test server; and
A wafer test method of a wafer test apparatus comprising the step of selectively performing either the first process or a second process subsequent to the first process according to whether the log file exists. ◈Claim 17 was abandoned when the registration fee was paid.◈ According to claim 16,
Performing the first process when the log file for the first process does not exist in the test server, and performing the second process when the log file for the first process exists in the test server Wafer test method of a wafer test apparatus, characterized in that.

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