CN115527974A - Packaging structure, packaging structure manufacturing method and electronic device - Google Patents

Packaging structure, packaging structure manufacturing method and electronic device Download PDF

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Publication number
CN115527974A
CN115527974A CN202211230905.9A CN202211230905A CN115527974A CN 115527974 A CN115527974 A CN 115527974A CN 202211230905 A CN202211230905 A CN 202211230905A CN 115527974 A CN115527974 A CN 115527974A
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CN
China
Prior art keywords
arc
base island
segment
chip
groove
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Pending
Application number
CN202211230905.9A
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Chinese (zh)
Inventor
何正鸿
张超
高源�
姜滔
王承杰
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Yongsi Semiconductor Ningbo Co ltd
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Yongsi Semiconductor Ningbo Co ltd
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Priority to CN202211230905.9A priority Critical patent/CN115527974A/en
Publication of CN115527974A publication Critical patent/CN115527974A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4896—Mechanical treatment, e.g. cutting, bending
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29021—Disposition the layer connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The disclosure provides a packaging structure, a manufacturing method of the packaging structure and an electronic device, and relates to the technical field of semiconductors. The packaging structure comprises a lead frame, a chip and a plastic package body, wherein the lead frame comprises a pin and a base island, and the pin comprises a first section and a second section which are mutually insulated; the chip is arranged on the base island; the chip is electrically connected with the base island and the first segment respectively, and the base island is electrically connected with the second segment; the plastic package body covers the lead frame and the chip, a groove is formed in one side, close to the base island, of the plastic package body, and the groove is located between the base island and the pin. The arrangement is favorable for improving the bonding force of the packaging structure and the circuit board and preventing the layering or the fracture of the pins.

Description

Packaging structure, packaging structure manufacturing method and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a packaging structure, a manufacturing method of the packaging structure and an electronic device.
Background
The existing Quad Flat No-lead Package (QFN) product has low reliability because the leads or the connecting ends are not easy to see during soldering, and it is impossible to confirm whether the QFN product is successfully soldered on the circuit board. After some reliability tests, the pins at the welding part of the QFN product and the circuit board are layered or broken easily, so that the product fails.
Disclosure of Invention
The invention aims to provide a packaging structure, a packaging structure manufacturing method and an electronic device, which can improve the bonding force of the QFN packaging structure and a circuit board and enhance the connection reliability.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a package structure, including:
a lead frame including a pin and a base island, the pin including a first segment and a second segment insulated from each other;
the chip is arranged on the base island; the chip is respectively electrically connected with the base island and the first segment, and the base island is electrically connected with the second segment;
the plastic package body covers the lead frame and the chip, a groove is formed in one side, close to the base island, of the plastic package body, and the groove is located between the base island and the pins.
In an alternative embodiment, the pin further comprises an insulating gel disposed between the first segment and the second segment and used to connect the first segment and the second segment.
In an alternative embodiment, the first segment is remote from the base island relative to the second segment.
In an alternative embodiment, the chip is electrically connected to the first segment by a first arc, and the second segment is electrically connected to the base island by a second arc; the second wire arc is grounded, and the highest point of the second wire arc is higher than the surface of one side of the chip far away from the base island;
or the highest point of the second line arc is lower than or equal to the surface of one side of the chip far away from the base island.
In an alternative embodiment, the second arc is at least partially disposed within the recess.
In an alternative embodiment, the distance between the lowest point of the second line arc and the bottom surface of the base island is less than or equal to the thickness of the base island.
In an alternative embodiment, the second arc has one or more peaks and one or more valleys; the plane where the first arc is located is intersected with the plane where the second arc is located, and the first arc penetrates through a wave crest or a wave trough;
or the plane where the first arc is located is parallel to the plane where the second arc is located, the first arc is located between the two second arcs, and the highest point of each second arc is higher than that of each first arc.
In an alternative embodiment, the base islands are made of a conductive material.
In a second aspect, the present invention provides a method for manufacturing a package structure, including:
providing a lead frame; wherein the lead frame comprises a pin and a base island;
mounting a chip on the base island;
forming a first wire arc between the chip and the pin, and forming a second wire arc between the base island and the pin;
forming a plastic package body outside the chip and the lead frame;
and forming a groove on one side of the plastic package body close to the base island to expose the second wire arc.
In an alternative embodiment, the method further comprises:
after the step of forming a plastic package body outside the chip and the lead frame, cutting the pins to form independent first and second segments; wherein a cutting groove is formed between the first section and the second section;
and filling insulating colloid in the cutting groove.
In an alternative embodiment, the method further comprises:
and filling conductive adhesive in the groove.
In a third aspect, the present invention provides an electronic device, comprising a circuit board and the package structure as described in any of the previous embodiments, wherein the circuit board is provided with a first pad and a second pad, and the first pad is electrically connected to the first segment;
at least one of the second segment and the base island is electrically connected to the second pad; and/or the second section is electrically connected with the base island by adopting a second wire arc, the second wire arc is at least partially exposed out of the groove, and the second wire arc in the groove is electrically connected with the second bonding pad.
The beneficial effects of the embodiment of the invention include, for example:
according to the packaging structure provided by the embodiment of the invention, the groove is formed in the plastic packaging body between the base island and the pin, and solder can be filled in the groove during welding, so that the contact area with the solder is increased, and the welding reliability is improved. And simultaneously, the bonding force between the circuit board and the plastic package body is increased. And secondly, the pins comprise a first section and a second section, and the first section and the second section are respectively welded with the circuit board, so that the binding force between the pins and the circuit board is improved. The packaging structure can improve the binding force between the lead frame and the circuit board, is more reliable in connection, and effectively prevents the problem of product failure caused by layering or breakage between the pins and the circuit board in the prior art.
According to the manufacturing method of the packaging structure, the groove is formed in the plastic packaging body between the base island and the pin, the second arc is exposed out of the groove, the bonding force between the packaging structure and the circuit board is improved, and the reliability is higher. And the second wire arc is exposed from the groove, so that the electric connection points of the circuit board and the packaging structure are increased, the connection range is larger, the connection precision requirement is lower, and the reliability is better.
The electronic device provided by the embodiment of the invention comprises the packaging structure and the circuit board, so that the connection reliability is favorably improved, the product quality is good, and the qualification rate is high.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic view of an application scenario of a package structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a first structure of a package structure according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of another view angle of a first structure of a package structure according to an embodiment of the invention;
fig. 4 is a schematic diagram of a second structure of a package structure according to an embodiment of the invention;
fig. 5 is a schematic diagram of a layout structure of first arcs and second arcs of a package structure according to an embodiment of the present invention;
fig. 6 is a first schematic view illustrating a manufacturing method of a package structure according to an embodiment of the invention;
fig. 7 is a schematic diagram illustrating a second method for manufacturing a package structure according to an embodiment of the invention.
Icon: 100-a package structure; 110-a lead frame; 120-pin; 121-a first segment; 123-a second section; 125-cutting groove; 127-insulating colloid; 130-base island; 131-a frame; 140-a chip; 141-first line arc; 143-second line arc; 145-third arc; 150-plastic package body; 151-grooves; 160-protective film; 161-adhesive; 200-a circuit board; 210-a first pad; 220-a second pad; 230-conductive glue.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the product of the present invention is used to usually place, it is only for convenience of description and simplification of the description, but it is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1 to 3, the present invention provides a package structure 100 suitable for a QFN structure, wherein the package structure 100 is used for connecting with a circuit board 200.
The package structure 100 includes a lead frame 110, a chip 140 and a molding body 150, wherein the lead frame 110 includes a lead 120 and a base island 130, and the lead 120 includes a first segment 121 and a second segment 123 insulated from each other. The chip 140 is arranged on the base island 130; the chip 140 is electrically connected to the base island 130 and the first segment 121, and the base island 130 and the second segment 123, respectively. The plastic package body 150 covers the lead frame 110 and the chip 140, and the plastic package body 150 is provided with a groove 151 on a side close to the base island 130, and the groove 151 is located between the base island 130 and the pin 120. When the package structure 100 is connected to the circuit board 200, soldering or bonding of the conductive adhesive 230 may be performed, and the groove 151 may be filled with solder, so as to increase a contact area between the package structure 100 and the solder, and improve reliability and soldering easiness of soldering. And is beneficial to increasing the bonding force between the circuit board 200 and the plastic package body 150. Secondly, the pin 120 includes a first segment 121 and a second segment 123, and the first segment 121 and the second segment 123 are respectively soldered to the circuit board 200, thereby improving the bonding force between the pin 120 and the circuit board 200. The packaging structure 100 can improve the bonding force between the lead frame 110 and the circuit board 200, the connection is more reliable, and the product failure problem caused by layering or fracture between the pins and the circuit board in the prior art is effectively prevented.
Optionally, the lead frame 110 further includes a frame 131, the frame 131 is disposed on the outer periphery of the base island 130, and the leads 120 are disposed on the frame 131. The base island 130 is connected to the frame 131. The base island 130 and the pins 120 are hollow.
The pin 120 further includes an insulating gel 127, the insulating gel 127 being disposed between the first segment 121 and the second segment 123 and being used to connect the first segment 121 and the second segment 123. Insulating gel 127 electrically insulates first segment 121 from second segment 123, avoiding short circuits between first segment 121 and second segment 123. Optionally, the first segment 121 is far from the base island 130 relative to the second segment 123, i.e., the second segment 123 is closer to the base island 130, which facilitates wire bonding of the second segment 123 and the base island 130. Of course, without being limited thereto, the first segment 121 may be disposed adjacent to the base island 130 relative to the second segment 123. Alternatively, the first segment 121 and the second segment 123 are disposed side by side, and the distances from the base island 130 are substantially equal.
In this embodiment, the thermal expansion coefficient of the insulating colloid 127 is smaller than that of the overall structure after plastic encapsulation, and is prior to deformation of the overall structure after plastic encapsulation, so that the warpage of the package structure 100 can be reduced, and a stress buffering effect is achieved. It is easy to understand that in the subsequent process of cutting the outer side of the pin 120 along the cutting path to form a single product, some structural stress is generated due to the cutting pull, and the insulating colloid 127 filled in the pin 120 in advance can absorb the stress, so as to alleviate the warpage of the structure. And the burr phenomenon on the outer edge of the pins 120 when cutting along the cutting path, which is caused by the warpage of the package structure 100, can be avoided, thereby causing problems such as metal electrical bridging and the like caused by burrs among the pins 120.
The chip 140 may be a face-up chip 140 or a flip chip 140. In this embodiment, the chip 140 is a front-mounted chip 140. The chip 140 is electrically connected to the first segment 121 with a first wire loop 141 and the second segment 123 is electrically connected to the base island 130 with a second wire loop 143. Optionally, the first wire loop 141 is a functional wire loop, the second wire loop 143 is grounded, and the highest point of the second wire loop 143 is higher than the surface of the chip 140 on the side away from the base island 130. Since the number of the pins 120 is plural, a ring is provided at the periphery of the base island 130. Thus, the number of the second wire loops 143 may be plural and arranged around the chip 140. The second wire loop 143 forms a cage structure at the outer periphery of the chip 140, and acts as an electromagnetic shield for the chip 140. Meanwhile, the second wire loop 143 has heat dissipation and buffering functions.
It can be understood that the arrangement of the first arc 141 and the second arc 143 can also reflect the pulling stress in the subsequent process of forming a single product along the outer side of the cutting street of the cutting pin 120, reduce the burr phenomenon of the cutting edge, and improve the cutting quality and efficiency. Certainly, in the cutting process of separating the cutting pin 120 into the first segment 121 and the second segment 123, a buffering effect can be achieved, and the cutting quality and efficiency are improved. In addition, the second wire 143 has a ground shielding function, is disposed between the base island 130 and the lead 120, and also shields noise between the base island 130 and the lead 120 in the lead frame 110, and has functions of electromagnetic shielding and electrostatic discharge. The existing lead frame cannot be provided with a circuit layer, so that the electromagnetic wave between the base island and the pins cannot be blocked and isolated.
With reference to fig. 4, of course, in other embodiments, the highest point of the second arc 143 may be lower than or equal to the surface of the chip 140 on the side away from the base island 130. Thus, the buffer and heat dissipation functions can be achieved.
In this embodiment, the base island 130 is provided with an electrical connection end, the electrical connection end is electrically connected to the second segment 123 by using a second wire arc 143, and the ground pad on the chip 140 is electrically connected to the electrical connection end by using a third wire arc 145. Of course, the base islands 130 may also be made of a conductive material. This allows the entire base island 130 to act as a conductive body, forming a connection terminal.
Optionally, second wire loop 143 is at least partially disposed within groove 151. In this way, the second wire loop 143 in the groove 151 can be used as a grounding point, and when the circuit board 200 is connected, the electrical connection is more reliable due to the larger number of grounding points, and after one or part of the connections fails, other grounding points can be used to ensure the grounding connection. In addition, the number of the grounding points is more, the grounding area is larger, when the packaging structure 100 is connected to the upper board, the requirement for the alignment precision of the grounding points is relatively lower, the reliability of the electrical connection can be ensured even if the deviation within a certain range exists, and the operation is more convenient and simpler.
In conjunction with fig. 2, optionally, the depth of the groove 151 is less than the thickness of the base island 130 (i.e., the height of the base island 130). The distance H between the lowest point of the second line arc 143 and the bottom surface of the base island 130 is less than or equal to the thickness D of the base island 130. In this embodiment, the distance H between the lowest point of the second wire loop 143 and the bottom surface of the base island 130 is less than half the thickness D of the base island 130. It can be understood that a certain distance is left between the second wire arc 143 and the bottom surface of the base island 130, which can prevent the second wire arc 143 from touching the circuit board 200 during the board loading process, and protect the second wire arc 143. While preventing the second wire 143 from protruding out of the groove 151 so that a gap exists between the lead frame 110 and the circuit board 200 to be detrimental to the electrical connection operation of the lead 120. The distance between the second wire loop 143 and the bottom surface of the base island 130 cannot be too large, and if the distance is too large, the reliability of connection between the second wire loop 143 and the circuit board 200 is lowered, and the capillary action on the solder or the like cannot be sufficiently exerted.
Optionally, the second wire arc 143 is a multi-segment arcuate arc. The second wire loop 143 has one or more peaks and one or more valleys. In this embodiment, an arc line of two peaks and one valley is taken as an example for explanation, but it is needless to say that in an alternative manner, the shape may be a single peak and a single valley, or a three-peak two-valley shape, etc., which is not limited specifically here. It can be understood that by using the dual-peak or multi-peak arcs, the shielding arcs are denser, the electromagnetic shielding effect is better, more electromagnetic waves can be prevented from passing through, and the electromagnetic interference caused by the signal of the lead frame 110 can be reduced. Meanwhile, the heat around the chip 140 is dissipated from the bottom of the lead frame 110, thereby greatly improving the heat dissipation effect. And the impact resistance to the plastic package mold flow is improved, and the structure is more reliable.
Referring to fig. 3, a plane on which the first arc 141 is located is parallel to a plane on which the second arc 143 is located, the first arc 141 is located between the two second arcs 143, and a highest point of the second arc 143 is higher than a highest point of the first arc 141. The second wire loop 143 may also serve as an electromagnetic shield for the first wire loop 141. Electromagnetic interference caused by the signal of the lead frame 110 itself can be reduced. Alternatively, the plane on which the first arc 141 is located and the plane on which the second arc 143 is located are on the same plane, and the first arc 141 is higher than the second arc 143, which is not limited herein.
Optionally, in conjunction with fig. 5, the plane of the first wire arc 141 intersects the plane of the second wire arc 143, and the first wire arc 141 passes through a peak or a trough. In this way, the second arcs 143 may also serve as electromagnetic shields for electromagnetic waves between the plurality of first arcs 141, and may also achieve electrostatic discharge between the first arcs 141. And optionally, the second line arc 143 has a certain included angle with the mold flow direction, that is, is not parallel to the mold flow direction, so that the impact caused by the plastic package mold flow is favorably relieved, the buffering effect is better, the electrical connection is more stable, and the reliability is high. Fig. 5 shows only a portion of the first and second arcs 141 and 143, which are not fully shown.
Second embodiment
With reference to fig. 6 to fig. 7, a method for manufacturing a package structure 100 according to an embodiment of the invention includes:
providing a lead frame 110; wherein, the lead frame 110 includes a frame 131, a lead 120, and a base island 130; the lead 120 and the base island 130 are respectively connected with the frame 131, and a hollow structure is arranged between the base island 130 and the lead 120. The protective film 160 is attached to the back surface of the frame 131 to protect the frame 131 and the leads 120 from deformation, which is beneficial to reducing warpage during packaging.
A chip 140 is mounted on the base island 130. Chip 140 may be adhesively secured to base island 130 using adhesive 161. For example, the adhesive 161 is silver paste or non-conductive adhesive film, and is not limited herein. The adhesive 161 functions to perform adhesion fixation and buffer heat dissipation. Optionally, the base islands 130 are conductive material.
A first wire loop 141 is struck between the chip 140 and the pin 120 and a second wire loop 143 is struck between the base island 130 and the pin 120. Optionally, the pin 120 includes a first segment 121 distal from the base island 130 and a second segment 123 proximal to the base island 130. The functional pads of chip 140 make a first wire loop 141 with first segment 121 of pin 120, base island 130 and second segment 123 of pin 120 make a second wire loop 143, and the ground pads of chip 140 and base island 130 make a third wire loop 145. The second and third arcs 143, 145 are grounded. The shape and the path of the second arc 143 can be flexibly adjusted according to actual conditions, and the height relationship and the position arrangement of the first arc 141 and the second arc 143 can be flexibly set according to actual conditions.
In this embodiment, the second wire loop 143 is a multi-segment wire loop having two peaks and one valley. The specific routing operation is as follows: the first segment of wire bonding starts from the second segment 123, wire bonding is performed upwards, the highest point is higher than the surface of one side of the chip 140 away from the base island 130, wire bonding is performed downwards, the distance from the lowest point to the bottom surface of the base island 130 is less than half of the thickness of the base island 130, and the lowest point does not exceed the bottom surface of the base island 130 (the back surface of the lead frame 110). The second segment of routing starts from the lowest point, routing upwards, the highest point is higher than the surface of one side of the chip 140 far away from the base island 130, routing downwards, and the tail end of the wire arc is connected to the base island 130. It is understood that the lowest point of the second wire loop 143 does not extend beyond the bottom surface of the base island 130, and the second wire loop 143 can be protected from the second wire loop 143 contacting the circuit board 200 in the subsequent mounting or mounting process.
A molding compound 150 is formed outside the chip 140 and the lead frame 110 to protect the chip 140, the lead frame 110 and the wire bonding structure. After the molding, the protective film 160 on the back surface of the frame 131 is removed.
Optionally, after the step of forming the molding compound 150 outside the chip 140 and the lead frame 110, the lead 120 is cut to form the independent first segment 121 and second segment 123; wherein a cutting groove 125 is formed between the first section 121 and the second section 123; the cutting groove 125 is filled with an insulating colloid 127. The insulating colloid 127 is filled, so that the effects of insulation, isolation, heat dissipation and buffering can be achieved.
A groove 151 is opened on one side of the plastic package body 150 close to the base island 130 to expose a portion of the second wire loop 143. Alternatively, the groove 151 may be formed by laser grooving. The position of the groove 151 is disposed corresponding to the lowest point of the second wire 143 to expose the lowest point of the second wire 143. The second wire arc 143 in the groove 151 may serve as a ground point. It is easy to understand that the provision of the groove 151 on the plastic package body 150 is also beneficial to releasing structural stress and alleviating warpage.
Finally, the entire package structure is separated, such as by laser cutting or knife cutting, to form a single package structure 100. The fabrication of the package structure 100 is completed.
With reference to fig. 1, an electronic device is further provided in an embodiment of the present invention, and includes a circuit board 200 and a package structure 100 as in any one of the foregoing embodiments, where a first pad 210 and a second pad 220 are disposed on the circuit board 200, and the first pad 210 is electrically connected to the first segment 121. At least one of the second segment 123 and the base island 130 is electrically connected to the second pad 220; and/or the second segment 123 is electrically connected with the base island 130 by using a second wire arc 143, the second wire arc 143 is at least partially exposed out of the groove 151, and the second wire arc 143 in the groove 151 is electrically connected with the second pad 220.
Alternatively, the method for mounting the package structure 100 to the circuit board 200 is as follows:
the package structure 100 is mounted to the circuit board 200, the first segment 121 is electrically connected to the first pad 210, and the second segment 123 is electrically connected to the second pad 220. The electrical connection may be made using solder paste or conductive paste 230. Since the second wire loop 143 is exposed at the groove 151, the exposed second wire loop 143 may serve as a ground point. The second pads 220 can be electrically connected to the second wire arcs 143 in the grooves 151 for grounding effect. The second wire arcs 143 in the grooves 151 can also promote the capillary action of the solder paste or the conductive adhesive 230, and the solder paste covers the second wire arcs 143 and fills the grooves 151, so that the welding strength of the pins 120 and the circuit board 200 is improved, and a wettable side-climbing effect is achieved. The method can avoid the problems of damage to the pin 120 and the like caused by the need of designing a groove or a hole on the pin 120 in the conventional process.
In this embodiment, the ground connection welding point in the package structure 100 is added, and at least one of the second segment 123, the second wire arc 143, and the base island 130 is electrically connected to the second pad 220, so that the ground connection effect can be achieved, thereby reducing the mounting accuracy of the package structure 100 on the circuit board 200, enlarging the mounting range, and achieving faster, more convenient and simpler operation and better reliability.
Of course, the solder paste or the conductive paste 230 may be pre-disposed in the groove 151, or the second wire 143 may be electrically connected to the circuit board 200 by dispensing or printing.
The content of the part not mentioned in this embodiment is similar to the content described in the first embodiment, and is not described again here.
In summary, the beneficial effects of the embodiment of the invention include:
in the package structure 100 provided by the embodiment of the invention, the plastic package body 150 between the base island 130 and the pin 120 is provided with the groove 151, and when the board is mounted, solder can be filled in the groove 151, so that the contact area between the groove 151 and the solder is increased, and the reliability of welding is improved. Meanwhile, the bonding force between the circuit board 200 and the plastic package body 150 is increased. Secondly, the pin 120 includes a first segment 121 and a second segment 123, and the first segment 121 and the second segment 123 are respectively soldered to the circuit board 200, thereby improving the bonding force between the pin 120 and the circuit board 200. The packaging structure 100 can improve the bonding force between the lead frame 110 and the circuit board 200, the connection is more reliable, and the product failure problem caused by layering or fracture between the pin 120 and the circuit board 200 in the prior art is effectively prevented. In addition, the electromagnetic shielding structure also has an electromagnetic shielding effect, the warping of the structure can be relieved, and the heat dissipation performance is improved.
In the manufacturing method of the package structure 100 provided by the embodiment of the invention, the plastic package body 150 between the base island 130 and the pins 120 is provided with the groove 151, and the second arc 143 is exposed out of the groove 151, so that the bonding force between the package structure 100 and the circuit board 200 is improved, and the reliability is higher. Moreover, the second arc 143 is exposed from the groove 151, so that electrical connection points between the circuit board 200 and the package structure 100 are increased, the connection range is wider, the requirement on mounting accuracy is lower, and the reliability is better. In the embodiment, process steps such as etching and the like are not needed, so that pollution and corrosion caused by the etching solution are avoided, and the method is more environment-friendly.
The electronic device provided by the embodiment of the invention comprises the packaging structure 100 and the circuit board 200, so that the connection reliability is improved, the product quality is good, and the qualification rate is high.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (12)

1. A package structure, comprising:
a lead frame including a pin and a base island, the pin including a first segment and a second segment insulated from each other;
the chip is arranged on the base island; the chip is electrically connected with the base island and the first segment respectively, and the base island is electrically connected with the second segment;
the plastic package body covers the lead frame and the chip, a groove is formed in one side, close to the base island, of the plastic package body, and the groove is located between the base island and the pins.
2. The package structure of claim 1, wherein the leads further comprise an insulating gel disposed between and connecting the first and second segments.
3. The package structure of claim 1, wherein the first segment is distal from the base island relative to the second segment.
4. The package structure of claim 1, wherein the chip is electrically connected to the first segment using a first arc, and the second segment is electrically connected to the base island using a second arc; the second wire arc is grounded, and the highest point of the second wire arc is higher than the surface of one side of the chip far away from the base island;
or the highest point of the second line arc is lower than or equal to the surface of one side of the chip far away from the base island.
5. The package structure of claim 4, wherein the second arc is at least partially disposed within the recess.
6. The package structure of claim 4, wherein a distance between a lowest point of the second line arc and the bottom surface of the base island is less than or equal to a thickness of the base island.
7. The package structure of claim 4, wherein the second arc has one or more peaks and one or more valleys; the plane where the first arc is located is intersected with the plane where the second arc is located, and the first arc penetrates through the wave crest or the wave trough;
or the plane where the first arc is located is parallel to the plane where the second arc is located, the first arc is located between the two second arcs, and the highest point of the second arc is higher than that of the first arc.
8. The package structure according to any one of claims 1 to 7, wherein the base island is made of a conductive material.
9. A method for manufacturing a package structure includes:
providing a lead frame; wherein the lead frame comprises a pin and a base island;
mounting a chip on the base island;
forming a first wire arc between the chip and the pin, and forming a second wire arc between the base island and the pin;
forming a plastic package body outside the chip and the lead frame;
and forming a groove on one side of the plastic package body close to the base island to expose the second wire arc.
10. The method for manufacturing a package structure according to claim 9, further comprising:
cutting the pins to form independent first and second segments after the step of forming a plastic package body outside the chip and the lead frame; wherein a cutting groove is formed between the first section and the second section;
and filling insulating colloid in the cutting groove.
11. The method of claim 9, further comprising:
and filling conductive adhesive in the groove.
12. An electronic device, comprising a circuit board and the package structure according to any one of claims 1 to 8, the circuit board having a first pad and a second pad thereon, wherein the first pad is electrically connected to the first segment;
at least one of the second segment and the base island is electrically connected to the second pad; and/or the second section is electrically connected with the base island by adopting a second arc, at least part of the second arc is exposed out of the groove, and the second arc in the groove is electrically connected with the second bonding pad.
CN202211230905.9A 2022-09-30 2022-09-30 Packaging structure, packaging structure manufacturing method and electronic device Pending CN115527974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211230905.9A CN115527974A (en) 2022-09-30 2022-09-30 Packaging structure, packaging structure manufacturing method and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211230905.9A CN115527974A (en) 2022-09-30 2022-09-30 Packaging structure, packaging structure manufacturing method and electronic device

Publications (1)

Publication Number Publication Date
CN115527974A true CN115527974A (en) 2022-12-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211230905.9A Pending CN115527974A (en) 2022-09-30 2022-09-30 Packaging structure, packaging structure manufacturing method and electronic device

Country Status (1)

Country Link
CN (1) CN115527974A (en)

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