CN115527850A - Flash memory and manufacturing method thereof - Google Patents

Flash memory and manufacturing method thereof Download PDF

Info

Publication number
CN115527850A
CN115527850A CN202211203905.XA CN202211203905A CN115527850A CN 115527850 A CN115527850 A CN 115527850A CN 202211203905 A CN202211203905 A CN 202211203905A CN 115527850 A CN115527850 A CN 115527850A
Authority
CN
China
Prior art keywords
flash memory
layer
etching process
opening
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211203905.XA
Other languages
Chinese (zh)
Inventor
张振兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202211203905.XA priority Critical patent/CN115527850A/en
Publication of CN115527850A publication Critical patent/CN115527850A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

Abstract

According to the flash memory and the manufacturing method thereof, 2MHZ extremely-low frequency and high energy power larger than 700W are adopted, when a first etching process is performed on a medium material layer, ions of the first etching process can perform rapid physical bombardment on the medium material layer in a direction vertical to a substrate with high energy, so that a medium layer located on the side wall of a second opening in a finally formed medium layer obtains a vertical and uniform appearance, the product performance is improved, the uniformity of the appearance of the flash memory prepared from the same wafer can be improved, and the product yield is improved.

Description

Flash memory and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a flash memory and a method for manufacturing the same.
Background
Flash memory is an important device in integrated circuit products. The main feature of flash memory is to retain the stored information for a long period of time without the application of a voltage. Flash memories have the advantages of high integration, fast access speed, easy erasing, etc., and thus are widely used.
Current flash memories are divided into two types: stacked gate (stack gate) flash memory and split gate (split gate) flash memory. The stacked gate flash memory has a floating gate and a control gate above the floating gate, and the control gates in the same column are connected to serve as word lines. Different from a stacked gate flash memory, the split gate flash memory forms a word line serving as an erasing gate on one side of a control gate, can effectively avoid an over-erasing effect, and is programmed by utilizing hot electron injection of a source end, so that the split gate flash memory has higher programming efficiency.
In both stacked gate flash memory and split gate flash memory, the verticality and uniformity of the sidewall profile of the dielectric layer above the control gate layer are very important, and if the verticality and uniformity are poor, the quality of the finally formed flash memory is reduced, and the yield is reduced. In the actual etching process, the dielectric layers in the central area and the edge area of the wafer are easy to generate difference. The central region of the wafer is etched slowly and the edge of the wafer is etched quickly, so that the shapes of the side walls of the dielectric layers in the central region and the edge region of the wafer are inconsistent.
Disclosure of Invention
The invention aims to provide a flash memory and a manufacturing method thereof, which aim to solve the problem of low performance of the flash memory caused by the failure of programming crosstalk of flash memory units in the conventional split-gate flash memory.
In order to solve the above technical problem, the present invention provides a method for manufacturing a flash memory, comprising:
providing a substrate;
sequentially forming a medium material layer and a photoresist layer on the substrate, wherein the photoresist layer is provided with a first opening;
and performing a first etching process on the dielectric material layer by taking the photoresist layer as a mask to form a dielectric layer, and extending the first opening to the dielectric layer to form a second opening, wherein the etching frequency of the first etching process is 2MHZ, and the power of the first etching process is more than 700W.
Optionally, the first etching process is dry etching.
Optionally, the etching gas of the first etching process is argon.
Optionally, the flow rate of the argon gas is greater than 700SCCM.
Optionally, when the first etching process is performed, a protective gas is also introduced to protect the dielectric layer on the sidewall of the second opening from being etched in the process of forming the second opening.
Optionally, the shielding gas comprises: carbon tetrafluoride and trifluoromethane.
Optionally, the gas ratio of the carbon tetrafluoride to the trifluoromethane is greater than 1:1.
optionally, the gas ratio of the argon gas to the protective gas is greater than 5.
Optionally, the dielectric layer is formed of silicon nitride.
In order to solve the above problems, the present invention further provides a flash memory, which is manufactured according to the method for manufacturing a flash memory described in any one of the above aspects.
According to the manufacturing method of the flash memory, the extremely low frequency of 2MHZ and the high energy power larger than 700W are adopted, when the first etching process is performed on the medium material layer, ions of the first etching process can perform rapid physical bombardment on the medium material layer in the direction vertical to the substrate with high energy, so that the medium layer on the side wall of the second opening in the finally formed medium layer obtains a vertical and uniform appearance, the product performance is improved, the uniformity of the appearance of the flash memory prepared from the same wafer can be improved, and the product yield is improved.
Drawings
Fig. 1 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the invention.
Fig. 2 to 4 are schematic structural diagrams of a method for manufacturing a flash memory according to an embodiment of the invention during a manufacturing process thereof.
Wherein the reference numbers are as follows:
1-a substrate;
3-a polysilicon layer;
4-a mask layer; 40-a layer of dielectric material;
5-an anti-reflection layer; 50-a layer of antireflective material;
6-photoresist layer;
a-a first opening;
b-a second opening.
Detailed Description
The following describes a flash memory and a method for manufacturing the same in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings are intended to show different emphasis, sometimes in different proportions. The purpose of the invention is as follows: by adopting the extremely low frequency of 2MHZ and the high energy power of more than 700W, when the first etching process is executed on the dielectric material layer, ions of the first etching process can carry out rapid physical bombardment on the dielectric material layer in the direction perpendicular to the substrate with high energy, so that the dielectric layer on the side wall of the second opening in the finally formed dielectric layer obtains a perpendicular and uniform appearance, the product performance is improved, the uniformity of the appearance of the flash memory prepared by the same wafer can be improved, and the product yield is improved.
Fig. 1 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the invention. Fig. 2 to 4 are schematic structural diagrams illustrating a method for manufacturing a flash memory according to an embodiment of the invention during a manufacturing process thereof; the steps of the method for manufacturing a flash memory according to the present embodiment will be described in detail with reference to fig. 2 to 4, and the following detailed description does not depart from the gist of the present invention.
In step S10, as shown in fig. 2, a substrate 1 is provided.
The substrate may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, siGe, siGeC, siC, gaAs, inAs, inP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, with reference to fig. 2, a dielectric material layer 40 and a photoresist layer 6 are sequentially formed on the substrate 1, wherein the photoresist layer 6 has an opening a.
In this embodiment, the thickness of the photoresist layer 6 is
Figure BDA0003872815930000041
In this embodiment, by setting the thickness of the photoresist layer 6 reasonably, the protection of the dielectric material layer 40 that needs to be preserved is ensured when the dielectric material layer 40 is etched, and meanwhile, the material waste can be avoided, and the cost is saved. In this embodiment, the photoresist layer 6 may be a positive photoresist or a negative photoresist, and in this embodiment, the photoresist layer is not particularly limited, which is based on the actual situation.
In step S30, referring to fig. 3, a first etching process is performed on the dielectric material layer 40 by using the photoresist layer 6 as a mask to form a dielectric layer 4, and the first opening a is extended to the dielectric layer 4 to form a second opening B, wherein an etching frequency of the first etching process is 2MHZ, and a power of the first etching process is greater than 700W.
In this embodiment, because the very low frequency of 2MHZ and the high energy power greater than 700W are used in the first etching process, when the first etching process is performed, ions of the first etching process can physically bombard the dielectric material layer 40 in a direction perpendicular to the substrate 1 with high bombardment energy, so that the dielectric layer 4 located on the sidewall of the second opening B in the finally formed dielectric layer 4 obtains a vertical and uniform morphology, thereby improving product performance, further improving the uniformity of the morphology of the flash memory prepared from the same wafer, and improving product yield.
Further, in the present embodiment, the dielectric layer 4 is formedThe material is silicon nitride, and the thickness of the dielectric layer 4 is
Figure BDA0003872815930000042
In this embodiment, the performance of the device is ensured by setting the reasonable thickness of the dielectric layer 4.
Further, with continuing reference to fig. 2 in conjunction with fig. 3, in this embodiment, the method further includes, before forming the photoresist layer 6: a layer of antireflective material 50 is formed over the layer of dielectric material 40. And, while etching the dielectric material layer 4 with the photoresist layer 6 as a mask, the method further includes etching the anti-reflection material layer 50 to form an anti-reflection layer 5, and extending the first opening a to the anti-reflection layer 5.
In this embodiment, the anti-reflection material layer 50 is formed on the dielectric material layer 40, so that the photo-etching reflected light can be absorbed in the etching process, and further, the problem of uneven photo-etching when the dielectric material layer 40 is etched by using the photo-etching layer 6 as a mask due to light interference in the etching process is avoided, so as to further improve the perpendicularity and uniformity of the finally formed side wall of the dielectric layer 5, and further improve the performance of the flash memory.
In this embodiment, the first etching process is dry etching, the etching gas of the first etching process is argon, and the flow rate of the argon is greater than 700SCCM. In the embodiment, when the first etching process is performed, the argon ions bombard the dielectric material layer 40 rapidly and at high energy under the action of high energy greater than 700SCCM at a low frequency of 2MHZ after the argon ions are dissociated, so as to etch the second opening B on the dielectric material layer 40 rapidly and vertically. Thus, the side wall of the dielectric layer 4 on the side wall of the second opening B is vertical and uniform.
In addition, in this embodiment, when the first etching process is performed, the temperature of the central region close to the substrate 1 is: 30 degrees celsius and the temperature near the edge region of the substrate 1 is between 24 and 35 degrees celsius. And when the first etching process is executed, the environmental pressure is 20MT to 80MT. To further ensure that the argon ions rapidly and vertically etch the second opening B in the dielectric material layer 40. Thus, the side wall of the dielectric layer 4 on the side wall of the second opening B is vertical and uniform.
Further, in this embodiment, when the first etching process is performed, a protective gas is also introduced to protect the dielectric layer located on the sidewall of the second opening B from being etched during the process of forming the second opening B. The shielding gas includes: carbon tetrafluoride and trifluoromethane. In this embodiment, when the first etching process is performed, protective gases, namely carbon tetrafluoride and trifluoromethane, react with the dielectric layer 5 located on the sidewall of the second opening B to form a protective layer 7 on the dielectric layer 5 located on the sidewall of the second opening B, and the protective layer 7 can protect the dielectric layer 5 located on the sidewall of the second opening B from being etched in the etching process, so that the dielectric layer 5 on the sidewall of the second opening B can be further made vertical.
In this embodiment, the gas ratio of the carbon tetrafluoride to the trifluoromethane is greater than 1:1. in the present embodiment, the gas ratio of carbon tetrafluoride and trifluoromethane is set to be suitable so that the side wall of the second opening B obtains the best protection effect.
Further, in this embodiment, the gas ratio of the argon gas to the shielding gas is greater than 5. In this embodiment, by setting a suitable gas ratio of the etching gas to the protective gas, the verticality and uniformity of the dielectric layer 5 on the sidewall of the second opening B formed by etching are improved.
Furthermore, in this embodiment, before forming the dielectric material layer 40, the method further includes: a polysilicon layer 3 is formed on the substrate 1. In this embodiment, when the first etching process is performed to etch the dielectric material layer 40, the etching is stopped on the polysilicon layer 3.
Further, with continued reference to fig. 3 in conjunction with fig. 4, after forming the dielectric layer 5, the method further includes removing the photoresist layer 6 and the antireflective layer 5. In this embodiment, the method of removing the photoresist layer 6 and the anti-reflection layer 5 includes: an ashing process is performed to remove the photoresist layer 6 and the anti-reflection layer 5. Wherein the gas of the ashing process includes oxygen gas, and the photoresist layer 6 and the anti-reflection layer 5 are removed by burning oxygen. Specifically, the oxygen reacts with the photoresist layer 6 and the anti-reflection layer 5 in a high temperature environment to remove the photoresist layer 6 and the anti-reflection layer 5.
Further, the embodiment also discloses a flash memory, and the flash memory is prepared according to the manufacturing method of the flash memory.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A method for manufacturing a flash memory is characterized in that,
providing a substrate;
sequentially forming a medium material layer and a photoresist layer on the substrate, wherein the photoresist layer is provided with a first opening;
and performing a first etching process on the dielectric material layer by taking the photoresist layer as a mask to form a dielectric layer, and extending the first opening to the dielectric layer to form a second opening, wherein the etching frequency of the first etching process is 2MHZ, and the power of the first etching process is more than 700W.
2. The method of manufacturing a flash memory of claim 1, wherein the first etching process is dry etching.
3. The method of claim 1, wherein the etching gas of the first etching process is argon.
4. The method of claim 3, wherein the flow of argon is greater than 700SCCM.
5. The method according to claim 3, wherein during the first etching process, a protective gas is also introduced to protect the dielectric layer on the sidewall of the second opening from being etched during the process of forming the second opening.
6. The method of manufacturing a flash memory of claim 5, wherein the shielding gas comprises: carbon tetrafluoride and trifluoromethane.
7. The method of claim 6, wherein the carbon tetrafluoride and the trifluoromethane are present in a gas ratio of greater than 1:1.
8. the method of claim 5, wherein a gas ratio of the argon gas to the shielding gas is greater than 5.
9. The method of claim 1, wherein the dielectric layer is formed of silicon nitride.
10. A flash memory prepared according to the method for manufacturing a flash memory according to any one of claims 1 to 9.
CN202211203905.XA 2022-09-29 2022-09-29 Flash memory and manufacturing method thereof Pending CN115527850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211203905.XA CN115527850A (en) 2022-09-29 2022-09-29 Flash memory and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211203905.XA CN115527850A (en) 2022-09-29 2022-09-29 Flash memory and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115527850A true CN115527850A (en) 2022-12-27

Family

ID=84699645

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211203905.XA Pending CN115527850A (en) 2022-09-29 2022-09-29 Flash memory and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN115527850A (en)

Similar Documents

Publication Publication Date Title
KR100518606B1 (en) Method for fabricating a recess channel array transistor using a mask layer having high etch selectivity for silicon substrate
US7868373B2 (en) Flash memory device and a method of fabricating the same
US7566621B2 (en) Method for forming semiconductor device having fin structure
US9287285B2 (en) Self-aligned liner method of avoiding PL gate damage
CN105448841A (en) Method for forming semiconductor structure
US6706602B2 (en) Manufacturing method of flash memory
US7645667B2 (en) Two-step self-aligned source etch with large process window
CN105762114B (en) The forming method of semiconductor structure
US7696074B2 (en) Method of manufacturing NAND flash memory device
US20230118901A1 (en) Semiconductor device
CN110767658A (en) Forming method of flash memory device
KR100490301B1 (en) Method of manufacturing a flash memory cell
CN115527850A (en) Flash memory and manufacturing method thereof
US7741203B2 (en) Method of forming gate pattern of flash memory device including over etch with argon
US20020072156A1 (en) Method of forming gate electrode in semiconductor devices
KR100561970B1 (en) Method for fabricating semiconductor device
CN111863944B (en) Semiconductor device and method of forming the same
CN115802750A (en) Flash memory and manufacturing method thereof
KR20070047179A (en) Method of manufacturing a nand type flash memory device
KR100479969B1 (en) Method for manufacturing a flash memory device
KR20080038953A (en) Method of manufacturing a flash memory device
KR20070001590A (en) Method for forming recessed gate of semiconductor device
KR100859485B1 (en) Manufacturing Method of Flash Memory Device
CN115472615A (en) Flash memory and manufacturing method thereof
KR20050031299A (en) Method for manufacturing control gate of the flash memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination