CN115525133A - Server power supply power failure control method, device, terminal and storage medium - Google Patents

Server power supply power failure control method, device, terminal and storage medium Download PDF

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Publication number
CN115525133A
CN115525133A CN202211214526.0A CN202211214526A CN115525133A CN 115525133 A CN115525133 A CN 115525133A CN 202211214526 A CN202211214526 A CN 202211214526A CN 115525133 A CN115525133 A CN 115525133A
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power supply
power
server
key
microprocessor
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郭杨洋
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/28Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof

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Abstract

The invention discloses a server power supply power-down control method, a device, a terminal and a storage medium, wherein the method is applied to an ARM server, a monitoring event is set in an input/output system of the ARM server, whether a power supply key is in a pressing state or not is judged through the monitoring event, and after the power supply key is determined to be in a short pressing state, a power-down control function is called through an extensible firmware interface on a microprocessor, so that a first control instruction based on a power supply state coordination interface protocol PSCI is sent to the microprocessor and is converted into a second control instruction based on a system control management protocol SCMI, and the server power supply is enabled to execute power-down operation according to the second control instruction. By adopting the technical scheme, the ARM server can realize the power-off function of short-time pressing of the power key through monitoring the event, the real-time power-off requirement of the ARM server on equipment in the research, development, operation and maintenance processes is facilitated, and the time for controlling the server to be powered off by a user is saved.

Description

Server power supply power failure control method, device, terminal and storage medium
Technical Field
The invention relates to the technical field of server testing, in particular to a server power supply power failure control method, a server power supply power failure control device, a server power supply power failure control terminal and a storage medium.
Background
The startup, shutdown and restart operations of the server of the data center all need to be quickly operated through the power key. At present, the default function of a power key of most servers is to realize the actions of starting and closing the servers through a power signal, and to control the electrification or the outage of alternating current through a fatigue machine or a power distribution unit, so as to realize the circulation of power-on and power-off.
Because the server of the data center is large in size and occupies a large amount of resources, in the process of ordinary research and development and operation maintenance, when a user has a power-off requirement, the user needs to manually plug and unplug on the spot, and operation is inconvenient. Currently, part of servers can be remotely controlled through an input/output system firmware connected with the servers, but for an ARM (advanced riscmachine) server, because the ARM server generally does not support an SMI interrupt type, the ARM server cannot be powered off by pressing a power key for a short time at present, so that the operation of the ARM server is inconvenient.
Disclosure of Invention
In view of the above problems, embodiments of the present invention are provided to provide a server power down control method, and a corresponding server power down control apparatus, terminal and storage medium that overcome or at least partially solve the above problems.
In order to solve the above problem, in one aspect, an embodiment of the present invention discloses a server power failure control method, which is applied to an advanced reduced instruction set ARM server, where the ARM server includes a microprocessor and a power button, and the method includes:
setting a monitoring event in an input/output system of the ARM server, wherein the monitoring event is whether the accumulated time length of the power key in a pressed state is less than a preset time threshold value; the power supply key is in a pressed state, and the power supply key is converted from a high level to a low level and then from the low level to the high level;
when the microprocessor is in a working state, monitoring whether the monitoring event occurs or not through the input and output system;
when the monitoring event is monitored, determining that the power supply key is in a short-press state, and calling a shutdown control function through an extensible firmware interface (UEFI) on the microprocessor so as to send a first control instruction based on a power supply state coordination interface Protocol (PSCI) to the microprocessor;
and converting the first control instruction into a second control instruction based on a system control management protocol SCMI (Single chip computer interface), and executing shutdown operation of the power supply of the server according to the second control instruction by the microprocessor.
Optionally, the ARM server includes at least one group of main board and a bottom board, the main board and the bottom board are both connected to a power supply of the server, the main board is provided with the microprocessor, the bottom board is provided with a bottom board controller, the bottom board controller is connected to the power key, and the method further includes:
and when the bottom board controller receives a power-down command of a server power supply, the bottom board controller starts the power supply key so as to enable the power supply key to be in a pressed state.
Optionally, a timer is further disposed on the ARM server, and the timer is configured to count the accumulated duration of the power key in the pressed state.
Optionally, the process of calculating the accumulated time length of the power key in the pressed state includes:
when the power supply key is converted from a high level to a low level, recording first time for starting timing by the timer;
after the timer starts to time, when the power key is converted from a low level to a high level, the timer finishes timing and records a second time when the timer finishes timing;
and calculating the accumulated time length between the first time and the second time.
Optionally, the preset time threshold is 3 seconds.
On the other hand, the embodiment of the invention discloses a power supply power failure control device of a server, which is applied to an advanced reduced instruction set ARM server, wherein the ARM server comprises a microprocessor and a power supply key, and the device comprises:
the monitoring event creating module is used for setting a monitoring event in an input and output system of the ARM server, wherein the monitoring event is whether the accumulated time length of the power key in a pressed state is less than a preset time threshold value; the power supply key is in a pressed state, and the power supply key is converted from a high level to a low level and then from the low level to the high level;
the monitoring event monitoring module is used for monitoring whether the monitoring event occurs or not through the input and output system when the microprocessor is in a working state;
the first data processing module is used for determining that the power key is in a short-press state when the monitoring event is monitored to occur, and calling a shutdown control function through an extensible firmware interface UEFI on the microprocessor so as to send a first control instruction based on a power state coordination interface protocol PSCI to the microprocessor;
and the second data processing module is used for converting the first control instruction into a second control instruction based on a system control management protocol SCMI (Single chip computer interface), and executing shutdown operation of the power supply of the server according to the second control instruction.
Optionally, the ARM server includes at least one group of motherboard and a bottom plate, the motherboard and the bottom plate are both connected to the power supply of the server, the motherboard is provided with the microprocessor, the bottom plate is provided with a bottom plate controller, the bottom plate controller is connected to the power supply key, the apparatus further includes:
and the power supply key starting module is used for starting the power supply key by the bottom plate controller after the bottom plate controller receives a power-down command of a server power supply so as to enable the power supply key to be in a pressed state.
Optionally, a timer is further disposed on the ARM server, and the timer is used for counting the accumulated time length of the power key in the pressed state.
Optionally, the monitoring event creating module includes:
the first timing submodule is used for recording first time when the timer starts timing when the power supply key is converted from a high level to a low level;
the second timing submodule is used for finishing timing by the timer when the power supply key is converted from a low level to a high level after the timer starts timing, and recording second time when the timer finishes timing;
and the third timing submodule is used for calculating the accumulated time length between the first time and the second time.
Optionally, the preset time threshold is 3 seconds.
In another aspect, an embodiment of the present invention further provides a terminal, where the terminal includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the computer program implements the steps of the server power supply failure control method.
In another aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the server power supply failure control method.
The embodiment of the invention discloses a power-down control method for a server power supply, which is applied to an ARM server, wherein the ARM server comprises a microprocessor and a power supply key, a monitoring event is set in an input and output system of the ARM server, whether the power supply key is in a pressing state is judged through the monitoring event, and after the power supply key is determined to be in a short-pressing state, a power-off control function is called through an extensible firmware interface on the microprocessor, so that a first control instruction based on a power supply state coordination interface protocol PSCI is sent to the microprocessor through the power-off control function and is converted into a second control instruction based on a system control management protocol SCMI, and the power supply of the server executes power-off operation according to the second control instruction. By adopting the technical scheme, the ARM server can realize the power-off function of short-time pressing of the power key through monitoring the event, the real-time power-off requirement of the ARM server on equipment in the research, development, operation and maintenance processes is facilitated, the time for a user to control the server to be powered off is saved, and the use of the user is facilitated.
Drawings
Fig. 1 is a flowchart illustrating steps of a server power failure control method according to an embodiment of the present invention;
fig. 2 is a block diagram of a server power failure control apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description thereof. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
At present, the default of the power key functions of most servers in a data center is to realize the power-on and power-off actions of the servers through a GPD3_ PWRBTN _ N signal of a PCH, when the power supply of the servers needs to be powered off, the power key is pressed for a short time to trigger the power-off action, the SCI interrupt triggers a system kernel to perform a soft power-off action, and the power key is pressed for a long time to trigger a hardware power-off action. When the server is in a non-operating System, a power key is pressed for a short time to trigger a System Management interrupt mechanism (SMI) in the BIOS according to a GPD3_ PWRBTN _ N signal, the SMI interrupt mechanism adopts a hardware interrupt mechanism principle, namely a System Management Mode (System Management Mode) that the power key generates hardware interrupt to trigger SMI interrupt in the BIOS when being pressed for a short time, the CPU is required to enter the System Management Mode in advance when an SMM program is executed, a specific operation flow is that the CPU needs a memory area SMRAM, the value of the register is stored in the SMRAM before the CPU enters an SMM, the program is transferred to SMINTRY POINT to be executed, the SMM instruction is used for jumping back to the original SMM to continue to be executed after the SMM program is processed, and the value of the CPU register is restored. And after the server power supply key is pressed for a short time, the SMM program writes a shutdown value to the CPU internal register through the IO port to perform shutdown action.
Currently, an X86 processor or an ARM (Advanced RISC Machine) processor is generally adopted in a server, wherein the X86 processor refers to an instruction set architecture of a central processing unit based on an Intel8086 and backward compatible, and supports the above-mentioned SMI interrupt mechanism. Compared with an X86 processor, the ARM processor has the advantages of multiple cores, small size, low power consumption, low cost, high performance and the like, the business can be processed more efficiently and more quickly, and based on the advantages, the server based on the ARM processor is more and more widely applied. However, due to the small size of the ARM processor, its startup and operation needs to be tied to external SCP firmware. In order to ensure the safe startup of the ARM server, the SCP firmware of the ARM processor needs to be checked safely when the ARM server is started. For the ARM server, the ARM server does not have BIOS firmware and does not support the SMI interrupt type, so the ARM server cannot be powered off by pressing a power key for a short time at present, which causes inconvenience in operation of the ARM server.
In order to solve the problem that the ARM server cannot be powered off by pressing a power key for a short time at present, fig. 1 is a flowchart illustrating steps of a server power supply power-down control method according to an embodiment of the present invention, where the method is applied to an advanced reduced instruction set ARM server, the ARM server includes a microprocessor and a power key, and the method includes the following steps:
step 101, setting a monitoring event in an input/output system of the ARM server, wherein the monitoring event is whether the accumulated time length of the power key in a pressed state is less than a preset time threshold value; the power supply key is in a pressed state, and the power supply key is converted from a high level to a low level and then from the low level to the high level;
the input output system may be a BIOS system (basic input output system) that uses BIOS code to create monitoring events on the input output system. Specifically, the ARM server may be provided with a signal acquisition circuit, and the signal acquisition circuit is connected to the power key and is configured to acquire a level signal output by the power key. In the embodiment of the present invention, the signal acquisition circuit may adopt an ADC acquisition circuit, and for example, the model of the ADC acquisition circuit may be LTC2440.
In the using process, the microprocessor is connected with the signal acquisition circuit and used for analyzing the voltage signals acquired by the signal acquisition circuit and judging the using state of the power supply key. The power key may have a high state and a low state, and the monitoring event that the power key is in the pressed state may include: after the power supply key is converted from a high level to a low level, the low level is converted into a high level; or the power supply key is converted from the low level to the high level and then converted from the high level to the low level.
Still be provided with the timer on the ARM server, after confirming that the power button is in the state of pressing, this timer is used for counting the power button and is in the accumulative duration of pressing the state, and the process of calculating the power button and be in the accumulative duration of pressing the state can include: when the power supply key is converted from a high level to a low level, recording the first time when the timer starts to time; after the timer starts to time, when the power supply key is converted from the low level to the high level, the timer finishes timing and records the second time when the timer finishes timing; and calculating the accumulated time length between the first time and the second time. In this embodiment, the preset time threshold may be 3 seconds, when the accumulated duration of the power key being in the pressed state is less than 3 seconds, the power key is considered to be in the short-press state, and when the accumulated duration of the power key being in the pressed state is greater than or equal to 3 seconds, the power key is considered to be in the long-press state. It should be noted that, generally, the default power key high level is the normal state, and the power key low level is the pressed state, and of course, the user may also set the default power key low level to the normal state, and the power key high level to the pressed state. Meanwhile, a user can set the preset time threshold according to the power supply control requirement of the user, and the specific numerical value of the preset time threshold is not specifically limited.
102, monitoring whether the monitoring event occurs or not through the input and output system when the microprocessor is in a working state;
when the microprocessor is in a working state, the level signal of the power supply key can be switched between a high level signal and a low level signal, and the input and output system judges whether a monitoring event occurs or not in the process of monitoring and recording the level use state of the power supply key.
103, when the monitoring event is monitored to occur, determining that the power key is in a short-press state, and calling a shutdown control function through an extensible firmware interface UEFI on the microprocessor to send a first control instruction based on a power state coordination interface protocol PSCI to the microprocessor;
after the power key is determined to be in the short-press state, a shutdown control function is called through UEFI (unified extensible firmware interface), the shutdown control function can be an SMC (sheet molding compound) function, a power management protocol can be a Power State coordination interface Protocol (PSCI), the PSCI is a power management interaction protocol between Linux and ATF (auto-configuration framework) and can be used for power management, and an extensible firmware interface on the microprocessor calls the SMC function so as to send a first control instruction based on the PSCI to the microprocessor through the SMC function.
And 104, converting the first control instruction into a second control instruction based on a system control management protocol SCMI (Single chip computer interface), and executing shutdown operation of the power supply of the server according to the second control instruction by the microprocessor.
The microprocessor converts the first control instruction into a System Control and Management Interface (SCMI) based System Control and Management Interface (SCMI), so that the server power supply executes shutdown operation of the server power supply according to the second control instruction. An application processor (application processor) on the ARM server includes an Operating System (OSPM) and a PSCI power management component (psciccpupperdomain), wherein the OSPM includes a processor power supply (CPUPOWER), a device performance (devicecpupperform), a device power domain (devicepowerdomain), and a sensor (Sensors), the CPUPOWER is connected with the SCMI through the psccpupperdomain, and the deviceupower, the devicepowerdomain, and the Sensors are connected with the SCMI and interact with the system processor through an SCMI protocol. The PSCI is a power management interaction protocol between Linux and the ATF, can be used for power management, the microprocessor executes a PSCI _ SYSTEM _ OFF instruction and controls the power of the server through an SCMI protocol, the SCMI protocol comprises a protocol layer and a transmission layer, the protocol layer is used for describing supportable commands, and the transmission layer defines the mode through which the commands are transmitted so as to realize the shutdown operation of the power of the server.
It should be noted that, the SMC function may transmit a shutdown instruction of the PSCI protocol, that is, PSCI _ SYSTEM _ OFF, to the microprocessor, and the microprocessor executes the PSCI _ SYSTEM _ OFF instruction and controls the server power supply through the SCMI protocol, where the SCMI protocol includes a protocol layer and a transport layer, the protocol layer is used to describe a command that can be supported, and the transport layer defines what way the command is transmitted through to implement a shutdown operation on the server power supply, thereby implementing a setup interface of the input and output SYSTEM and a shutdown function under the Shell.
The embodiment of the invention discloses a power-down control method for a server power supply, which is applied to an ARM server, wherein the ARM server comprises a microprocessor and a power supply key, a monitoring event is set in an input and output system of the ARM server, whether the power supply key is in a pressing state or not is judged through the monitoring event, a power-down control function is called through an extensible firmware interface on the microprocessor after the power supply key is determined to be in a short-pressing state, a first control instruction based on a power supply state coordination interface protocol PSCI is sent to the microprocessor, and the first control instruction is converted into a second control instruction based on a system control management protocol SCMI, so that the server power supply executes power-down operation according to the second control instruction. By adopting the technical scheme, the ARM server can realize the power-off function of short-time pressing of the power key through monitoring the event, the real-time power-off requirement of the ARM server on equipment in the research, development, operation and maintenance processes is facilitated, the time for a user to control the server to be powered off is saved, and the use of the user is facilitated.
At present, the server is very commonly applied in life, and has wide application in education industry, financial industry, telecommunication industry, military administration industry and the like, and the server in the network era plays an increasingly important role. In the process of daily use, the server generally operates autonomously, but when the server fails to operate, the server needs to be managed and maintained. In order to reduce the loss of the server and prolong the service life of the server, the power key functions of most servers are defaulted to realize the startup and shutdown actions of the server through power signals, and the power-on or power-off of alternating current is controlled through a fatigue machine or a power distribution unit by default, so that the cyclic power-on and power-off are realized. In the process of managing and maintaining the server, if the user is in the field, a great deal of time cost and traffic cost are consumed. When the number of servers is large, such as servers in a data center, the number of the servers may be as high as hundreds to thousands, and it takes a lot of time to manually implement the startup and shutdown actions of the servers.
In some embodiments, the real-time and long-distance transmission functions of the Internet provide a good platform for people to transmit control signals to all over the world based on the TCP/IP protocol through the Internet, and if the information of a computer can be transmitted to a remote control end in real time through a device, the remote management server can manage the remote servers as if each server is controlled on site locally. In order to solve the problem that the server power management consumes time, the embodiment of the application remotely controls the controlled terminal through the application and control terminal. The controlled terminal is arranged on the ARM server, the control program is arranged on the controlled terminal and is solidified in an embedded system of the ARM server of the application and control terminal, and when the ARM embedded system is controlled through the application and control terminal, the WEB-based control platform of the ARM embedded system can be accessed through a network without complex operation. Illustratively, the ARM server comprises at least one group of main boards and a bottom board, the main boards and the bottom board are both connected with a power supply of the server, a microprocessor is arranged on the main boards, a bottom board controller is arranged on the bottom board, and the bottom board controller is connected with power supply keys. When a user needs to execute remote power-down control, the control terminal establishes a control link with the controlled terminal through an IP address of a control device connected with the controlled terminal, the control terminal sends control instructions of a mouse and a keyboard to the bottom board controller, and a network card module of the bottom board controller acquires the control instructions and sends the control instructions to the processor for processing. And sending a power supply power-down instruction to a bottom plate controller in the ARM server through the application and control terminal, and starting a power supply key by the bottom plate controller after the bottom plate controller receives the power supply power-down instruction of the server so that the power supply key is in a pressed state. It should be noted that, the embodiment of the present invention has no special requirement on the application and control terminal, and only needs to have a browser and be capable of performing remote connection with the controlled terminal, so that remote control can be performed through any networked computer at any time and any place. According to the embodiment of the invention, the external power supply supplies power to the bottom board controller, so that the bottom board controller can operate independently of the state of the controlled terminal, an ARM embedded system on the bottom board controller can operate no matter whether the power supply of the controlled terminal works, and even if the controlled terminal cannot be automatically restarted due to abnormal power failure, the controlled terminal can be subjected to cold start starting and starting through the remote application and control terminal. The embodiment of the invention is characterized in that a BMC module is arranged on the control device, the control device is connected with the controlled terminal through the IPMB interface, and the operation information of the ARM server mainboard is fed back to the administrator of the control terminal. By adopting the technical scheme, the user can remotely control the power supply of the ARM server at the application and control terminal, and the power supply of the server is manually controlled on site, so that the time of managers is saved, and the control efficiency is improved.
In some embodiments, the ARM server is quite simple to maintain when running and supported by a control system, the management of the server can be realized through remote management software, the management of the server cannot only stay at the level of an operating system, and high-level software of the ARM server can be allowed to communicate with a hardware layer through a certain standard from a bottom layer, so that the management of the server is more complete and transparent. An Intelligent Platform Management Interface (IPMI) is originated from the field of servers, and aims to provide functions of equipment management, sensor event management, user management, remote maintenance and the like for the servers. The IPMI has the characteristics of standardization, separation of a management channel and a service channel, rich command set, high safety and the like. The IPMI has high applicability due to the characteristic that the management channel and the service channel of the IPMI are separated, the power supply of an IPMI subsystem is independent, the IPMI is independent from the service management system and still has operability even when the service system fails, the IPMI is an intelligent management platform interface based on the Internet, the core of the IPMI is a server processor or a Baseboard Management Controller (BMC) which does not depend on the processor, the BIOS or an operating system of the server to work, the baseboard management controller can independently run in the system without an agent management subsystem, the IPMI can start to work as long as BMC and IPMI firmware are available, and a BMC chip can be arranged on a mainboard of an ARM server to provide IPMI support for the server mainboard through the BMC. The good autonomy of IPMI overcomes the limitation of the management mode based on the operating system in the past, for example, the operating system can still perform the operations of startup and shutdown, information extraction and the like under the condition that the operating system does not respond or is not loaded.
In some embodiments, the server power input is typically 220V AC, and the 220V AC is coupled to the server power input via a power cord. The 220V alternating current is converted into two direct currents of P12V _ main and P12V _ STBY in the server power supply. The two kinds of power are 12V voltage, and the difference is that the current provided by P12V _ main is larger, and in addition, the P12V _ main needs to receive a power supply enabling signal to be converted into the output voltage of the system mian power for other chips or components. And the current provided by the P12V _ STBY is smaller, the P12V _ STBY automatically outputs voltage after being inserted into an AC line, and the control of a power supply enable signal is not carried out.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
In order to implement the above-mentioned server power-down control method, fig. 2 is a block diagram of a server power-down control apparatus according to an embodiment of the present invention, where the apparatus is applied to a server using an advanced risc machine, and the apparatus includes:
a monitoring event creating module 201, configured to set a monitoring event in an input/output system of the ARM server, where the monitoring event is whether an accumulated time length of the power key in a pressed state is less than a preset time threshold; the power supply key is in a pressed state, and the power supply key is converted from a high level to a low level and then from the low level to the high level;
a monitoring event monitoring module 202, configured to monitor whether a monitoring event occurs through the input/output system when the microprocessor is in a working state;
the first data processing module 203 is configured to, when it is monitored that the monitoring event occurs, determine that the power button is in a short-press state, invoke a shutdown control function through an extensible firmware interface UEFI on the microprocessor, and send a first control instruction based on a power state coordination interface protocol PSCI to the microprocessor;
the second data processing module 204 is configured to convert the first control instruction into a second control instruction based on a system control management protocol SCMI through the microprocessor, and execute a shutdown operation of the server power according to the second control instruction.
The embodiment of the invention discloses a power supply power failure control device of a server, which is applied to an ARM server, wherein the ARM server comprises a microprocessor and a power supply key, a monitoring event is set in an input and output system of the ARM server, whether the power supply key is in a pressed state or not is judged through the monitoring event, after the power supply key is determined to be in a short-time pressed state, a power-off control function is called through an extensible firmware interface on the microprocessor, a first control instruction based on a power supply state coordination interface protocol PSCI is sent to the microprocessor, and the first control instruction is converted into a second control instruction based on a system control management protocol SCMI, so that the power supply of the server executes power-off operation according to the second control instruction. By adopting the technical scheme, the ARM server can realize the power-off function of short-time pressing of the power key through monitoring the event, the real-time power-off requirement of the ARM server on equipment in the research, development, operation and maintenance processes is facilitated, the time for a user to control the server to be powered off is saved, and the use of the user is facilitated.
In an optional embodiment, the ARM server includes at least one set of motherboard and a backplane, the motherboard and the backplane are both connected to a power supply of the server, the motherboard is provided with the microprocessor, the backplane is provided with a backplane controller, the backplane controller is connected to the power supply key, and the apparatus further includes:
and the power supply key starting module is used for starting the power supply key by the bottom plate controller after the bottom plate controller receives a power-down command of a server power supply so as to enable the power supply key to be in a pressed state.
In an optional embodiment, a timer is further disposed on the ARM server, and the timer is configured to count an accumulated time length of the power key in the pressed state.
In an alternative embodiment, the monitoring event creating module 201 may include:
the first timing submodule is used for recording first time when the timer starts timing when the power supply key is converted from a high level to a low level;
the second timing submodule is used for finishing timing by the timer when the power supply key is converted from a low level to a high level after the timer starts timing, and recording second time when the timer finishes timing;
and the third timing submodule is used for calculating the accumulated time length between the first time and the second time.
In an optional embodiment, the shutdown control function is an SMC function, the power management protocol is a power state coordination interface protocol PSCI, the first data processing module 203 is further configured to call the SMC function through an extensible firmware interface on the microprocessor, so as to send the first control instruction based on the PSCI to the microprocessor through the SMC function, and the microprocessor converts the first control instruction into a second control instruction based on a system control management protocol SCMI, so that the server power performs a shutdown operation of the server power according to the second control instruction.
In an alternative embodiment, the preset time threshold is 3 seconds.
In an optional embodiment, the ARM server is further provided with a controlled terminal, and the controlled terminal is connected with the execution and control terminal through a network and receives a control instruction sent by the execution and control terminal.
In an alternative embodiment, the controlled terminal is disposed on a substrate controller of the backplane.
On the other hand, an embodiment of the present invention further provides a terminal, where the terminal includes: the server power supply power failure control method comprises a processor, a memory and a computer program which is stored on the memory and can run on the processor, wherein the computer program realizes the steps of the server power supply power failure control method when being executed by the processor. The memory is used for storing the execution instructions and may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as static access memory (SRAM), erasable programmable read-only memory (EPROM), and the like. The processor is a control center of the storage terminal, links various parts of the whole electronic terminal by various interfaces and lines, runs a software program in the memory, and calls data in the memory to execute functions of the electronic terminal, such as integrated circuit (integrated circuit). The communication unit is used for establishing a communication channel, so that the storage terminal and other terminals can communicate, receive or send data and the like.
In another aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the server power down method.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or terminal apparatus that comprises the element.
The server power supply power failure control device and the server power supply power failure control method provided by the invention are introduced in detail, specific examples are applied in the text to explain the principle and the implementation mode of the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A power supply power failure control method for a server is characterized by being applied to a server adopting an advanced reduced instruction set ARM, wherein the ARM server comprises a microprocessor and a power supply key, and the method comprises the following steps:
setting a monitoring event in an input/output system of the ARM server, wherein the monitoring event is whether the accumulated time length of the power key in a pressed state is less than a preset time threshold value; the power key is in a pressed state and comprises the steps that after the power key is converted from a high level to a low level, the power key is converted from the low level to the high level;
when the microprocessor is in a working state, monitoring whether the monitoring event occurs or not through the input and output system;
when the monitoring event is monitored, determining that the power supply key is in a short-press state, and calling a shutdown control function through an extensible firmware interface (UEFI) on the microprocessor so as to send a first control instruction based on a power supply state coordination interface Protocol (PSCI) to the microprocessor;
and converting the first control instruction into a second control instruction based on a system control management protocol SCMI (Single chip computer interface), and executing shutdown operation of the power supply of the server according to the second control instruction by the microprocessor.
2. The method of claim 1, wherein the ARM server comprises at least one set of a motherboard and a backplane, the motherboard and the backplane both connected to a power supply of the server, the motherboard having the microprocessor disposed thereon, the backplane having a backplane controller disposed thereon, the backplane controller connected to the power button, the method further comprising:
and when the bottom board controller receives a power-down command of a server power supply, the bottom board controller starts the power supply key so as to enable the power supply key to be in a pressed state.
3. The method of claim 1, wherein a timer is further installed on the ARM server, and the timer is used for counting the accumulated time duration of the power key in the pressed state.
4. The method of claim 3, wherein calculating a cumulative duration that the power key is in the depressed state comprises:
when the power supply key is converted from a high level to a low level, recording first time when the timer starts timing;
after the timer starts to time, when the power key is converted from a low level to a high level, the timer finishes timing and records a second time when the timer finishes timing;
and calculating the accumulated time length between the first time and the second time.
5. The method of claim 1, wherein the preset time threshold is 3 seconds.
6. The utility model provides a server power supply power down control device which characterized in that is applied to advanced reduced instruction set ARM server, ARM server includes microprocessor and power button, the device includes:
the monitoring event creating module is used for setting a monitoring event in an input and output system of the ARM server, wherein the monitoring event is whether the accumulated time length of the power key in a pressed state is less than a preset time threshold value; the power supply key is in a pressed state, and the power supply key is converted from a high level to a low level and then from the low level to the high level;
the monitoring event monitoring module is used for monitoring whether the monitoring event occurs or not through the input and output system when the microprocessor is in a working state;
the first data processing module is used for determining that the power key is in a short-press state when the monitoring event is monitored to occur, and calling a shutdown control function through an extensible firmware interface UEFI on the microprocessor so as to send a first control instruction based on a power state coordination interface protocol PSCI to the microprocessor;
and the second data processing module is used for converting the first control instruction into a second control instruction based on a system control management protocol SCMI (Single chip computer interface), and executing shutdown operation of the power supply of the server according to the second control instruction.
7. The apparatus of claim 6, wherein the ARM server comprises at least one set of a motherboard and a backplane, the motherboard and the backplane are both connected to a power supply of the server, the motherboard is provided with the microprocessor, the backplane is provided with a backplane controller, the backplane controller is connected to the power key, the apparatus further comprises:
and the power supply key starting module is used for starting the power supply key by the bottom plate controller after the bottom plate controller receives a power-down command of a server power supply so as to enable the power supply key to be in a pressed state.
8. The apparatus of claim 6, wherein the monitor event creation module comprises:
the first timing submodule is used for recording first time when the timer starts timing when the power supply key is converted from a high level to a low level;
the second timing submodule is used for finishing timing by the timer when the power supply key is converted from a low level to a high level after the timer starts timing, and recording second time when the timer finishes timing;
and the third timing submodule is used for calculating the accumulated time length between the first time and the second time.
9. A terminal, comprising: processor, memory and a computer program stored on the memory and being executable on the processor, the computer program realizing the steps of the method according to any of the claims 1-5 when executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
CN202211214526.0A 2022-09-30 2022-09-30 Server power supply power failure control method, device, terminal and storage medium Pending CN115525133A (en)

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CN202211214526.0A CN115525133A (en) 2022-09-30 2022-09-30 Server power supply power failure control method, device, terminal and storage medium

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