CN1155157C - Low clock feed-through charge pumping circuit - Google Patents
Low clock feed-through charge pumping circuit Download PDFInfo
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- CN1155157C CN1155157C CNB991236912A CN99123691A CN1155157C CN 1155157 C CN1155157 C CN 1155157C CN B991236912 A CNB991236912 A CN B991236912A CN 99123691 A CN99123691 A CN 99123691A CN 1155157 C CN1155157 C CN 1155157C
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Abstract
The present invention relates to a low clock feed-through charge pump circuit for a phase-locked loop, which comprises a first pump transistor, a second pump transistor, a first switching device, a second switching device, a third switching device, a fourth switching device, a first wide-amplitude wobble current mirror circuit and a second wide-amplitude wobble current mirror circuit, wherein the first wide-amplitude wobble current mirror circuit and the second wide-amplitude wobble current mirror circuit are respectively composed of overlapped transistor circuits and biasing circuits and used for providing bias required by the low clock feed-through charge pump. The four switching devices and four overlapped transistor circuits are composed of transistors working in a saturated work area. Therefore, the present invention can reduce the phenomena of charge injection and frequency deviation.
Description
Technical field
The invention relates to a kind of phase-locked loop (phase-locked loop, PLL) circuit, and particularly relevant for the charge pumping in a kind of phase-locked loop (charge pump) circuit.
Background technology
Because semiconductor technology is significantly progressive at present, make that the running speed of computer in modern age is more and more faster, but then, along with the raising of operation frequency, the power that is consumed is also high more, in order to reduce the consumption of power, therefore the running voltage of computer also reduces gradually now, dropped to 3.3V by former 5V, more reduce to 2.5V till now, even may reduce to below the 2.0V.Along with the reduction of supply voltage, many circuit also need to revise thereupon, so that it can be worked under the condition of low-voltage, for example provide the oscillator of clock.Because at present computer system is used the clock of multiple frequency simultaneously in running, wherein major part is all used phase-locked loop, produces other frequency clocks of different proportion by a reference clock, uses so that a plurality of subsystems in the system to be provided.A major part that influences the performance of phase-locked loop is a voltage-controlled oscillator.The performance of assessment voltage-controlled oscillator can be according to its long-range and short distance frequency shift (FS) (long term jitter and short term jitter) and the situation that influences that is subjected to power supply voltage variation.
Please refer to Fig. 1, it illustrates a kind of block diagram of phase-locked loop circuit.Phase-locked loop circuit consist essentially of phase detectors 10, charge pumping 12, low pass filter (lowpass filter, LPF) 14 with voltage-controlled oscillator (voltage control oscillator, VCO) 16.Generally speaking, if the fluctuations of the voltage signal of input voltage control generator 16 is more little, then the frequency shift (FS) of its output voltage just can be more little, and phase-locked loop just has way that stable electric voltage frequency output is arranged thus.For the fluctuations of the voltage signal that will make input voltage control generator 16 is more little, two current sources in the charge pumping 12 just will equate.
Please refer to Fig. 2, it illustrates the circuit diagram of the charge pumping of the known technology among Fig. 1.Switch SW 1, SW1, SW2 and SW2 are made of the transistor of operating under linear zone.When transistor was closed from being conducting to, the electric charge that is stored in drain electrode must disengage, and caused electric charge to inject phenomenon (chargeInjection).If it is few more to be stored in the electric charge of drain electrode, then the influence of electric charge injection is just more little, so can be so that the control voltage of VCO is almost motionless.Switch SW 1 is operated under linear zone with SW2, therefore between its Push And Release, can be in transistorized passage stored charge, and near the electric charge that major part is stored in the drain electrode end can be disengaged, and this can impact the magnitude of voltage of output.
Transistor Q gives transistor T 2 with the electric current I mirror, and current source I2.Therefore when if the voltage of node P3 equals the voltage of node P4, then can be so that current source I2 is identical with the magnitude of current of transistor T 2.The voltage of supposing node P4 is at certain certain value, if the voltage of node P3 is greater than the value of node P4, because the relation of passage modulation will cause electric current I 1 to be slightly larger than I2.Yet the inevitable voltage greater than P4 of the voltage of node P2 become a diode configuration because the grid of transistor T 1 couples with drain electrode, will make and flow through transistor T 1 and understand different with the electric current of T2 if the voltage of node P2 equals the voltage of node P4.The electric current of current source I3 is produced by transistor T 1 mirror, so the electric current of current source I3 is identical with the electric current that flows through transistor T 1.Therefore, just on the whole, current source I2 and I3 are also unequal.Current source I3 can be greater than I2.The difference of current source I2 and I3 is big more, pass through low pass filter 14 again after, the fluctuating of its change in voltage just can be very big.Therefore, cause the frequency shift (FS) of the output voltage of voltage-controlled oscillator 14 just can be big more.
In addition, the transistor that operates in linear zone can be considered as resistance, and the change in voltage of output point can cause node P1 and P4 to exert an influence, and then changes the value of I2 and I3.
Summary of the invention
Therefore the present invention proposes a kind of low clock feed-through charge pumping circuit, the main switching transistor of its formation is to work under the saturation region, and the phenomenon that makes in the charge pumping transistorized electric charge as switch inject is very not obvious.
A kind of low clock feed-through charge pumping circuit (low clodk feed-throughcharge pump circuit) that the present invention proposes, the transistor of its formation is to work under the saturation region, make the magnitude of current of the current source in the charge pumping equate, and make and under the environment of low-work voltage, work.
A kind of low clock feed-through charge pumping circuit that the present invention proposes, it can significantly reduce the frequency shift (FS) of the floating of the signal that is input to voltage-controlled oscillator with the output signal of reduction voltage-controlled oscillator, and the frequency of the output signal of phase-locked loop is stablized.
Low clock feed-through charge pumping circuit proposed by the invention, it is summarized as follows:
A kind of low clock feed-through charge pumping circuit comprises: first and 1 second pumping transistor, and the transistorized source electrode of first pumping is coupled to a power supply, and the transistorized source electrode of second pumping then is coupled to a ground wire, respectively as the usefulness of current source.First to fourth switching device, respectively have first, second and the 3rd end, first end of first and second switching device and the first pumping transistor drain couple, and second end of the 3rd and the 4th switching device and the second pumping transistor drain couple, first with second end of this second switch device respectively with first end of the 3rd and the 4th switching device, and the 3rd end of first and second switching device is coupled to each other, and the 3rd end of the 3rd and the 4th switching device is coupled to each other.Two groups of swing current mirrors of wide cut (wide-swing current mirror) are in order to provide low clock feed-through charge pumping needed bias voltage.Accurate and the needed supply voltage of bias circuit more stacked (cascode) current mirror that the electric current that utilizes the swing current mirror of wide cut to make to be produced is more known is low.First group of swing current mirror of wide cut is mainly a stacked transistor circuit (cascodetransistor circuit), be coupled between power supply and the ground wire, it is made of two stacked institutes of transistor, wherein the grid of the first transistor all is couple to the 3rd end of first switching device, and the grid of transistor seconds then is coupled to the drain electrode of transistorized grid of first pumping and the first transistor.Second group of swing current mirror of wide cut is mainly a stacked transistor circuit, it is made of two stacked institutes of transistor, the grid of the first transistor wherein is couple to the 3rd end of the 4th switching device, and the grid of the transistor seconds of the second stacked transistor circuit then is coupled to the drain electrode of transistorized grid of second pumping and the first transistor.Second group of swing current mirror of wide cut also provides first group of needed bias current of the swing current mirror of wide cut.The input current source is coupled to the drain electrode of the first transistor of the second stacked transistor circuit and the grid of transistor seconds, in order to the input current of low clock feed-through charge pumping circuit to be provided.
Transistor by first and second group wide cut swing current mirror is worked under the saturation region, makes to have the magnitude of current that equates as first of current source with one second pumping transistor.In addition, the main transistor that constitutes first to fourth switching device is worked under the saturation region.By low clock feed-through charge pumping circuit of the present invention, can significantly reduce the floating of the signal that is input to voltage-controlled oscillator, the frequency shift (FS) of the output signal of voltage-controlled oscillator just can reduce, and makes that the frequency of output signal of phase-locked loop is stablized.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Brief description of drawings:
Fig. 1 illustrates the phase-locked loop circuit block diagram;
Fig. 2 illustrates the circuit diagram of known charge pumping circuit; And
Fig. 3 illustrates the details drawing according to low clock feed-through charge pumping circuit of the present invention.
Embodiment
Please refer to Fig. 3, it illustrates the details drawing according to low clock feed-through charge pumping circuit of the present invention.In the present embodiment, the first pumping transistor C1 is to use P-type mos (p-typemetal-oxide semiconductor, PMOS) transistor, and the second pumping transistor C2 is N type metal oxide semiconductor (n-type metal-oxide semiconductor, NMOS) transistor.Transistor M1～the M6 that constitutes first and second switching device 22a, 22b is the PMOS transistor; And the transistor M7～M12 that constitutes the 3rd and the 4th switching device 22c, 22d is a nmos pass transistor.Constituting transistor M13, the M14 of the first stacked transistor circuit 24a and M15, M16 and the Q of bias circuit 27b is the PMOS transistor; Transistor M17～M29 of second stacked transistor circuit 26a～26d and circuit 27a is made of nmos pass transistor., be not below in order to restriction the present invention only as example.
A kind of low clock feed-through charge pumping circuit 20, it has first and second pumping transistor C1, C2, and the source electrode of the first pumping transistor C1 is coupled to a power Vcc, and the source electrode of the second pumping transistor C2 then is coupled to a ground wire, respectively as the usefulness of current source.
First to 1 the 4th switching device 22a～22d, respectively has first (the node N1, N4, N7 and N10), second (the node N2, N5, N8 and N11) and the 3rd end (node N3, N6, N9 and N12), first and second switching device 22a, the first end N1 of 22b, the drain electrode of the N4 and the first pumping transistor C1 couples, and the 3rd and the 4th switching device 22c, the second end N8 of 22d, the drain electrode of the N11 and the second pumping transistor C2 couples, first and second switching device 22a, the second end N2 of 22b, N5 respectively with the 3rd and the 4th switching device 22c, the first end N7 of 22d, N10 couples.In addition, the 3rd end N3, the N6 of first and second switching device 22a, 22b are coupled to each other; The 3rd end N9, the N12 of the 3rd and the 4th switching device 22c, 22d are coupled to each other.
In this embodiment, first to the 4th above-mentioned switching device 22a～22d is all constituted with three transistors.With the first switching device 22a is example, and switching device 22a is mainly switching transistor M1, and it is worked under the saturation region.The drain electrode of the source electrode of transistor M1 and the first pumping transistor C1 couples.The source electrode of oxide-semiconductor control transistors M2 is coupled to power Vcc and its drain electrode is coupled to the grid of transistor M1.Another oxide-semiconductor control transistors M3 is coupled between the grid of node N3 and transistor M1.By this configuration, can make transistor M1 when conducting, its grid voltage is a little more than Vcc/2, rather than known 0V.Therefore, transistor M1 may operate in the saturation region, and can not enter linear zone.In like manner, transistor M4, M7 and the M10 that constitutes switching device 22b, 22c and 22d also all operates under the saturation region.
Transistor M2 and M3 then work under linear zone.When transistor M2 conducting and transistor M3 when closing, the grid voltage of transistor M1 becomes Vcc, and this just makes transistor M1 close.When transistor M2 closes and during transistor M3 conducting, the node voltage that the grid voltage of transistor M1 is subjected to node N3 determines, and the voltage of node N3 is determined by bias circuit 27b.Therefore, the conducting voltage of transistor M1 just be the voltage of node N3 to Vcc, but not 0V is to Vcc.Moreover because transistor M1 conducting is when working under the saturation region, the equivalent capacity of drain electrode is little when operating under linear zone than M1.Thus, M1 is when saturation region operation, and the electric charge the when electric charge that is stored in drain electrode just operates in linear zone than M1 is few.When not conducting of M1, the electric charge that is caused injects phenomenon and becomes more not obvious.This has great help for the voltage of stablizing control oscillation circuit.
First stacked (cascode) transistor circuit 24a and the circuit 27b is made of with (M15, M16, Q) transistor (M13, M14) respectively.The first stacked transistor circuit 24a, in order to the current source that provides the first pumping transistor C1 one to fix, it is serially connected in stacked (cascode) mode by transistor M13 and M14, wherein the grid of transistor M14 is couple to the 3rd end N3 of the first switching device 22a, the grid of transistor M13 then is coupled to the grid of the first pumping transistor C1, and the grid of the drain electrode of transistor M14 and transistor M13 couples.Bias circuit 27b, it is serially connected in stacked (cascode) mode by transistor M15 and M16, wherein the grid of transistor M16 is couple to the 3rd end N3 of the first switching device 22a, and the grid of transistor M15 then is coupled to a load Q, and the drain electrode of transistor M16 couples with grid.The first stacked transistor circuit 24a and bias circuit 27b constitute a current mirror (current mirror) device, in order to the current source that provides the first pumping transistor C1 one to fix.
Two groups of swing current mirrors of wide cut (wide-swing current mirror) 19a, 19b are in order to provide low clock feed-through charge pumping needed bias voltage.Accurate and the needed supply voltage of bias circuit that the electric current that utilizes the swing current mirror 19a of wide cut, 19b to make to be produced is more known is lower.First group of swing current mirror of wide cut is mainly the aforesaid first stacked transistor circuit 24a and bias circuit 27b constitutes, and constitutes and second group of swing current mirror of wide cut is mainly the aforesaid second stacked transistor circuit 26a, 26b, 26c, 26d and bias circuit 27a.
Stacked transistor circuit 26a, 26b and 26c among second group of swing current mirror 19b of wide cut are respectively coupled between first group of swing current mirror 19a of wide cut and bias circuit 27b and the ground wire.Stacked transistor circuit 26a, 26b, 26c, the second stacked transistor circuit 26d and bias circuit 27a are respectively by transistor (M17, M18), (M19, M20), (M12, M22), (M23, M24), (M27, M28, M29) constitutes, wherein the grid of transistor M17, M19, M21, M23 all is couple to the 3rd end N9 of the 3rd switching device 22c, and the grid of another transistor M18, M20, M22, M24 then is coupled to the grid of the second pumping transistor C2.Transistor M13, the M14, M16, M17～27, the M29 that wherein constitute first and second stacked transistor circuit 24a, 26d and 26a, 26b, 26c, 27a, 27b work under the saturation region.
The input current source I1 of charge pumping 20 in the mirror mode with electric current from the 26d mirror to stacked transistor, make the electric current that flows through the first stacked transistor 24a identical with input current source I1.From the node N5 of voltage-controlled oscillator (VCO), transistor M10 and transistor C2 (current source) constitute a stacked configuration, so equal I1 via the 26d mirror to the electric current of C2.Moreover transistor C1 and transistor M4 also constitute stacked configuration, equate with the electric current that flows through stacked transistor 24a so flow through the electric current of transistor C1.Moreover, because the electric current that flows through 24a equals I1, so the magnitude of current that is flow through as first and second pumping transistor C1, the C2 of current source is just equal.Therefore, utilize stacked transistor can improve the too big shortcoming of magnitude of current difference of two current sources of known charge pumping.
Transistor M1, M4, M7 and M10 in the charge pumping circuit of the present invention work under the saturation region, so the phenomenon that the electric charge that can be greatly improved injects.By low clock feed-through charge pumping circuit of the present invention, accurately Control current source C1 equates with the magnitude of current of C2, makes that the signal that outputs to voltage-controlled oscillator (VC0) can be very smooth-going, and it is minimum promptly to rise and fall.Therefore, the frequency shift (FS) of the output signal of voltage-controlled oscillator just can reduce, and makes that the frequency of output signal of phase-locked loop is stablized.
To sum up, because transistor M1, M4, M7 and M10 operate under the saturation region, so when its conducting, electric charge can be accumulated in the side by source electrode, and the coupling capacitance of drain electrode end is also little during operation under linear zone, and transistorized grid voltage changes and less, so it is less to be stored in the electric charge of drain electrode end, so when transistor was closed, electric charge was also few a lot of from the amount that drain electrode end is released out, and is therefore just very little to the magnitude of voltage influence of output point.In addition, according to design of the present invention, transistor M1, M4, M7 and M10 operate under the saturation region, so the change in voltage of its output point is difficult to influence the transistorized electric current of C1, C2.Moreover, constitute a stacked framework with transistor C1, C2 as current source, make electric current that transistor C1, C2 provided very near the electric current I 1 in input current source.
Therefore, feature of the present invention is the stacked transistor AND gate switching transistor configuration that has in saturation region operation, makes the magnitude of current of two current sources that charge pumping is interior equate.
Another feature of the present invention is that the transistor circuit as switching device has to finish drilling at the transistor of saturation region operation and at linear zone and does in order to control this transistorized two transistors, so as to eliminating electric charge injection phenomenon.
It is highly stable that another feature of the present invention is that charge pumping is exported to the voltage of voltage-controlled oscillator, do not have violent fluctuations, so the frequency shift (FS) effect can be improved significantly.
A feature more of the present invention is that the phase-locked loop of using low clock feed-through charge pumping circuit of the present invention can have stable electric voltage frequency output.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (23)
1. low clock feed-through charge pumping circuit, this low clock feed-through charge pumping circuit comprises:
One first and one second pumping transistor, the transistorized source electrode of this first pumping is coupled to a power supply, and the transistorized source electrode of this second pumping then is coupled to a ground wire, respectively as the usefulness of current source;
One first to 1 the 4th switching device, respectively have one first, one second and one the 3rd end, this first couples with this first end and this first pumping transistor drain of this second switch device, and this second end of the 3rd and the 4th switching device and this second pumping transistor drain couple, this first couples with this first end of the 3rd and the 4th switching device respectively with this second end of this second switch device, and this first is coupled to each other with the 3rd end of this second switch device, and the 3rd be coupled to each other with the 3rd end of the 4th switching device, it is characterized in that wherein this first comprises more respectively with the 4th switching device:
One switching transistor is to be conductively coupled to this first pumping transistor, and this switching transistor is to work under the saturation region, and
One first and one second oxide-semiconductor control transistors, be respectively in linear zone work, wherein this first oxide-semiconductor control transistors is to be coupled between the grid of this power supply and this switching transistor, and this second oxide-semiconductor control transistors is to be coupled between the grid of the 3rd end and this switching transistor;
One first group of swing current mirror of wide cut (wide-swing current mirror), in order to provide this low clock feed-through charge pumping needed bias voltage, it is coupled to the 3rd end of this power supply, the transistorized grid of this first pumping and this first switching device; And
One second group of swing current mirror of wide cut, it is coupled to the 3rd end of this earth terminal, the transistorized grid of this second pumping and the 4th switching device.
2. low clock feed-through charge pumping circuit as claimed in claim 1 is characterized in that this first group of swing current mirror of wide cut also comprises:
One first stacked transistor circuit, be coupled between this power supply and this ground wire, it is made of two overlapping institutes of transistor, wherein the grid of a first transistor of this first stacked transistor circuit all is couple to the 3rd end of this first switching device, and the grid of a transistor seconds then is coupled to the drain electrode of the transistorized grid of this first pumping and this first transistor; And
One first current bias circuit couples with this first stacked transistor circuit.
3. low clock feed-through charge pumping circuit as claimed in claim 1 is characterized in that this second group of swing current mirror of wide cut also comprises:
One second stacked transistor circuit, it is made of two stacked institutes of transistor, wherein the grid of the first transistor of this second stacked transistor circuit is couple to the 3rd end of the 4th switching device, the grid of the transistor seconds of this second stacked transistor circuit then is coupled to the drain electrode of the transistorized grid of this second pumping and this first transistor, one input current source is coupled to the drain electrode of the first transistor of this second stacked transistor circuit, in order to the input current of this low clock feed-through charge pumping circuit to be provided.
A plurality of stacked transistor circuits are coupled between this first current bias circuit, this first stacked transistor circuit, this second stacked transistor circuit, the 4th switching device and this second pumping transistor; And
One second current bias circuit, (cascode transistorcircuit) couples with described stacked transistor circuit.
4. low clock feed-through charge pumping circuit as claimed in claim 3 is characterized in that each described stacked transistor circuit constitutes by two transistors are stacked at least.
5. low clock feed-through charge pumping circuit as claimed in claim 1 is characterized in that this first pumping transistor is the PMOS transistor.
6. low clock feed-through charge pumping circuit as claimed in claim 1 is characterized in that this second pumping transistor is a nmos pass transistor.
7. low clock feed-through charge pumping circuit as claimed in claim 1, it is characterized in that constituting this first with the described transistor of this second switch device be the PMOS transistor.
8. low clock feed-through charge pumping circuit as claimed in claim 1, it is characterized in that constituting the 3rd with the described transistor of the 4th switching device be nmos pass transistor.
9. low clock feed-through charge pumping circuit as claimed in claim 1, it is characterized in that constituting this first with the described transistor of this second stacked transistor circuit be to be respectively PMOS and nmos pass transistor.
10. low clock feed-through charge pumping circuit, this low clock feed-through charge pumping circuit comprises:
One first and one second pumping transistor, the transistorized source electrode of this first pumping is coupled to a power supply, and the transistorized source electrode of this second pumping then is coupled to a ground wire, respectively as the usefulness of current source; One first to 1 the 4th switching device, respectively have one first, one second and one the 3rd end, this first couples with this first end and this first pumping transistor drain of this second switch device, and this second end of the 3rd and the 4th switching device and this second pumping transistor drain couple, this first with this second end of this second switch device respectively with this first end of the 3rd and the 4th switching device, and this first is coupled to each other with the 3rd end of this second switch device, and the 3rd be coupled to each other with the 3rd end of the 4th switching device, it is characterized in that wherein this first also comprises respectively with the 4th switching device:
One switching transistor is to be conductively coupled to this first pumping transistor, and this switching transistor is to work under the saturation region, and
One first and one second oxide-semiconductor control transistors, be respectively in linear zone work, wherein this first oxide-semiconductor control transistors is to be coupled between the grid of this power supply and this switching transistor, and this second oxide-semiconductor control transistors is to be coupled between the grid of the 3rd end and this switching transistor;
One the first transistor, its grid is coupled to the transistorized grid of this first pumping jointly with drain electrode, and source electrode is coupled to this power supply;
One transistor seconds, its grid are coupled to the transistorized grid of this second pumping, and source electrode is coupled to this ground wire, and the drain electrode of this transistor seconds then is coupled to the drain electrode of this first transistor; And
One the 3rd transistor, its grid and drain electrode are coupled to the grid of this transistor seconds jointly, and drain electrode is coupled to an input current source, source ground.
11. low clock feed-through charge pumping circuit as claimed in claim 10 is characterized in that this first pumping transistor is the PMOS transistor.
12. low clock feed-through charge pumping circuit as claimed in claim 10 is characterized in that this second pumping transistor is a nmos pass transistor.
13. low clock feed-through charge pumping circuit as claimed in claim 10, it is characterized in that constituting this first with the described transistor of this second switch device be the PMOS transistor.
14. low clock feed-through charge pumping circuit as claimed in claim 10, it is characterized in that constituting the 3rd with the described transistor of the 4th switching device be nmos pass transistor.
15. a charge pumping circuit that is applied in the phase-locked loop, it is coupled between the phase detectors and low pass filter in this phase-locked loop, and this charge pumping circuit comprises:
One first and one second pumping transistor, the transistorized source electrode of this first pumping is coupled to a power supply, and the transistorized source electrode of this second pumping then is coupled to a ground wire, respectively as the usefulness of current source;
One first to 1 the 4th switching device, respectively have one first, one second and one the 3rd end, this first couples with this first end and this first pumping transistor drain of this second switch device, and this second end of the 3rd and the 4th switching device and this second pumping transistor drain couple, this first with this second end of this second switch device respectively with this first end of the 3rd and the 4th pass device, and this first is coupled to each other with the 3rd end of this second switch device, and the 3rd be coupled to each other with the 3rd end of the 4th switching device, it is characterized in that wherein this first also comprises respectively with the 4th switching device:
One switching transistor is to be conductively coupled to this first or second pumping transistor, and this switching transistor is to work under the saturation region, and
One first and one second oxide-semiconductor control transistors, be respectively in linear zone work, wherein this first oxide-semiconductor control transistors is to be coupled between the grid of this power supply and this switching transistor, and this second oxide-semiconductor control transistors is to be coupled between the grid of the 3rd end and this switching transistor;
One first stacked transistor circuit, be coupled between this power supply and this ground wire, it is made of two stacked institutes of transistor, wherein the grid of a first transistor of this first stacked transistor circuit is couple to the 3rd end of this first switching device, and the grid of a transistor seconds then is coupled to the drain electrode of the transistorized grid of this first pumping and this first transistor; And
One second stacked transistor circuit, it is made of two stacked institutes of transistor, wherein the grid of the first transistor of this second stacked transistor circuit is couple to the 3rd end of the 4th switching device, the grid of the transistor seconds of this second stacked transistor circuit then is coupled to the transistorized grid of this second pumping, one input current source is coupled to the drain electrode of the first transistor of this second stacked transistor circuit and the grid of transistor seconds, in order to the input current of this low clock feed-through charge pumping circuit to be provided.
16. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 15 is characterized in that also comprising:
One first and one second electric current provides transistor circuit, first couples with this second stacked transistor circuit with this respectively.
17. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 16 is characterized in that also comprising that a plurality of bias transistor circuit are coupled to this first electric current and provide between transistor circuit (first corrent supply transistor circuit), this first stacked transistor circuit, this second stacked transistor circuit, the 4th switching device and this second pumping transistor.
18. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 17 is characterized in that each described bias transistor circuit constitutes by two transistors are stacked at least.
19. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 15 is characterized in that this first pumping transistor is the PMOS transistor.
20. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 15 is characterized in that this second pumping transistor is a nmos pass transistor.
21. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 15, it is characterized in that constituting this first with the described transistor of this second switch device be the PMOS transistor.
22. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 15, it is characterized in that constituting the 3rd with the described transistor of the 4th switching device be nmos pass transistor.
23. the charge pumping circuit that is applied in the phase-locked loop as claimed in claim 15 is characterized in that constituting this and first is respectively PMOS and nmos pass transistor with the described transistor of this second stacked transistor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991236912A CN1155157C (en) | 1999-11-05 | 1999-11-05 | Low clock feed-through charge pumping circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991236912A CN1155157C (en) | 1999-11-05 | 1999-11-05 | Low clock feed-through charge pumping circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1295380A CN1295380A (en) | 2001-05-16 |
| CN1155157C true CN1155157C (en) | 2004-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991236912A Expired - Lifetime CN1155157C (en) | 1999-11-05 | 1999-11-05 | Low clock feed-through charge pumping circuit |
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| CN (1) | CN1155157C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103973222B (en) * | 2013-01-31 | 2016-12-28 | 立锜科技股份有限公司 | Voltage-Controlled oscillation circuit and relevant bias circuit |
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1999
- 1999-11-05 CN CNB991236912A patent/CN1155157C/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| CN1295380A (en) | 2001-05-16 |
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Granted publication date: 20040623 |