CN115513776A - Semiconductor laser chip and preparation method thereof - Google Patents
Semiconductor laser chip and preparation method thereof Download PDFInfo
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- CN115513776A CN115513776A CN202110693966.8A CN202110693966A CN115513776A CN 115513776 A CN115513776 A CN 115513776A CN 202110693966 A CN202110693966 A CN 202110693966A CN 115513776 A CN115513776 A CN 115513776A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/2202—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure by making a groove in the upper laser structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/24—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a grooved structure, e.g. V-grooved, crescent active layer in groove, VSIS laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/305—Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure
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Abstract
The application discloses a semiconductor laser chip and a preparation method thereof. The semiconductor laser chip includes: the active layer is positioned in the functional layer, and the functional layer comprises a current injection region and a particle doping region positioned at the end part of the current injection region; the functional layer is provided with a groove, and the groove is positioned between the particle doping area and the current injection area. The semiconductor laser chip is simple in preparation process and high in process stability, and the semiconductor laser chip has a high COD threshold value.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and in particular, to a semiconductor laser chip and a method for manufacturing the same.
Background
Increasing Optical output power, improving reliability and working life are important research points in the field of semiconductor lasers, a COD (Catastrophic Optical Damage) threshold value is an important factor influencing the maximum output power of a semiconductor laser, and Catastrophic Optical mirror Damage is Catastrophic Damage which is caused by that a laser cavity surface region absorbs higher Optical radiation in a resonant cavity and the temperature exceeds the melting point of the laser cavity surface region after the laser cavity surface region absorbs the higher Optical radiation in the resonant cavity, so that the cavity surface is melted.
Particle doping is used as a method for improving the COD threshold, and the existing particle doping process has the problem of lateral diffusion, so that the luminous efficiency of a semiconductor laser is seriously influenced, and the COD threshold of the semiconductor laser is lower.
Disclosure of Invention
The application provides a semiconductor laser chip and a preparation method thereof, and the semiconductor laser chip has the advantages of simple structure, high stability and higher COD threshold value.
In order to solve the technical problem, the application adopts a technical scheme that: there is provided a semiconductor laser chip including: the active layer is positioned in the functional layer, and the functional layer comprises a current injection region and a particle doping region positioned at the end part of the current injection region; the functional layer is provided with a groove, and the groove is positioned between the particle doping area and the current injection area.
Furthermore, the current injection region is provided with a ridge platform, the groove is positioned between the ridge platform and the particle doping region, and the length direction of the groove is vertical to that of the ridge platform.
Further, the width of the ridge land is less than or equal to the length of the trench.
Further, the cross-sectional shape of the groove in the depth direction thereof is a rectangle, a square, a trapezoid, a parallelogram, or a triangle.
Further, the length of the groove ranges from: 70-120 μm, the width of the groove is 10-20 μm, and the depth of the groove is: 0.3-0.6 μm; the length range of the ridge table is: 1100 μm to 1700 μm, the width of the ridge mesa ranging from: 50 μm to 100 μm, and the height of the ridge table is in the range of: 1 μm to 2 μm.
Furthermore, both ends of the functional layer are provided with particle doped regions, and both opposite sides of the ridge-shaped platform are provided with grooves.
Further, the particles doped in the particle doping region include at least one of magnesium particles, zinc particles and aluminum particles.
In order to solve the above technical problem, another technical solution adopted by the present application is: a preparation method of a semiconductor laser chip is provided, which comprises the following steps: dividing a particle doping area at the end part of the functional layer, and etching a groove on the functional layer, wherein the groove is positioned between the particle doping area and a current injection area of the functional layer; and doping particles in the particle doping region.
Further, the step of doping the particle doping region with particles further includes: a ridge platform is formed in the current injection region of the functional layer such that the trench is located between the ridge platform and the particle doping region, the length direction of the trench being perpendicular to the length direction of the ridge platform.
Further, the width of the ridge land is less than or equal to the length of the trench.
The beneficial effects of the embodiment of the application are that: the semiconductor laser chip comprises an active layer and a functional layer, wherein the active layer is positioned in the functional layer, the functional layer provides electronic input for the active layer through an electrode so as to enable the semiconductor laser chip to emit light, a particle doping area is arranged at the end part of the functional layer, and a non-absorption window is formed on the cavity surface of the semiconductor laser chip so as to reduce the heat energy generated by light absorption of the light-emitting cavity surface and further improve the COD threshold value of the semiconductor laser chip; in addition, because the groove is arranged between the particle doping area and the current injection area, the current of the current injection area is not directly diffused to the cavity surface but blocked at the groove, so that the density of the current carriers injected to the cavity surface is reduced, the non-radiative recombination absorption can be reduced, and the COD threshold current is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment of a semiconductor laser chip provided in the present application;
fig. 2 is a schematic top view of the semiconductor laser chip of fig. 1;
FIG. 3 is a side cross-sectional schematic view of the semiconductor laser chip of FIG. 1;
FIG. 4 is a schematic diagram of the structure of the layers of the semiconductor laser chip of FIG. 1;
fig. 5 is a schematic flow chart diagram of an embodiment of a method for fabricating a semiconductor laser chip provided in the present application;
FIG. 6 is a flowchart illustrating an embodiment of step S11 in FIG. 5;
FIG. 7 is a flowchart illustrating an embodiment of step S12 in FIG. 5;
FIG. 8 is a schematic view of the structure of an epitaxial wafer and a trench;
FIG. 9 is a schematic diagram of the structure of FIG. 8 after the epitaxial wafer is coated with photoresist;
FIG. 10 is a schematic structural view of an epitaxial wafer, a doped particle source layer and a trench;
FIG. 11 is a schematic structural view of an epitaxial wafer, a doped particle source layer, and a silicon dioxide layer;
FIG. 12 is a schematic view of the structure of the epitaxial wafer after removal of the silicon dioxide layer and the doped particle source layer;
FIG. 13 is a schematic diagram of the structure after etching a ridge mesa on an epitaxial wafer;
fig. 14 is a schematic structural diagram of a semiconductor laser chip manufactured by the manufacturing method in fig. 5.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, the present application will be described in further detail with reference to the accompanying drawings and detailed description. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced in other ways than those described herein, and therefore the scope of the present application is not limited by the specific embodiments disclosed below.
The semiconductor laser is a device commonly used in the photoelectronic industry and has general application in the fields of optical communication, biotechnology, laser processing, illumination and the like. Compared with traditional gas, solid and other lasers, the laser has the advantages of small size, simple structure, long service life, high cost performance and the like, and particularly, the development of a high-power semiconductor laser gradually replaces the traditional laser in many fields. The application provides a semiconductor laser chip, simple structure, the preparation of being convenient for, and have higher COD (catastropic Optical Damage) threshold value.
Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a schematic structural diagram of an embodiment of a semiconductor laser chip provided in the present application, fig. 2 is a schematic top view of the semiconductor laser chip in fig. 1, and fig. 3 is a schematic side cross-sectional view of the semiconductor laser chip in fig. 1. Specifically, the semiconductor laser chip includes: a functional layer 11 and an active layer 12.
Wherein the active layer 12 is located in the functional layer 11, and the functional layer 11 provides electron input to the active layer 12 through an electrode and can limit electrons to a certain area so as to enable the semiconductor laser chip to emit light. The active layer 12 is used to generate sufficient optical gain and emit light, enabling the semiconductor laser chip to output a desired laser emission wavelength.
Alternatively, as shown in fig. 1, the functional layer 11 includes a current injection region and a non-current injection region 16, the non-current injection region 16 is located at an end of the current injection region, the current injection region may be provided with a ridge mesa 13, and the ridge mesa 13 is located at a middle position of the functional layer 11, that is, the non-current injection region 16 is located at two opposite ends of the ridge mesa 13.
As shown in fig. 2, a particle doping region 15 is disposed at an end of the functional layer 11, wherein metal particles are doped in the particle doping region 15 to change a local area and a component of the functional layer, improve a forbidden bandwidth of a local epitaxial material on a light emitting surface, and form a non-absorption window for laser emitted from an interior of the semiconductor laser chip, so as to effectively reduce light absorption, prevent the semiconductor laser chip from optical catastrophic damage too early, and further improve a COD threshold of the semiconductor laser chip.
Optionally, the particle doping region 15 may be disposed at one end of the functional layer 11, and the particle doping regions 15 may also be disposed at two opposite ends of the functional layer 11, so as to form non-absorption windows on both cavity surfaces of the functional layer 11, thereby increasing the COD threshold of the semiconductor laser chip.
The particles may be doped specifically in different layers of the semiconductor laser chip, as long as the particles are not doped in the active layer 12, and the particles may be doped in other layers in the functional layer 11. The metal particles doped in the particle doping region 15 include at least one of magnesium particles, zinc particles, and aluminum particles. For example, the particle doping region 15 at the end of the functional layer 11 is doped with magnesium particles and aluminum particles, or the particle doping region 15 at the end of the functional layer 11 is doped with magnesium particles, zinc particles, and aluminum particles. The setting may be selected according to actual conditions, and is not specifically limited herein. The doped metal particles may be introduced into the end of the functional layer 11 by thermal diffusion or implantation.
Alternatively, the particle source to be diffused may be prepared as a thin film, which covers the particle doping region 15 of the functional layer 11, and the particles in the particle source to be diffused enter the interior of the functional layer 11 through thermal diffusion. However, thermal diffusion is an isotropic diffusion mode, and particles diffuse to the end of the functional layer 11 and also to the side (current injection region). When the doped particles diffuse into the current injection region, the epitaxial composition and the energy band width of the current injection region are changed, which affects the effective injection area of the current and reduces the light emitting efficiency and the electrical performance of the semiconductor laser chip.
In the present application, a trench 14 is provided in the functional layer 11, the trench 14 being located between the particle doping region 15 and the current injection region, wherein the depth of the trench 14 can be selected according to the thickness of the layer to be doped actually.
The trench 14 may be located on the side of the particle doping region 15 close to the ridge mesa 13, i.e. the trench 14 is located between the ridge mesa 13 and the particle doping region 15. By arranging the groove 14, in the process of injecting light emitted by the semiconductor laser chip, the current in the current injection region is not directly diffused to the cavity surface, but is blocked at the groove 14, so that the density of carriers injected to the cavity surface is reduced, non-radiative recombination absorption can be reduced, and the COD threshold current is further improved. In addition, the provision of the trench 14 can effectively prevent contamination of the active region, thereby improving the light emission efficiency of the semiconductor laser chip.
It will be appreciated that the grooves 14 may be provided only at one end of the functional layer 11, and in other embodiments, the grooves 14 may be provided at both opposite ends of the functional layer 11, and the grooves 14 may be provided at both opposite sides of the ridge mesa 13, so that the respective ends of the functional layer 11 have high reliability in particle doping.
In the above embodiment, the semiconductor laser chip has a simple structure, and the trench 14 is provided between the ridge table 13 and the particle doping region 15, so that the current in the current injection region can be prevented from diffusing to the cavity surface, the COD threshold of the semiconductor laser chip can be increased, and other photoelectric performance parameters of the semiconductor laser chip cannot be affected. In addition, the semiconductor laser chip of the embodiment has simple preparation process and stable process, and is suitable for industrial production of the semiconductor laser chip.
Further, as shown in fig. 1, the trench 14 has a length direction a, a width direction B, and a depth direction C, the length of the trench 14 in the a direction is the length of the trench 14, the length of the trench 14 in the B direction is the width of the trench 14, and the length of the trench 14 in the C direction is the depth of the trench 14. The ridge table 13 has a longitudinal direction X, a width direction Y, and a height direction Z. The length of the ridge table 13 in the X direction is the length of the ridge table 13, the length of the ridge table 13 in the Y direction is the width of the ridge table 13, and the length of the ridge table 13 in the Z direction is the height of the ridge table 13.
The length direction a of the trench 14 and the length direction X of the ridge table 13 form a predetermined included angle, for example, the included angle between the length direction a of the trench 14 and the length direction X of the ridge table 13 is 70 degrees, 80 degrees, or 90 degrees. Preferably, the length direction a of the trench 14 is perpendicular to the length direction X of the ridge mesa 13, which can increase the length of the ridge mesa 13, improve the light emitting power and efficiency of the semiconductor laser chip, reduce the length of the trench 14, and simplify the fabrication process of the semiconductor laser chip.
The width of the ridge mesa 13 is less than or equal to the length of the trench 14 so that the trench 14 completely blocks the ridge mesa 13 and the current in the current injection region does not directly diffuse to the facet, thereby increasing the COD threshold of the semiconductor laser chip.
Optionally, the length of the trench 14 ranges from: 70 μm to 120 μm, for example, the length of the trench 14 may be: 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, or 120 μm, and the like.
The width of the trench 14 ranges from: 10 μm to 20 μm, for example, the width of the trench 14 may be 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, or the like.
The depth range of the trench 14 is: 0.3 μm to 0.6 μm, for example, the depth of the trench 14 may be 0.3 μm, 0.4 μm, 0.5 μm, or 0.6 μm.
The length range of the ridge table 13 is: 1100 μm to 1700 μm, for example, the length of the ridge stage 13 may be 1100 μm, 1200 μm, 1300 μm, 1400 μm, 1500 μm, 1600 μm, 1700 μm, or the like.
Width range of ridge stage 13: for example, the width of the ridge table 13 may be 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm, or the like.
The height range of the ridge table 13 is: for example, the height of the ridge table 13 may be 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, or 2 μm, etc.
The cross-sectional shape of the groove 14 in the depth direction C thereof is rectangular, square, trapezoidal, parallelogram, triangular, or the like. Preferably, the cross-sectional shape of the trench 14 in its depth direction C is rectangular in such a way as to facilitate etching of the trench 14.
Further, as shown in fig. 1, the functional layer 11 includes at least a first functional layer 111 and a second functional layer 112. The first functional layer 111, the active layer 12, and the second functional layer 112 are stacked in this order. That is, the active layer 12 is located between the first functional layer 111 and the second functional layer 112.
In this embodiment, particle doping is performed at the end of the first functional layer 111 to form a non-absorption window.
Further, referring to fig. 4, the first functional layer 111 at least includes a first waveguide layer 101, a first confinement layer 102, a transition layer 103, and a contact layer 104, which are sequentially stacked. The first waveguide layer 101 is located on the active layer 12, and any one of the first functional layers 111 can be doped with metal particles to change the local area and the component of each functional layer, improve the forbidden bandwidth of the local epitaxial material of the light-emitting surface, and form a non-absorption window at the cavity surface of the semiconductor laser chip, thereby effectively reducing light absorption and improving the COD threshold of the semiconductor laser chip.
It is understood that the arrangement of the trench 14 may be determined according to the actual layers to be doped, for example, all the layers in the first functional layer 111 are doped with particles, and the difference between the sum of the thicknesses of the layers in the first functional layer 111 and the depth of the trench 14 is smaller than a preset value, so as to prevent the particles at the end of the first functional layer 111 from diffusing into the current injection region.
The second functional layer 112 includes a second waveguide layer 105 and a second confinement layer 106. The second waveguide layer 105 is located on a side of the active layer 12 away from the first functional layer 111, and the second confinement layer 106 is located on a side of the second waveguide layer away from the active layer 12. The second waveguide layer 105 and the second confinement layer 106 are generally not particle doped.
It should be noted that the first waveguide layer 101 and the second waveguide layer 105 are used to transport electrons or holes to the active layer 12, the electrons and the holes meet and pair at the active layer 12, and the bonded electrons and holes release energy and are absorbed by the active layer 12, so that the active layer 12 radiates laser light. The refractive indices of the first confinement layer 102 and the second confinement layer 106 are smaller than the first waveguide layer 101 and the second waveguide layer 105. The laser light radiated from the active layer 12 passes through the first waveguide layer 101 and the second waveguide layer 105, and is totally reflected at interfaces between the first waveguide layer 101 and the second waveguide layer and between the first confinement layer 102 and the second confinement layer 106, so that the optical field of the laser light radiated from the active layer 12 is confined in the active layer 12, the first waveguide layer 101, and the second waveguide layer 105.
Based on the light emitting principle of the semiconductor laser chip, in the application, the groove 14 is formed in the functional layer 11, and in the light emitting current injection process of the semiconductor laser chip, the current in the current injection region is not directly diffused to the cavity surface, but is blocked at the groove 14, so that the density of carriers injected to the cavity surface is reduced, non-radiative recombination absorption can be reduced, and the COD threshold current is further improved.
It is understood that the first functional layer 111 may be an N-type semiconductor layer; correspondingly, the second functional layer 112 is a P-type semiconductor layer. Or the first functional layer 111 is a P-type semiconductor layer; correspondingly, the second functional layer 112 is an N-type semiconductor layer.
Optionally, the first waveguide layer 101 is P-type (Al) with a wavelength of 50-250 nm y Ga 1-y ) x In 1-x P; the first confinement layer 102 is P-type Al x In 1-x P, the thickness is 500-5000 nm; the transition layer 103 is P-type doped (Al) with a thickness of 50-250 nm y Ga 1-y ) x In 1-x P, the contact layer 104 is P-type doped GaAs with a thickness of 100-500 nm. The second confinement layer 106 is N-type undoped Al matched with N-type GaAs x In 1-x P, the thickness is 500-5000 nm; the second waveguide layer 105 is N-type undoped (Al) y Ga 1-y ) x In 1-x P, the thickness is 50-250 nm.
In the above embodiment, the particle doping region 15 is disposed at the end of the functional layer 11, and the trench 14 is disposed between the particle doping region 15 and the current injection region, so that the current in the current injection region is not directly diffused to the cavity surface. The semiconductor laser chip has the advantages of simple structure, higher COD threshold value, simple manufacturing process and high process stability.
Referring to fig. 5, fig. 5 is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor laser chip according to the present application, specifically, the method includes:
s11: and dividing a particle doping area at the end part of the functional layer, and etching a groove on the functional layer, wherein the groove is positioned between the particle doping area and a current injection area of the functional layer.
In this step, as shown in fig. 8, a particle doping region 15 is partitioned at an end portion of the functional layer 11, and a trench 14 is etched at one side of the particle doping region 15, wherein the trench 14 is located between the particle doping region 15 and the current injection region. The grooves 14 can effectively block doped particles from diffusing to the current injection region, prevent pollution to the active region, improve the COD threshold of the semiconductor laser chip, and simultaneously can reduce the requirement of the semiconductor laser chip on a thermal diffusion process, thereby simplifying the preparation process of the semiconductor laser chip.
In a specific embodiment, as shown in fig. 6, the step of etching a trench 14 in the functional layer 11 comprises:
s111: and cleaning the surface of the epitaxially grown semiconductor laser chip.
Before starting a device process, firstly, surface cleaning is carried out on an epitaxially grown semiconductor laser chip, the surface cleaning is mainly divided into organic cleaning and inorganic cleaning, and the semiconductor laser chip is cleaned to provide a foundation for a subsequent process. As shown in fig. 8, the semiconductor laser chip includes a functional layer 11 and an active layer 12 located in the functional layer 11, the active layer 12 is located in the functional layer 11, and for specific description of the active layer 12 and the functional layer 11, please refer to the description of the above embodiments, which is not described herein again.
S112: and photoetching a groove pattern on the functional layer.
Specifically, as shown in fig. 8 and 9, a photoresist 22 may be coated on the functional layer 11, and a region of the trench 14 may be etched through the photoresist 22.
S113: the trench is etched according to the trench pattern.
The trench 14 is etched according to the trench pattern etched by the photoresist 22, and after the trench 14 is etched, the photoresist is removed and cleaned, so as to obtain the trench 14 shown in fig. 8.
Optionally, the length of the trench 14 ranges from: 70 μm to 120 μm, for example, the length of the trench 14 may be 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, or the like.
The width of the trench 14 ranges: 10 μm to 20 μm, for example, the width of the trench 14 may be 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, or the like.
The depth range of the trench 14 is: 0.3 μm to 0.6 μm, for example, the depth of the trench 14 may be 0.3 μm, 0.4 μm, 0.5 μm, or 0.6 μm.
S12: and carrying out particle doping on the particle doping area.
After the trench 14 is formed, the particle doping region 15 is particle doped. Specifically, as shown in fig. 7, the step of particle doping the particle doping region 15 includes:
s121: and forming a doped particle source layer on the particle doping region.
Specifically, as shown in fig. 10, a doped particle source layer 21 is formed on the particle doping region 15 (the end portion of the functional layer 11), and the doped particle source layer 21 is used for providing doped particles for the particle doping region 15, and for the structure of the particle doping region 15, please refer to the description of the above embodiment, which is not repeated herein.
The doped particle source layer 21 is located at an end portion of the functional layer 11. The doped particle source layer 21 is a thin film with doped particles, wherein the doped particles include at least one of magnesium particles, zinc particles, or aluminum particles.
S122: and enabling the particles in the doped particle source layer to enter the particle doping area.
The particles in the doping particle source layer 21 are diffused into the particle doping region 15 to dope the particles in the particle doping region 15. Further, as shown in fig. 11, a silicon dioxide layer 23 may be deposited on the functional layer 11 and the doped particle source layer 21 so that the doped particle source layer 21 can rapidly perform particle diffusion. In another embodiment, the silicon dioxide layer 23 may be deposited only on the doped particle source layer 21 to save the process cost. In other embodiments, the particles in the doped particle source layer 21 may be rapidly diffused into the particle doping region 15 by heating.
S123: and removing the doped particle source layer.
After the particle doping region 15 at the end of the functional layer 11 is doped with particles, high-temperature annealing is performed to remove all the film layers on the functional layer 11, specifically, the silicon dioxide layer 23 and the doped particle source layer 21 on the functional layer 11 may be removed, so as to obtain the semiconductor laser chip as shown in fig. 12.
In this embodiment, by providing the trench 14, in the process of particle doping the particle doping region 15, the lateral diffusion of particles can be reduced, and the light emitting efficiency of the semiconductor laser chip can be improved.
In another embodiment, when manufacturing a semiconductor laser chip, after the step of forming a doped particle source layer on the particle doping region, the method further includes:
s13: a ridge mesa is formed on the functional layer such that the trench is located between the ridge mesa and the particle doping region.
As shown in fig. 13, the ridge mesa 13 is etched in the middle region of the functional layer 13 so that the trench 14 is located between the particle doping region 15 and the ridge mesa 13.
Preferably, the length direction of the trench 14 is perpendicular to the length direction of the ridge mesa 13, which can increase the length of the ridge mesa 13, improve the light-emitting power and efficiency of the semiconductor laser chip, reduce the length of the trench 14, and simplify the fabrication process of the semiconductor laser chip.
The width of the ridge platform 13 is less than or equal to the length of the groove 14 so that the groove 14 can completely block the ridge platform 13 and particles at the end of the functional layer 11 cannot enter the lower portion of the ridge platform 13, thereby increasing the COD threshold of the semiconductor laser chip.
The length range of the ridge table 13 is: 1100 μm to 1700 μm, for example, the length of the ridge stage 13 may be 1100 μm, 1200 μm, 1300 μm, 1400 μm, 1500 μm, 1600 μm, 1700 μm, or the like.
Width of ridge table 13: 50 μm to 100 μm, for example, the width of the ridge stage 13 may be: 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm, or the like.
The height range of the ridge table 13 is: for example, the height of the ridge table 13 may be 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, or 2 μm, etc.
S14: an upper electrode and a lower electrode are formed on opposite sides of the functional layer, respectively.
As shown in fig. 14, an insulating layer 17 is deposited on the functional layer 11, the insulating layer 17 covers the groove 14 and the particle doping region 15, and then an upper electrode 24 and a lower electrode 25 are formed on opposite sides of the functional layer 11, respectively, to complete the fabrication of the semiconductor laser chip. The upper electrode 24 may be a P electrode, the lower electrode 25 may be an N electrode, and in another embodiment, the upper electrode may also be an N electrode, and the lower electrode 25 is a P electrode.
The preparation process of the semiconductor laser chip is simple, the lateral diffusion of particles can be reduced through the grooves 14, and the luminous efficiency of the semiconductor laser chip is improved.
In this application, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless explicitly defined otherwise. In the description of the present application, it is to be understood that the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or unit must have a specific direction, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application.
In the description herein, the description of the terms "one embodiment," "some embodiments," "specific embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A semiconductor laser chip, comprising:
the active layer is positioned in the functional layer, and the functional layer comprises a current injection region and a particle doping region positioned at the end part of the current injection region;
and the functional layer is provided with a groove, and the groove is positioned between the particle doping region and the current injection region.
2. A semiconductor laser chip as claimed in claim 1 wherein the current injection region is provided with a ridge mesa and the trench is located between the ridge mesa and the particle doped region, the length of the trench being perpendicular to the length of the ridge mesa.
3. A semiconductor laser chip as claimed in claim 2 wherein the width of the ridge mesa is less than or equal to the length of the trench.
4. A semiconductor laser chip as claimed in claim 1, wherein the cross-sectional shape of the trench in its depth direction is rectangular, square, trapezoidal, parallelogram, or triangular.
5. The semiconductor laser chip of claim 2,
the length range of the groove is as follows: 70-120 μm, the width of the groove is in the range: 10-20 μm, the depth of the groove is in the range: 0.3-0.6 μm;
the length range of the ridge table is as follows: 1100 μm to 1700 μm, the width of the ridge table ranging from: 50 μm to 100 μm, the height of the ridge-shaped mesa ranging from: 1 μm to 2 μm.
6. A semiconductor laser chip as claimed in claim 2 wherein both ends of the functional layer are provided with the particle doped regions and opposite sides of the ridge mesa are provided with the grooves.
7. A semiconductor laser chip as claimed in claim 1 wherein the particles doped within the particle doping region comprise at least one of magnesium particles, zinc particles, and aluminum particles.
8. A preparation method of a semiconductor laser chip is characterized by comprising the following steps:
dividing a particle doping area at the end part of the functional layer, and etching a groove on the functional layer, wherein the groove is positioned between the particle doping area and a current injection area of the functional layer;
and doping particles in the particle doping region.
9. The method of claim 8, wherein the step of doping the particle doping region with particles further comprises: and forming a ridge platform in the current injection region of the functional layer, so that a groove is positioned between the ridge platform and the particle doping region, and the length direction of the groove is vertical to that of the ridge platform.
10. The method of claim 9, wherein a width of the ridge mesa is less than or equal to a length of the trench.
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Effective date of registration: 20231211 Address after: 518055 room 411-1, Shenzhen integrated circuit design and application Industrial Park, south of chaguang Road, Xili street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: YLX Inc. Address before: 23 / F and 24 / F, joint headquarters building, high tech Zone, 63 Xuefu Road, Nanshan District, Shenzhen, Guangdong 518052 Applicant before: Shenzhen Zhongguang Industrial Technology Research Institute |