CN115513126A - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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Publication number
CN115513126A
CN115513126A CN202110699494.7A CN202110699494A CN115513126A CN 115513126 A CN115513126 A CN 115513126A CN 202110699494 A CN202110699494 A CN 202110699494A CN 115513126 A CN115513126 A CN 115513126A
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layer
forming
semiconductor structure
substrate
top surface
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张田田
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110699494.7A priority Critical patent/CN115513126A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate is provided with a plurality of first device structures and second device structures positioned on the substrate at two sides of the first device structures; forming a first dielectric layer on a substrate, wherein the first dielectric layer is internally provided with a first opening, and the first opening exposes part of the top surface of the first device structure; forming a first connection layer in the first opening; forming a passivation layer on the top surface of the first connecting layer; after a passivation layer is formed, forming a second opening in the first dielectric layer, wherein the second opening exposes a part of the surface of the second device structure; and forming a second connecting layer in the second opening by adopting a selective deposition process, wherein the growth rate of the second connecting layer on the second device structure is greater than that on the passivation layer. The performance of the semiconductor structure formed by the method is improved.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The metal interconnection structure is an indispensable structure in a semiconductor device, and is used for realizing interconnection between an active region and an active region, interconnection between a transistor and a transistor, or interconnection between metal wires of different layers to complete signal transmission and control. Therefore, in a semiconductor manufacturing process, the formation of a metal interconnection structure has a great influence on the performance of a semiconductor device and the manufacturing cost of the semiconductor device. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced, and in order to achieve electrical connection of the respective semiconductor devices, a multi-layer interconnection structure is generally required.
Generally, in a back-end interconnection process in a semiconductor device manufacturing process, a first metal layer (M1) needs to be electrically connected with an underlying active device structure (including a source drain region and a gate structure region). Therefore, before forming the first metal layer, it is generally necessary to form a Local Interconnect structure (Local Interconnect) of the semiconductor device in advance. The local interconnect structure includes: a zero layer metal layer (M0) electrically connected with the source drain region of the lower layer, and a zero layer gate metal layer (M0G) electrically connected with the gate structure.
However, the manufacturing process of the semiconductor structure having the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure is to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a plurality of first device structures and second device structures positioned on the substrate at two sides of the first device structures; forming a first dielectric layer on a substrate, wherein the first dielectric layer is internally provided with a first opening, and the first opening exposes part of the top surface of the first device structure; forming a first connection layer in the first opening; forming a passivation layer on the top surface of the first connection layer; forming a passivation layer, and forming a second opening in the first dielectric layer, wherein the second opening exposes a part of the surface of the second device structure; and forming a second connecting layer in the second opening by adopting a selective deposition process, wherein the growth rate of the second connecting layer on the second device structure is greater than that on the passivation layer.
Optionally, the method for forming the passivation layer on the top surface of the first connection layer includes: and passivating the top surface of the first connecting layer, and forming a passivation layer on the top surface of the first connecting layer, wherein the material of the passivation layer comprises a first connecting layer material containing doped ions.
Optionally, the process of passivating the top surface of the first connection layer includes a plasma treatment process containing dopant ions.
Optionally, the process of passivating the top surface of the first connection layer includes an ion implantation process containing dopant ions.
Optionally, the dopant ions include nitrogen ions.
Optionally, while performing passivation on the top surface of the first connection layer, the method further includes: and passivating the top surface of the first dielectric layer to form a barrier layer on the top surface of the first dielectric layer.
Optionally, the thickness of the passivation layer ranges from 50 angstroms to 100 angstroms.
Optionally, the material of the first connection layer includes a metal, and the metal includes tungsten.
Optionally, the method for forming the second connection layer includes: forming an initial second connection layer in the second opening; and flattening the initial connection layer until the surface of the first dielectric layer is exposed to form the second connection layer.
Optionally, the passivation layer is planarized while the initial connection layer is planarized.
Optionally, the material of the initial second connection layer comprises a metal, and the metal comprises tungsten.
Optionally, the process of forming the initial second connection layer includes a selective deposition process; the temperature range is 300-400 ℃, and the reaction gas is the mixed gas of hydrogen and tungsten hexafluoride.
Optionally, the method for planarizing the initial connection layer and the passivation layer includes: forming a liner layer on the initial connecting layer, the passivation layer and the first dielectric layer; forming a buffer layer on the pad layer; and flattening the buffer layer, the liner layer and the initial connecting layer by adopting a chemical mechanical polishing process until the surface of the first medium layer is exposed.
Optionally, the material of the buffer layer is the same as that of the initial connection layer.
Optionally, the material of the pad layer includes one or both of a metal and a metal compound; the metal comprises titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises: the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a plurality of first device structures and second device structures positioned on the substrate at two sides of the first device structures; a first dielectric layer on the substrate, the first dielectric layer having a first opening and a second opening therein, the first opening exposing a portion of the top surface of the first device structure, the second opening exposing the top surface of the second device structure; a first connection layer located within the first opening; a passivation layer on a top surface of the first connection layer; a second connection layer located within the second opening.
Optionally, the material of the passivation layer includes a first connection layer material containing dopant ions.
Optionally, the dopant ions include nitrogen ions.
Optionally, the method further includes: and the barrier layer is positioned on the top surface of the first dielectric layer, the material of the barrier layer comprises a first dielectric layer material containing doped ions, and the barrier layer is exposed out of the surface of the passivation layer.
Optionally, the first device structure comprises a gate structure; the second device structure includes a conductive structure.
Optionally, the first device structure comprises a gate structure; the second device structure includes a conductive structure.
Optionally, the material of the second device structure comprises a metal, and the metal comprises cobalt.
Optionally, the substrate further includes: source-drain doped regions in the substrate at two sides of the gate structure; the conductive structure is positioned on the source-drain doped region.
Optionally, the substrate includes: the structure comprises a substrate and a fin part structure positioned on the substrate; the grid structure stretches across the fin structure, and the source drain doping area is located in the fin structure on two sides of the grid structure.
Optionally, the first device structure further includes: capacitance, inductance, or resistance; the second device structure further includes: capacitance, inductance, or resistance.
Optionally, the substrate further has a second dielectric layer, and the plurality of first device structures and the plurality of second device structures are located in the second dielectric layer; the first dielectric layer is positioned on the second dielectric layer.
Optionally, the material of the first connection layer includes a metal, and the metal includes tungsten; the material of the second connection layer comprises a metal comprising tungsten.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the forming method of the technical scheme, the passivation layer is formed on the top surface of the first connecting layer, the second connecting layer is formed in the second opening by adopting a selective deposition process, and the growth rate of the second connecting layer on the second device structure is larger than that on the passivation layer. Therefore, the situation that the material of the second connecting layer can grow on the first connecting layer in a large amount is reduced, and the first connecting layer and the second connecting layer which are compact in structure can be obtained when planarization is subsequently carried out, so that the performance of the semiconductor structure is improved.
Further, the process for passivating the top surface of the first connecting layer comprises a treatment process of a gas containing doped ions or an ion implantation process of the gas containing doped ions; the material of the passivation layer comprises a first connection layer material containing dopant ions. The passivation layer can be removed in the subsequent planarization process, thereby simplifying the process flow.
Drawings
FIGS. 1 and 2 are schematic structural diagrams illustrating a semiconductor structure formation process in one embodiment;
FIGS. 3 to 8 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a semiconductor structure formation process in another embodiment of the present invention.
Detailed Description
As described in the background, the manufacturing process of the semiconductor structure having the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure is to be further improved. The analysis will now be described with reference to specific examples.
Fig. 1 and 2 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment.
Referring to fig. 1, a substrate 100 is provided; forming a gate structure 101 and source-drain doped regions 102 in the substrate on two sides of the gate structure 101 on the substrate 100; forming a first dielectric layer 103 on the substrate 100 and the gate structure 101; forming a source drain plug 104 in the first dielectric layer 103, wherein the source drain plug 104 is electrically connected with the source drain doped region 102; forming a second dielectric layer 105 on the first dielectric layer 103; forming a gate plug 106 in the second dielectric layer 105, wherein the gate plug 106 is located on the gate structure 101; after forming the gate plug 106, an opening 107 is formed in the second dielectric layer 105, wherein the opening 107 exposes a portion of the top surface of the source/drain plug 104.
Referring to fig. 2, a conductive layer 108 is formed in the opening 107.
During the formation of the semiconductor structure, the gate plug 106 and the conductive layer 108 are made of tungsten. Since the film structure of the gate structure 101 is complex and the process is complex when the opening of the gate plug 106 is formed by etching, the conductive layer 108 is formed after the gate plug 106 is formed. The process for forming the conductive layer 108 is a selective deposition process, and the conductive layer 108 formed by the selective deposition process has a compact structure and a low resistance.
However, during the selective deposition process, the material forming the conductive layer 108 may also grow on the gate plug 106, forming a top cap layer 109 on the gate plug 106. After a pad layer (not shown) and a buffer layer (not shown) are formed on the second dielectric layer 105, in the process of planarizing the top cap layer 109 and the conductive layer 108, large particles may be formed due to the large volume of the top cap layer 109, which may scratch the surface of the substrate, and affect the performance of the substrate.
In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, in which a passivation layer is formed on a top surface of a first connection layer, and a second connection layer is subsequently formed in a second opening by using a selective deposition process, where a growth rate of the second connection layer on a second device structure is greater than a growth rate on the passivation layer. Therefore, the situation that the material of the second connecting layer can also grow on the first connecting layer is reduced, and the first connecting layer and the second connecting layer which are compact in structure can be obtained when the planarization is subsequently carried out, so that the performance of the semiconductor structure is favorably improved.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 3 to 8 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, wherein the substrate 200 has a plurality of first device structures 201 and second device structures 202 located on the substrate 200 at two sides of the first device structures 201.
In the present embodiment, the first device structure 201 includes a gate structure; the second device structure 202 includes a conductive structure.
In this embodiment, the substrate 200 further includes: source-drain doped regions 203 positioned in the substrate 200 at two sides of the gate structure; the conductive structure is located on the source-drain doped region 203.
The material of the conductive structure comprises a metal comprising cobalt.
The substrate 200 further has a second dielectric layer 204 thereon, and the plurality of first device structures 201 and the plurality of second device structures 202 are located in the second dielectric layer 204.
In the present embodiment, the substrate 200 is a planar substrate. The material of the substrate 200 comprises silicon.
The material of the second dielectric layer 204 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second dielectric layer 204 includes silicon oxide.
In other embodiments, the substrate comprises: the structure comprises a substrate and a fin part structure positioned on the substrate; the grid structure stretches across the fin part structure, and the source drain doping area is located in the fin part structures on two sides of the grid structure.
In other embodiments, the first device structure further comprises: capacitance, inductance, or resistance; the second device structure further includes: capacitance, inductance, or resistance.
Referring to fig. 4, a first dielectric layer 205 is formed on the substrate 200, and the first dielectric layer 205 has a first opening (not shown) therein, wherein the first opening exposes a portion of the top surface of the first device structure 201.
The material of the first dielectric layer 205 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first dielectric layer 205 includes silicon oxide.
The method for forming the first dielectric layer 205 and the first opening includes: forming an initial first dielectric layer (not shown) on the substrate 200; forming a patterning layer (not shown) on the initial first dielectric layer; and etching the initial first dielectric layer by using the patterning layer as a mask until the top surface of the first device structure 201 is exposed, thereby forming a first dielectric layer 205 and a first opening in the first dielectric layer 205.
With continued reference to fig. 4, a first connection layer 206 is formed within the first opening.
The material of the first connection layer 206 comprises a metal, which comprises tungsten.
The method of forming the first connection layer 206 includes: forming a first connection material layer (not shown) in the first opening; and flattening the first connecting material layer until the surface of the first dielectric layer 205 is exposed to form the first connecting layer 206.
The process of forming the first connection material layer includes a selective deposition process or a chemical vapor deposition process.
Referring to fig. 5, a passivation layer 207 is formed on the top surface of the first connection layer 206.
The method of forming the passivation layer 207 on the top surface of the first connection layer 206 includes: and passivating the top surface of the first connection layer 206 to form a passivation layer 207 on the top surface of the first connection layer 206, wherein the material of the passivation layer 207 comprises the material of the first connection layer 206 containing the doping ions.
The material of the passivation layer 207 includes the material of the first connection layer 206 containing dopant ions. The passivation layer 207 can thus be removed during subsequent planarization, thereby simplifying the process flow.
In this embodiment, the passivation process for the top surface of the first connection layer 206 includes a plasma treatment process containing dopant ions.
In other embodiments, the process of passivating the top surface of the first connection layer includes an ion implantation process including dopant ions.
The doping ions comprise nitrogen ions. The nitrogen ions can inhibit the growth of the material of the subsequently formed second connection layer on the top surface of the first connection layer 206.
The passivation layer 207 has a thickness ranging from 50 angstroms to 100 angstroms. If the thickness of the passivation layer 207 is too thin, i.e., less than 50 angstroms, the passivation layer 207 is easily damaged in the subsequent processes and then loses the protection effect on the first connection layer 206; if the thickness of the passivation layer 207 is too thick, i.e. greater than 100 angstroms, the height dimension of the first connection layer 206 is affected, and the passivation layer 207 is difficult to be removed cleanly during the planarization process, which affects the performance of the semiconductor structure.
While the passivation process is performed on the top surface of the first connection layer 206, the method further includes: the top surface of the first dielectric layer 205 is passivated to form a barrier layer 208 on the top surface of the first dielectric layer 205.
If the barrier layer 208 is not on the surface of the first dielectric layer 205, when a second connection layer is formed in the second opening subsequently, the process for forming the second connection layer is long due to the large aspect ratio of the second opening, the process for forming the second connection layer can modify and consume the surface of the first dielectric layer 205 to a certain extent, and nucleation is performed on the surface of the first dielectric layer 205, so that the second connection layer can grow on the surface of the first dielectric layer 205, which may affect the insulating property of the first dielectric layer 205, and further affect the performance of the semiconductor structure.
The top surface of the first dielectric layer 205 contains nitrogen ions, so that the barrier layer 208 can protect the surface of the first dielectric layer 205, and the nitrogen-containing surface can inhibit the second connecting layer which has a long-term forming process from growing on the surface of the first dielectric layer 205 on the top surface of the second opening, so as to close the opening and influence the quality of the second connecting layer.
Referring to fig. 6, after forming the passivation layer 207, a second opening 209 is formed in the first dielectric layer 205, wherein the second opening 209 exposes a portion of the surface of the second device structure 202.
The method of forming the second opening 209 includes: forming a patterned layer (not shown) on the first dielectric layer 205; and etching the first dielectric layer 205 by using the patterning layer as a mask until the surface of the second device structure 202 is exposed, so as to form the second opening 209.
The process for etching the first dielectric layer 205 includes a dry etching process, and the gas of the dry etching process includes a fluorine-containing gas.
Next, a second connection layer 211 is formed in the second opening. Please refer to fig. 7 and fig. 8 for a process of forming the second connection layer 211.
Referring to fig. 7, an initial second connection layer 210 is formed in the second opening 209 by using a selective deposition process, wherein the growth rate of the initial second connection layer 210 on the second device structure 202 is greater than that on the passivation layer 207.
The growth rate of the initial second connection layer 210 on the second device structure 202 is greater than the growth rate on the passivation layer 207. Therefore, the situation that the material of the second connection layer can also grow on the first connection layer 206 in a large amount is reduced, and the first connection layer 206 and the second connection layer with compact structures can be obtained when planarization is subsequently performed, so that the performance of the semiconductor structure can be improved.
The material of the initial second connection layer 210 comprises a metal comprising tungsten.
The process of forming the initial second connection layer 210 includes a selective deposition process; the parameters of the selective deposition process include: the temperature range is 300-400 ℃, and the reaction gas is the mixed gas of hydrogen and tungsten hexafluoride. Because the passivation layer 207 is formed on the top surface of the first connection layer 206 and the barrier layer 208 is formed on the top surface of the first dielectric layer 205, the material of the first connection layer 206 is difficult to grow on the surfaces of the first connection layer 206 and the first dielectric layer 205, and thus the performance of the semiconductor structure is improved.
Referring to fig. 8, the initial connection layer 210 is planarized until the surface of the barrier layer 208 is exposed, and the second connection layer 211 is formed.
The method of planarizing the initial connection layer 210 includes: forming a liner layer (not shown) on the initial connection layer 210, the passivation layer 207 and the barrier layer 208; forming a buffer layer (not shown) on the pad layer; and planarizing the buffer layer, the liner layer and the initial connection layer 210 by adopting a chemical mechanical polishing process until the surface of the barrier layer 208 is exposed, so as to form the second connection layer 211.
The buffer layer and the initial connection layer 210 are the same material.
The material of the buffer layer and the initial connection layer 210 includes a metal including tungsten.
The material of the pad layer includes one or both of a metal and a metal compound; the metal comprises titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 8, including:
the device comprises a substrate 200, wherein the substrate 200 is provided with a plurality of first device structures 201 and second device structures 202 positioned on the substrate at two sides of the first device structures 201;
a first dielectric layer 205 on the substrate 200, the first dielectric layer 205 having a first opening and a second opening therein, the first opening exposing a portion of the top surface of the first device structure 201, the second opening exposing the top surface of the second device structure;
a first connection layer 206 located within the first opening;
a passivation layer 207 on the top surface of the first connection layer 206;
and a second connection layer 211 positioned within the second opening.
In this embodiment, the material of the passivation layer 207 includes the material of the first connection layer 206 containing dopant ions.
In this embodiment, the dopant ions include nitrogen ions.
In this embodiment, the method further includes: and the barrier layer 208 is positioned on the top surface of the first dielectric layer 205, the material of the barrier layer 208 comprises a first dielectric layer material containing doped ions, and the barrier layer 208 exposes the surface of the passivation layer 207.
In the present embodiment, the first device structure 201 includes a gate structure; the second device structure 202 includes a conductive structure.
In this embodiment, the material of the second device structure 202 includes a metal including cobalt.
In this embodiment, the substrate 200 further includes: source and drain doped regions in the substrate at both sides of the gate structure; the conductive structure is positioned on the source-drain doped region.
In this embodiment, the substrate includes: the fin structure comprises a substrate and a fin structure positioned on the substrate; the grid structure stretches across the fin structure, and the source drain doping area is located in the fin structure on two sides of the grid structure.
In this embodiment, the first device structure 201 further includes: capacitance, inductance, or resistance; the second device structure 202 further includes: capacitance, inductance, or resistance.
In this embodiment, the substrate further has a second dielectric layer 204, and the plurality of first device structures 201 and the plurality of second device structures 202 are located in the second dielectric layer 204; the first dielectric layer 205 is located on the second dielectric layer 204.
In this embodiment, the material of the first connection layer 206 includes a metal, which includes tungsten; the material of the second connection layer 211 includes a metal including tungsten.
FIG. 9 is a schematic diagram of a semiconductor structure formation process in another embodiment of the present invention.
Referring to fig. 9, fig. 9 is a schematic view based on fig. 7, in which the initial connection layer 210 and the passivation layer 207 are planarized until the surface of the first dielectric layer 205 is exposed, and the second connection layer 311 is formed.
In this embodiment, the barrier layer 208 is removed while the initial connection layer 210 and the passivation layer 207 are planarized.
The method for planarizing the initial connection layer 210 and the passivation layer 207 includes: forming a liner layer (not shown) on the initial connection layer 210, the passivation layer 207 and the barrier layer 208; forming a buffer layer (not shown) on the pad layer; and planarizing the buffer layer, the liner layer, the initial connection layer 210, the passivation layer 207 and the barrier layer 208 by adopting a chemical mechanical polishing process until the surface of the first dielectric layer 205 is exposed, so as to form the second connection layer 311.
The buffer layer and the initial connection layer 210 are the same material.
The material of the buffer layer and the initial connection layer 210 includes a metal including tungsten.
The material of the liner layer includes one or both of a metal and a metal compound; the metal comprises titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.
The material of the passivation layer 207 comprises the material of the first connection layer 206 containing the dopant ions, on the one hand, no additional passivation layer has to be formed, and on the other hand, the passivation layer can be removed during the planarization process, thereby simplifying the process flow.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (26)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of first device structures and second device structures positioned on the substrate at two sides of the first device structures;
forming a first dielectric layer on a substrate, wherein the first dielectric layer is provided with a first opening, and the first opening exposes part of the top surface of the first device structure;
forming a first connection layer in the first opening;
forming a passivation layer on the top surface of the first connection layer;
forming a passivation layer, and forming a second opening in the first dielectric layer, wherein the second opening exposes a part of the surface of the second device structure;
and forming a second connecting layer in the second opening by adopting a selective deposition process, wherein the growth rate of the second connecting layer on the second device structure is greater than that on the passivation layer.
2. The method of forming a semiconductor structure of claim 1, wherein the forming a passivation layer on the top surface of the first interconnect layer comprises: and passivating the top surface of the first connecting layer, and forming a passivation layer on the top surface of the first connecting layer, wherein the material of the passivation layer comprises a first connecting layer material containing doping ions.
3. The method of claim 2, wherein the process of passivating the top surface of the first interconnect layer comprises a plasma treatment process including dopant ions.
4. The method of claim 2, wherein the process of passivating the top surface of the first interconnect layer comprises an ion implantation process including dopant ions.
5. The method of forming a semiconductor structure of claim 2, wherein the dopant ions comprise nitrogen ions.
6. The method of forming a semiconductor structure of claim 2, wherein passivating the top surface of the first connection layer further comprises: and passivating the top surface of the first dielectric layer to form a barrier layer on the top surface of the first dielectric layer.
7. The method of forming a semiconductor structure of claim 1, wherein the passivation layer has a thickness in a range of: 50 to 100 angstroms.
8. The method of forming a semiconductor structure of claim 1, wherein a material of the first connection layer comprises a metal comprising tungsten.
9. The method of forming a semiconductor structure of claim 1, wherein the method of forming the second connection layer comprises: forming an initial second connection layer in the second opening; and flattening the initial connection layer until the surface of the first dielectric layer is exposed to form the second connection layer.
10. The method of forming a semiconductor structure of claim 9, wherein the passivation layer is planarized while the initial connection layer is planarized.
11. The method of forming a semiconductor structure of claim 9, wherein a material of the initial second connection layer comprises a metal comprising tungsten.
12. The method of forming a semiconductor structure of claim 11, wherein the process of forming the initial second connection layer comprises a selective deposition process; the parameters of the selective deposition process include: the temperature range is 300-400 ℃, and the reaction gas is the mixed gas of hydrogen and tungsten hexafluoride.
13. The method of forming a semiconductor structure of claim 9, wherein planarizing the initial connection layer and passivation layer comprises: forming a liner layer on the initial connecting layer, the passivation layer and the first dielectric layer; forming a buffer layer on the pad layer; and flattening the buffer layer, the liner layer and the initial connecting layer by adopting a chemical mechanical polishing process until the surface of the first medium layer is exposed.
14. The method of forming a semiconductor structure of claim 13, wherein a material of the buffer layer and a material of the initial connection layer are the same.
15. The method of forming a semiconductor structure of claim 13, wherein a material of the liner layer comprises one or both of a metal and a metal compound; the metal comprises titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.
16. A semiconductor structure, comprising:
the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a plurality of first device structures and second device structures positioned on the substrate on two sides of the first device structures;
a first dielectric layer on the substrate, the first dielectric layer having a first opening and a second opening therein, the first opening exposing a portion of the top surface of the first device structure, the second opening exposing the top surface of the second device structure;
a first connection layer located within the first opening;
a passivation layer on a top surface of the first connection layer;
a second connection layer located within the second opening.
17. The semiconductor structure of claim 16, wherein the material of the passivation layer comprises a first tie layer material containing dopant ions.
18. The semiconductor structure of claim 17, in which the dopant ions comprise nitrogen ions.
19. The semiconductor structure of claim 16, further comprising: and the barrier layer is positioned on the top surface of the first dielectric layer, the material of the barrier layer comprises a first dielectric layer material containing doped ions, and the barrier layer is exposed out of the surface of the passivation layer.
20. The semiconductor structure of claim 16, wherein the first device structure comprises a gate structure; the second device structure includes a conductive structure.
21. The semiconductor structure of claim 20, in which a material of the second device structure comprises a metal comprising cobalt.
22. The semiconductor structure of claim 20, wherein the substrate further comprises: source and drain doped regions in the substrate at both sides of the gate structure; the conductive structure is positioned on the source-drain doped region.
23. The semiconductor structure of claim 22, wherein the substrate comprises: the structure comprises a substrate and a fin part structure positioned on the substrate; the grid structure stretches across the fin structure, and the source drain doping area is located in the fin structure on two sides of the grid structure.
24. The semiconductor structure of claim 23, wherein the first device structure further comprises: capacitance, inductance, or resistance; the second device structure further includes: capacitance, inductance, or resistance.
25. The semiconductor structure of claim 16, further comprising a second dielectric layer on said substrate, wherein a plurality of said first device structures and said second device structures are located within said second dielectric layer; the first dielectric layer is located on the second dielectric layer.
26. The semiconductor structure of claim 16, wherein a material of the first connection layer comprises a metal comprising tungsten; the material of the second connection layer comprises a metal comprising tungsten.
CN202110699494.7A 2021-06-23 2021-06-23 Semiconductor structure and method for forming semiconductor structure Pending CN115513126A (en)

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