CN115513123A - Silicon-on-insulator structure and forming method thereof - Google Patents

Silicon-on-insulator structure and forming method thereof Download PDF

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CN115513123A
CN115513123A CN202211374642.9A CN202211374642A CN115513123A CN 115513123 A CN115513123 A CN 115513123A CN 202211374642 A CN202211374642 A CN 202211374642A CN 115513123 A CN115513123 A CN 115513123A
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layer
substrate
device layer
silicon
insulating layer
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魏星
汪子文
戴荣旺
陈猛
徐洪涛
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Shanghai Institute of Microsystem and Information Technology of CAS
Zing Semiconductor Corp
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Shanghai Institute of Microsystem and Information Technology of CAS
Zing Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

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Abstract

The invention provides a silicon-on-insulator structure and a forming method thereof, wherein the forming method of the silicon-on-insulator structure increases the normal-temperature bonding strength during the bonding process through activation treatment, and reduces the temperature required by the subsequent reinforcement process, thereby reducing the thermal diffusion of heterogeneous components in an etch stop layer, ensuring the clear interface between the etch stop layer and a device layer, and further avoiding the thickness uniformity deterioration of the device layer after the etch stop layer is subsequently removed; the uniformity of the device layer after corrosion is controlled by two selective corrosion processes, so that the thickness uniformity of the finally obtained device layer with the silicon-on-insulator structure is less than 10%; the surface of the device layer is free from high-frequency corrosion fluctuation porous morphology through the formation and the removal of the sacrificial oxide layer.

Description

Silicon-on-insulator structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly to a silicon-on-insulator structure and a method for forming the same.
Background
With the continuous development of integrated circuits and the continuous reduction of feature sizes of electronic components, finFET technology and SOI (Silicon-On-Insulator) technology, which are developed as opportunities, become two mainstream routes at present. The demand for SOI structures is increasing with the continuous development of SOI technology. Generally, the SOI structure is composed of a support substrate, an insulating layer and a device layer, and the methods for manufacturing the SOI structure mainly include BESOI (bonding and back etching), SIMOX (separation by implantation of oxygen), and Smartcut TM . The BESOI removes the etching stop layer on the device layer through different etching selection ratios of the etching stop layer and the device layer to etching solutions in an etching manner, so that the thickness uniformity of the device layer can be effectively improved.
At present, the etch stop layer is mainly formed by heavily doped silicon or silicon-germanium alloy such as boron, carbon, nitrogen, etc., wherein HF and HNO are required to be used when the silicon-germanium alloy is used as the etch stop layer 3 And Hac, which forms a porous layer of several tens of nanometers on the surface of the device layer, and needs to be effectively removed in order not to affect the relevant performance of the subsequent device. This porous layer can typically be removed by a chemical mechanical polishing process, but the chemical mechanical polishing process makes the thickness uniformity of the device layer less controllable; can also be prepared by HF and HNO 3 The mixed solution is used for removing the micro-area, but the surface state of the micro-area of the device layer after the removing process still cannot meet the requirements of the subsequent process.
Disclosure of Invention
The invention aims to provide a silicon-on-insulator structure and a forming method thereof, which can effectively repair a porous layer caused by removing an etching stop layer and improve the thickness uniformity of the surface of a device layer.
In order to solve the above problems, there is provided a method of forming a silicon-on-insulator structure, comprising the steps of:
step S1: providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface;
step S2: performing activation treatment on the second front surface and the surface of the device layer, and bonding the first substrate and the second substrate, wherein the second front surface faces the device layer;
and step S3: thinning the first substrate from the first back surface, and removing the rest first substrate and the etch stop layer in sequence through two selective etching processes, so that the surface of the device layer is provided with a porous layer; and
and step S4: and generating a sacrificial oxide layer on the device layer, filling and covering the porous layer with the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure.
Optionally, step S1 includes:
providing a first substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged;
forming an etch stop layer on the first front side;
forming a device layer on the etch stop layer;
providing a second substrate, wherein a polycrystalline silicon capturing layer is formed on the surface of the second substrate, and the surface of the polycrystalline silicon capturing layer is the second front surface;
forming an insulating layer through an oxidation process; and
the insulating layer is located on the surface of the device layer, or the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is located on the surface of the device layer, and the second insulating layer is located on the second front surface.
Further, step S2 includes:
when the insulating layer is positioned on the surface of the device layer, the second front surface and the surface of the insulating layer are subjected to oxygen plasma activation treatment; and
the second front face faces the surface of the insulating layer, and low-temperature reinforcement treatment is performed.
Further, step S2 includes:
when the first insulating layer is positioned on the surface of the device layer and the second insulating layer is positioned on the second front surface, the surface of the first insulating layer and the surface of the second insulating layer are activated and treated by oxygen plasma; and
and the surface of the first insulating layer faces to the surface of the second insulating layer, and low-temperature reinforcement treatment is performed.
Furthermore, the temperature of the strengthening treatment is 300-500 ℃, and the treatment time is not more than 4 hours.
Optionally, step S3 includes:
thinning the first substrate from the first backside using mechanical grinding;
selectively etching the rest of the first substrate for the first time by a first etchant, and etching and stopping at the etch stop layer;
and selectively etching the etching stop layer for the second time by a second etchant, and etching and stopping on the surface of the device layer, so that the surface of the device layer is provided with a porous layer.
Further, the first corrosive agent is TMAH, the concentration of the first corrosive agent is not higher than 25%, and the corrosion temperature is 55-70 ℃.
Further, the second etchant is HF, HNO 3 And Hac, or HF, H 2 O 2 And Hac.
Optionally, step S4 includes:
carrying out oxidation treatment on the surface of the device layer under the atmosphere of dry oxygen, wet oxygen or combination of dry oxygen and wet oxygen to generate a sacrificial oxide layer on the device layer, wherein the sacrificial oxide layer fills and covers the porous layer;
removing the sacrificial oxide layer and the porous layer by a wet etching process to obtain a silicon-on-insulator structure; and
and carrying out roughness optimization treatment on the surface of the device layer through heat treatment.
Further, the wet etching process uses an HF solution, and the concentration of the HF solution is less than 20%.
In another aspect, the invention further provides a silicon-on-insulator structure prepared by the method for forming the silicon-on-insulator structure.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a silicon-on-insulator structure and a forming method thereof, wherein the forming method of the silicon-on-insulator structure comprises the following steps: step S1: providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface; step S2: performing activation treatment on the second front surface and the surface of the device layer, and bonding the first substrate and the second substrate, wherein the second front surface faces the device layer; and step S3: thinning the first substrate from the first back surface, and sequentially removing the remaining first substrate and the etching stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and step S4: and generating a sacrificial oxide layer on the device layer, filling and covering the porous layer with the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure. According to the invention, the normal-temperature bonding strength in the bonding process is increased through the activation treatment, and the temperature required by the bonding process is reduced, so that the thermal diffusion of heterogeneous components (germanium) in the corrosion stop layer is reduced, the interface between the corrosion stop layer and the device layer is ensured to be clear, and the thickness uniformity deterioration of the device layer after the subsequent removal of the corrosion stop layer is avoided; the uniformity of the device layer after corrosion is controlled by two selective corrosion processes, so that the thickness uniformity of the finally obtained device layer with the silicon-on-insulator structure is less than 10%; the formation and removal of the sacrificial oxide layer also results in the absence of a porous layer of high frequency corrosion undulations on the surface of the device layer.
Drawings
FIG. 1 is a flow chart illustrating a method for forming a silicon-on-insulator structure according to an embodiment of the present invention;
FIGS. 2-8 are schematic structural diagrams of a silicon-on-insulator structure provided in accordance with an embodiment of the present invention during formation;
FIG. 9 is an AFM schematic of a device layer surface of a silicon-on-insulator structure;
fig. 10 is an AFM illustration of a device layer surface of a silicon-on-insulator structure provided by an embodiment of the present invention.
Description of reference numerals:
100-a first substrate; 100 a-a first front side; 100 b-a first back side; 110-an etch stop layer; 120-a device layer; 121-a porous layer; 130-an insulating layer; 140-sacrificial oxide layer;
200-a second substrate; 200 a-a second front face; 210-polysilicon trapping layer.
Detailed Description
A silicon-on-insulator structure and method of forming the same of the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the appended drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art can modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 1 is a flow chart illustrating a method for forming a silicon-on-insulator structure according to this embodiment. As shown in fig. 1, the present embodiment provides a method for forming a silicon-on-insulator structure, which includes the following steps:
step S1: providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface;
step S2: performing activation treatment on the second front surface and the surface of the device layer, and bonding the first substrate and the second substrate, wherein the second front surface faces the device layer;
and step S3: thinning the first substrate from the first back surface, and sequentially removing the remaining first substrate and the etching stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and
and step S4: and generating a sacrificial oxide layer on the device layer, filling and covering the porous layer with the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure.
A method for forming a silicon-on-insulator structure according to this embodiment will be described in detail with reference to fig. 2 to 10.
As shown in fig. 2 and 3, step S1 is first performed to provide a first substrate 100 having a first front surface 100a and a first back surface 100b oppositely disposed, an etch stop layer 110 and a device layer 120 being sequentially formed on the first front surface 100a, and a second substrate 200 having a second front surface 200a.
The method specifically comprises the following steps:
as shown in fig. 2, first, a first substrate 100 is provided, and the first substrate 100 may be a single crystal silicon substrate, a silicon germanium substrate, a silicon carbide substrate, and various III-V semiconductor substrates. The first substrate 100 has a first front surface 100a and a first back surface 100b disposed opposite to each other. In this embodiment, the first substrate 100 may be a p-type silicon substrate, and the resistivity of the first substrate 100 is greater than 5 Ω · cm, and preferably, the resistivity of the first substrate 100 is greater than 10 Ω · cm.
Next, an etch stop layer 110 is formed on the first front surface 100 a. The etch stop layer 110 may be a germanium-silicon alloy, and preferably, the etch stop layer 110 has a germanium content of 0.1 to 0.5 and a silicon content of 0.2 to 0.3. The etch stop layer 110 has a thickness of 10nm to 60nm.
In this step, the temperature required for forming the etch stop layer 110 is lower than 800 ℃, and the whole process for forming the etch stop layer 110 is reduced pressure epitaxy, and the epitaxial precursors of silicon and germanium are DCS and GeH, respectively 4 。
Next, a device layer 120 is formed on the etch stop layer 110. The device layer 120 is made of a silicon material, the device layer 120 is doped with p-type ions or n-type ions, and the type and concentration of the doped ions in the device layer 120 depend on the specific requirements of the subsequently formed silicon-on-insulator structure. In order to ensure thickness uniformity of the silicon-on-insulator structure, the device layer 120 has a thickness not higher than 600nm.
In this step, the temperature required for forming the device layer 120 is lower than 800 ℃, and the whole process for forming the device layer 120 is decompression epitaxy, and the epitaxy precursor of the device layer 120 is DCS.
As shown in fig. 3, a second substrate 200 is provided, wherein the second substrate 200 serves as a support substrate of a subsequently formed silicon-on-insulator structure, and mainly serves as a support, and the second substrate 200 may be a single crystal silicon substrate, a silicon germanium substrate, a silicon carbide substrate, various III-V semiconductor substrates, a silicon substrate deposited with a polycrystalline trapping layer, a sapphire substrate, a quartz substrate, a glass substrate, or the like.
In this embodiment, the shape of the first substrate 100 is the same as the shape of the second substrate 200, and the size of the first substrate 100 is the same as the size of the second substrate 200. The second substrate 200 is a high resistivity silicon substrate having a polysilicon trapping layer 210 formed thereon, and the second substrate 200 has a resistivity greater than 1000 ohm-cm. The surface of the polysilicon trapping layer 210 is the second front surface 200a.
Next, an insulating layer 130 is formed by an oxidation process.
As shown in fig. 2, in this embodiment, the insulating layer 130 may be located on the surface of the device layer 120 and used as a final insulating layer of the soi structure, where the surface of the polysilicon trapping layer 210 (i.e., the second front surface 200 a) is a bonding surface on the second substrate side during bonding, and the surface of the insulating layer 130 is a bonding surface on the first substrate side during bonding.
In other embodiments, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is formed on the surface of the device layer, the second insulating layer is formed on the second front surface 200a, and the first insulating layer and the second insulating layer together serve as a final insulating layer of the silicon-on-insulator structure, where the surface of the first insulating layer is a bonding surface on the first substrate side during bonding; the surface of the second insulating layer is a bonding surface on the side of the second substrate when bonding.
In order to prevent thermal diffusion of dopant ions in the device layer 120 and/or the second substrate 200, the oxidation process has an oxidation temperature of not higher than 850 ℃, preferably not higher than 800 ℃, and the oxidation time depends on the thickness requirement of the insulating layer 130.
As shown in fig. 4, next, step S2 is performed, the second front surface 200a and the surface of the device layer 120 are subjected to activation treatment, and the first substrate 100 and the second substrate 200 are bonded, with the second front surface 200a facing the device layer 120.
First, in the present embodiment, since the insulating layer 130 is located on the surface of the device layer 120, the surface of the polysilicon trapping layer (i.e., the second front surface 200 a) and the surface of the insulating layer 130 are activated by oxygen plasma to increase the bonding strength at normal temperature.
In other embodiments, since the first and second insulating layers of the insulating layer are respectively located on the surface of the device layer and the second front surface 200a, the surface of the first insulating layer and the surface of the second insulating layer are activated using oxygen plasma to increase the room-temperature bonding strength.
Next, in this embodiment, the second front surface 200a faces the surface of the insulating layer 130, and the insulating layer 130 is bonded as an intermediate layer, and a low-temperature reinforcement treatment is performed, where the temperature of the low-temperature reinforcement treatment is not higher than 700 ℃, preferably 300 to 500 ℃, and the treatment time is not higher than 4 hours.
Since the second front surface 200a and the surface of the device layer 120 are subjected to activation treatment, the temperature during the reinforcement treatment in this step is low, thermal diffusion of heterogeneous component (germanium) in the etch stop layer 110 is reduced, and a clear interface between the etch stop layer 110 and the device layer 120 is ensured, thereby preventing the thickness uniformity of the device layer 120 from deteriorating after the etch stop layer 110 is subsequently removed from the device layer 120.
In other embodiments, the surface of the first insulating layer faces the surface of the second insulating layer, and the first insulating layer and the second insulating layer are bonded together as an intermediate layer, and low-temperature reinforcement treatment is performed. The temperature of the low-temperature reinforcement treatment is not higher than 700 ℃, preferably 300-500 ℃, and the treatment time is not higher than 4 hours.
Because the surface of the first insulating layer and the surface of the second insulating layer are subjected to activation treatment, the temperature during the reinforcement treatment in the step is lower, the thermal diffusion of heterogeneous components (germanium) in the etch stop layer 110 is reduced, and the interface between the etch stop layer 110 and the device layer 120 is ensured to be clear, so that the thickness uniformity deterioration of the device layer 120 after the subsequent removal of the etch stop layer 110 from the device layer 120 is avoided.
As shown in fig. 5 and fig. 6, step S3 is performed next, the first substrate 100 is thinned from the first back surface 100b, the remaining first substrate 100 and the etch stop layer 110 are sequentially removed by two selective etching processes, and etching is stopped on the surface of the device layer 120, so that the surface of the device layer 120 has a porous layer 121, and the uniformity of the device layer 120 after etching is controlled by two selective etching processes, so that the thickness uniformity of the finally obtained silicon-on-insulator thin film is less than 10%.
The method specifically comprises the following steps:
as shown in fig. 5, first, the first substrate 100 is thinned from the first back surface 100b by using mechanical grinding, for example, chemical mechanical grinding, wherein the thickness of the thinned first substrate 100 is controlled within 2 μm, and the thickness difference of the thinned first substrate 100 is less than 0.5 μm, that is, the thickness of the thinned first substrate 100 is 1.5 μm to 2 μm.
Then, the remaining first substrate 100 is selectively etched for the first time, and the etching is stopped on the surface of the etch stop layer 110. In detail, the remaining first substrate 100 is selectively etched for the first time by a first stress-sensitive etchant, and etching stops on the surface of the etch stop layer 110.
In this step, the first etchant may be TMAH (tetramethylammonium hydroxide), the concentration of the first etchant is not higher than 25%, and the etching temperature is 50 to 90 ℃, preferably, the etching temperature is 55 to 70 ℃.
As shown in fig. 6, the etch stop layer 110 is then selectively etched a second time, stopping at the surface of the device layer 120. In detail, the etch stop layer 110 is selectively etched a second time by a second etchant having a high etch selectivity and etch-stops on the surface of the device layer 120, so that the surface of the device layer 120 has a porous layer 121.
In this step, the second etchant may be HF, HNO 3 And Hac or HF, H 2 O 2 And Hac.
Due to the fact thatIn this step, the device layer 120 is etched by the second etchant, a porous layer with a depth of several tens of nanometers is formed on the surface of the device layer 120, the material of the porous layer of the device layer 120 is silicon and a silicon-oxygen compound, wherein the silicon-oxygen compound is H in the second etchant 2 O 2 Or HNO 3 Reacting with the surface of the device layer.
As shown in fig. 7 and 8, next, step S4 is performed, a sacrificial oxide layer 140 is formed on the device layer 120, the sacrificial oxide layer 140 fills and covers the porous layer 121, and the sacrificial oxide layer 140 and the porous layer 121 are removed by a wet etching process to obtain a silicon-on-insulator structure.
The method specifically comprises the following steps:
as shown in fig. 7, first, in order to remove the porous layer 121, an oxidation treatment is performed on the surface of the device layer 120 under an atmosphere of dry oxygen, wet oxygen, or a combination of dry oxygen and wet oxygen to generate a sacrificial oxide layer 140 on the device layer 120, wherein the sacrificial oxide layer 140 fills and covers the porous layer 121. The oxidation temperature during the oxidation treatment is 700-1100 ℃, preferably 750-1000 ℃. The thickness of the sacrificial oxide layer 140 is 50nm to 200nm, that is, 50nm to 200nm of silicon on the surface of the device layer 120 is oxidized into the sacrificial oxide layer. The oxidation time in the oxidation treatment is determined according to the thickness of the sacrificial oxide layer 140 and the oxidation temperature.
As shown in fig. 8, a wet etching process then removes the sacrificial oxide layer 140 and the porous layer 121 to obtain a silicon-on-insulator structure.
In detail, first, the wet etching process removes the sacrificial oxide layer 140 and the porous layer 121 using an HF solution. Wherein the concentration of the HF solution is less than 20%, preferably, the concentration of the HF solution is 5%, and in this case, the porous layer 121 is effectively removed.
Next, the surface of the device layer 120 is subjected to a roughness optimization process by a thermal process (i.e., a rapid thermal process or a long thermal process or both of them are alternated), thereby further reducing the surface roughness of the device layer 120. Wherein the atmosphere during the heat treatment is a hydrogen-argon mixed atmosphere or a pure argon atmosphere. This step removes the porous layer 121 of high frequency erosion undulation porous morphology by removing the sacrificial oxide layer 140 so that the surface of the device layer 120 is free of the porous layer 121.
As shown in fig. 9, the surface of the device layer of the prior art silicon-on-insulator structure is formed with a porous layer 121, which makes the thickness uniformity of the device layer difficult to control. As shown in fig. 10, the surface of the device layer of the soi structure of this embodiment has a high uniformity of the thickness of the device layer due to the removal of the porous layer 121.
The embodiment also provides a silicon-on-insulator structure which is prepared by the forming method of the silicon-on-insulator structure.
In summary, the present invention provides a silicon-on-insulator structure and a method for forming the same, wherein the method for forming the silicon-on-insulator structure comprises the following steps: step S1: providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface; step S2: performing activation treatment on the second front surface and the surface of the device layer, and bonding the first substrate and the second substrate, wherein the second front surface faces the device layer; and step S3: thinning the first substrate from the first back surface, and removing the rest first substrate and the etch stop layer in sequence through two selective etching processes, so that the surface of the device layer is provided with a porous layer; and step S4: and generating a sacrificial oxide layer on the device layer, filling and covering the porous layer with the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure. According to the invention, the normal-temperature bonding strength in the bonding process is increased through the activation treatment, and the temperature required by the bonding process is reduced, so that the thermal diffusion of heterogeneous components (germanium) in the corrosion stop layer is reduced, the interface between the corrosion stop layer and the device layer is ensured to be clear, and the thickness uniformity deterioration of the device layer after the subsequent removal of the corrosion stop layer is avoided; the uniformity of the device layer after corrosion is controlled by two times of selective corrosion processes, so that the thickness uniformity of the finally obtained device layer with the silicon-on-insulator structure is less than 10%; the porous structure (i.e., the porous layer) which enables the surface of the device layer to be free from high-frequency corrosion fluctuation (porous morphology) is also formed and removed through the sacrifice oxide layer.
In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used for distinguishing various components, elements, steps and the like in the specification, and is not used for representing logical relationships or sequential relationships among the various components, elements, steps and the like.

Claims (11)

1. A method of forming a silicon-on-insulator structure, comprising the steps of:
step S1: providing a first substrate and a second substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged, an etching stop layer and a device layer are sequentially formed on the first front surface, and the second substrate is provided with a second front surface;
step S2: performing activation treatment on the second front surface and the surface of the device layer, and bonding the first substrate and the second substrate, wherein the second front surface faces the device layer;
and step S3: thinning the first substrate from the first back surface, and sequentially removing the remaining first substrate and the etching stop layer through two selective etching processes, so that the surface of the device layer has a porous layer; and
and step S4: and generating a sacrificial oxide layer on the device layer, filling and covering the porous layer with the sacrificial oxide layer, and removing the sacrificial oxide layer and the porous layer through a wet etching process to obtain the silicon-on-insulator structure.
2. The forming method of claim 1, wherein step S1 includes:
providing a first substrate, wherein the first substrate is provided with a first front surface and a first back surface which are oppositely arranged;
forming an etch stop layer on the first front side;
forming a device layer on the etch stop layer;
providing a second substrate, wherein a polycrystalline silicon capturing layer is formed on the surface of the second substrate, and the surface of the polycrystalline silicon capturing layer is the second front surface;
forming an insulating layer through an oxidation process; and
the insulating layer is located on the surface of the device layer, or the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the surface of the device layer, and the second insulating layer is located on the second front surface.
3. The forming method of claim 2, wherein step S2 includes:
when the insulating layer is positioned on the surface of the device layer, activating the second front surface and the surface of the insulating layer by using oxygen plasma; and
the second front face faces the surface of the insulating layer, and low-temperature reinforcement treatment is performed.
4. The forming method of claim 2, wherein step S2 includes:
when the first insulating layer is positioned on the surface of the device layer and the second insulating layer is positioned on the second front surface, the surface of the first insulating layer and the surface of the second insulating layer are activated and treated by oxygen plasma; and
and the surface of the first insulating layer faces to the surface of the second insulating layer, and low-temperature reinforcement treatment is performed.
5. The forming method according to claim 3 or 4, wherein the temperature of the consolidation treatment is 300 ℃ to 500 ℃ and the treatment time is not more than 4 hours.
6. The forming method of claim 1, wherein step S3 includes:
thinning the first substrate from the first backside using mechanical grinding;
selectively etching the rest of the first substrate for the first time by a first etchant, and etching and stopping at the etch stop layer; and
and selectively etching the etching stop layer for the second time by a second etchant, and etching and stopping on the surface of the device layer, so that the surface of the device layer is provided with a porous layer.
7. The method of claim 6, wherein the first etchant is TMAH, the concentration of the first etchant is not higher than 25%, and the etching temperature is 55-70 ℃.
8. The method of claim 6 wherein the second etchant is HF, HNO 3 And Hac, or HF, H 2 O 2 And Hac.
9. The forming method of claim 1, wherein step S4 includes:
carrying out oxidation treatment on the surface of the device layer under the atmosphere of dry oxygen, wet oxygen or combination of dry oxygen and wet oxygen to generate a sacrificial oxide layer on the device layer, wherein the sacrificial oxide layer fills and covers the porous layer;
removing the sacrificial oxide layer and the porous layer by a wet etching process to obtain a silicon-on-insulator structure; and
and carrying out roughness optimization treatment on the surface of the device layer through heat treatment.
10. The method of forming as claimed in claim 9 wherein the wet etch process uses an HF solution having a concentration of less than 20%.
11. A silicon-on-insulator structure prepared by the method for forming a silicon-on-insulator structure according to any one of claims 1 to 10.
CN202211374642.9A 2022-11-04 2022-11-04 Silicon-on-insulator structure and forming method thereof Pending CN115513123A (en)

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CN202211374642.9A CN115513123A (en) 2022-11-04 2022-11-04 Silicon-on-insulator structure and forming method thereof

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