CN115512755A

CN115512755A - Three-dimensional memory, detection method and electronic equipment

Info

Publication number: CN115512755A
Application number: CN202211213434.0A
Authority: CN
Inventors: 周小锋
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2022-12-23

Abstract

The application discloses a three-dimensional memory. The three-dimensional memory comprises a memory array unit, a data memory array and a redundancy memory array, wherein the memory array unit comprises the data memory array and the redundancy memory array; the logic unit is connected with the storage array unit through a three-dimensional heterogeneous integrated structure to form a three-dimensional storage; the logic unit comprises a first testing module and a second testing module, wherein the first testing module is used for testing the data storage array according to a preset period so as to determine the address of an abnormal storage bit in the data storage array, the redundant storage array comprises a replacement storage bit, the address of the replacement storage bit is used for being associated with the address of the abnormal storage bit so as to generate a replacement address association table, so that the replacement storage bit in the redundant storage array stores data stored in the abnormal storage bit based on the replacement address association table, and the data storage array is repaired. The application also discloses a detection method and electronic equipment. Through the mode, the technical problem that the damaged storage array in the storage affects the normal use of the storage is solved.

Description

Three-dimensional memory, detection method and electronic equipment

Technical Field

The present disclosure relates to the field of storage, and in particular, to a three-dimensional memory, a method for detecting the memory, and an electronic device.

Background

The memory is generally divided into volatile memory and nonvolatile memory. Non-volatile memories can retain stored data when power is turned off, while volatile memories can release stored data when power is turned off. During the production and use of the memory, the memory array for storing data may be damaged due to various reasons, and the capacity of storing data may be lost. For example, the memory array cannot continuously store data due to overheating, excessive read/write times, damage caused by external force, short circuit of a circuit and other factors, and becomes a damaged memory array. Therefore, how to detect a damaged memory array in a memory and perform corresponding processing so as not to affect the use of the entire memory becomes a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The application mainly aims to provide a three-dimensional memory, a detection method of the memory and electronic equipment, and the technical problem that the normal use of the memory is influenced by a damaged memory array in the memory can be solved.

In order to solve the above technical problem, the first technical solution adopted by the present application is: a three-dimensional memory is provided. The three-dimensional memory comprises a memory array unit, a data memory array and a redundancy memory array, wherein the memory array unit comprises the data memory array and the redundancy memory array; the logic unit is connected with the storage array unit through a three-dimensional heterogeneous integrated structure to form a three-dimensional storage; the logic unit comprises a first testing module and a second testing module, wherein the first testing module is used for testing the data storage array according to a preset period so as to determine the address of an abnormal storage bit in the data storage array, the redundant storage array comprises a replacement storage bit, the address of the replacement storage bit is used for being associated with the address of the abnormal storage bit so as to generate a replacement address association table, so that the replacement storage bit in the redundant storage array stores data stored in the abnormal storage bit based on the replacement address association table, and the data storage array is repaired.

The logic unit comprises a data access interface, the test module also comprises a second test module, and the first test module and the second test module are respectively connected with the data access interface; the second testing module is used for carrying out initial testing on the three-dimensional memory, and the initial testing is wafer-level testing.

Wherein the second test module is implemented based on a one-time programmable memory.

The logic unit further comprises a multiplexer, the multiplexer comprises an input end, a first output end and a second output end, the input end is connected with the data access interface, the first output end is connected with the first testing module, and the second output end is connected with the second testing module.

The first test module comprises a register and is used for storing first test data and second test data generated in the process of testing the storage array in the storage array unit, the first test data is original data read from the storage array, and the second test data is obtained by data processing of the first test data.

The logic unit comprises a mapping table storage module which is connected with the first test module and used for storing the storage array address mapping information repaired based on the replacement address association table.

The first test module is used for modifying the address of the abnormal storage bit stored by the mapping table storage module into the address of the replacement storage bit in the redundant storage array based on the replacement address association table.

The data storage array and the redundancy storage array are connected through a three-dimensional heterogeneous integrated structure; the redundant storage array comprises a plurality of redundant storage units, the data storage array comprises a plurality of data storage units, the redundant storage units correspond to the data storage units in position, and the position correspondence comprises projection complete coincidence or projection partial coincidence.

The logic unit comprises a storage control module which is connected with the first test module and the second test module so as to read data from the storage array unit or write data into the storage array unit, thereby completing the test.

In order to solve the above technical problem, the second technical solution adopted by the present application is: a method for testing a memory is provided. The method comprises the steps that a first testing module in a logic unit tests a data storage array in a storage array unit according to a preset period to determine abnormal storage bits in the data storage array; causing a replacement storage bit in the redundant storage array to store data of an abnormal storage bit in the data storage array based on the replacement address association table; the replacement address association table is generated based on the association relation between the address of the replacement storage bit and the address of the abnormal storage bit, and the logic unit is connected with the storage array unit through a three-dimensional heterogeneous integrated structure to form the three-dimensional storage.

Wherein, the first test module in the logic unit tests the data storage array in the storage array unit according to a preset period, to determine the anomalous storage bit in the data storage array comprises: the first test module reads first data from a target storage array in the storage array unit and obtains second data based on the first data; writing the second data into the target storage array to replace the first data in the target storage array; reading data corresponding to the second data from the target storage array to obtain third data; matching the third data with the second data; if the matching is successful, writing the first data into the target storage array, and replacing the second data in the target storage array; reading data corresponding to the first data from the target storage array to obtain fourth data; matching the fourth data with the first data; if the third data and the second data are unsuccessfully matched or the fourth data and the first data are unsuccessfully matched, judging that the target storage array corresponding to the first data is an abnormal storage array, and determining abnormal storage bits in the abnormal storage array according to the matching result of the third data and the second data and/or the matching result of the fourth data and the first data.

Wherein causing the replacement storage bit in the redundant storage array to store data of the abnormal storage bit in the data storage array based on the replacement address association table comprises: and replacing the physical address corresponding to the abnormal storage bit in the address mapping relation with the physical address of the replacement storage bit based on the replacement address association table.

And if the third data and the second data are unsuccessfully matched or the fourth data and the first data are successfully matched, judging that the target storage array corresponding to the first data is successfully detected, and determining that the target storage array is a normal storage array.

In order to solve the above technical problem, the third technical solution adopted by the present application is: there is provided an electronic device comprising a processor and a memory, the memory being a three-dimensional memory as described in the first aspect, or the memory storing a computer program, the processor being configured to execute the computer program to implement the method described in the second aspect.

The beneficial effect of this application is: the memory comprises a storage array unit and a logic unit, the logic unit further comprises a test module, the storage array unit and the logic unit are connected through a three-dimensional heterogeneous integrated structure, the test module can test and repair a storage array in the storage array unit according to a preset period, abnormal data storage bits in the storage array unit, namely damaged storage bits, are detected in time, corresponding repair processing is carried out, addresses of the replaced storage bits in a redundant storage array in the storage array unit are used for replacing addresses of the abnormal data storage bits so as to complete repair of the storage array unit, and the overall continuous use of the memory is not influenced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a three-dimensional memory according to a first embodiment of the present application;

FIG. 2 is a schematic structural diagram of a second embodiment of the three-dimensional memory of the present application;

FIG. 3 is a schematic structural diagram of a first embodiment of a logic unit in a three-dimensional memory according to the present application;

FIG. 4 is a schematic structural diagram of a second embodiment of a logic unit in a three-dimensional memory according to the present application;

FIG. 5 is a schematic structural diagram of a third embodiment of a logic unit in a three-dimensional memory according to the present application;

FIG. 6 is a schematic block diagram of an embodiment of a dynamic BIST test module according to the present application;

FIG. 7 is a schematic block diagram of one embodiment of a logic cell in a three-dimensional memory according to the present application;

FIG. 8 is a flow chart illustrating a first embodiment of a method for testing a memory according to the present application;

FIG. 9 is a flow chart illustrating a second embodiment of a method for testing a memory according to the present application;

FIG. 10 is a block diagram of an embodiment of a computer readable storage device according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a three-dimensional memory according to a first embodiment of the present application.

In this embodiment, the three-dimensional memory implements a three-dimensional heterogeneous integrated structure by bonding. The three-dimensional memory includes a memory array unit 10 and a logic unit 11. The memory array unit 10 is used for storing data information, and the logic unit 11 is used for realizing corresponding logic functions. The three-dimensional memory is further integrated with a first bonding area 12 and a second bonding area 13. The first bonding area is connected with the memory array unit 10, and the second bonding area 13 is connected with the logic unit 11. The memory array unit 10 and the logic unit 11 are connected through the first bonding area 12 and the second bonding area 13, so that the memory array unit 10 and the logic unit 11 are bonded in a stacked manner to form a three-dimensional heterogeneous integrated structure.

The logic unit 11 includes a test module, and the test module may be configured to test and repair the storage array in the storage array unit 10 according to a preset period, find out a damaged storage array existing in the storage array, and replace the damaged storage array with a redundant storage array in the storage array to ensure subsequent normal use of the memory. The specific process may be that after the test module tests the data storage array according to a preset period, the address of the abnormal storage bit in the data storage array is determined, then a replacement storage bit is determined in the redundant storage array for replacing the abnormal storage bit, and the physical address of the replacement storage bit is associated with the physical address of the abnormal storage bit to generate an address association table. According to the address association table, the test module replaces the physical address of the abnormal storage bit in the address mapping information with the physical address of the replacement storage bit according to the address association table, so that the replacement storage bit can store the data which is required to be stored in the abnormal storage bit, and the repair of the data storage array is completed.

In this embodiment, the memory includes a storage array unit and a logic unit, and the logic unit further includes a test module, where the storage array unit and the logic unit are connected by a three-dimensional heterogeneous integrated structure, so that the test module can be used to test and repair a storage array in the storage array unit according to a preset period, thereby detecting a damaged storage array in the storage array unit in time, and performing corresponding repair processing.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a three-dimensional memory according to a second embodiment of the present application.

In this embodiment, the three-dimensional memory implements a three-dimensional heterogeneous integrated structure by bonding. The three-dimensional memory includes a memory array unit 10 and a logic unit 11. The memory array unit 10 is used for storing data information, and the logic unit 11 is used for realizing corresponding logic functions.

The three-dimensional memory is further integrated with a first bonding area 12 and a second bonding area 13. The first bonding area is connected with the memory array unit 10, and the second bonding area 13 is connected with the logic unit 11. The memory array unit 10 and the logic unit 11 are connected through the first bonding area 12 and the second bonding area 13, so that the memory array unit 10 and the logic unit 11 are bonded in a stacked manner to form a three-dimensional heterogeneous integrated structure. It also includes a substrate 15 and solder balls 14 for fixing the logic unit 11 on the substrate 15.

The logic unit 11 in this embodiment includes a test module, and the test module may be configured to test and repair the storage array in the storage array unit 10 according to a preset period, find out a damaged storage array existing in the storage array, and replace the damaged storage array with a redundant storage array in the storage array to ensure subsequent normal use of the memory.

Besides the bonding mode, the three-dimensional heterogeneous integrated structure also has other modes of system-level multifunctional integration through heterogeneous material epitaxial growth or line of sight transfer. The structure integration of the present application may also include D2I (Die to Interposer, integrated on Interposer), D2W (Die to Wafer), W2W (Wafer to Wafer), integrated and the like.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a logic unit in a three-dimensional memory according to a first embodiment of the present application.

The logic unit 11 includes a test module and a data access interface 100. The test module further includes a first test module 110 and a second test module 120, and the first test module 110 and the second test module 120 are respectively connected to the data access interface 100 to receive the relevant program instructions to perform the corresponding test tasks.

The first testing module 110 is configured to test and repair the storage array in the storage array unit 10 according to a preset period after the three-dimensional memory completes an initial test. The second testing module 120 is used for performing an initial test on the three-dimensional memory, where the initial test is a wafer-level test and repair task.

In one embodiment, the second test module 120 may be implemented based on one-time programmable memory.

In one embodiment, the first testing module 110 further includes a register for storing data generated during the testing of the memory array in the memory array unit 10. The data includes first test data and second test data. The first test data is raw data read directly from the memory array. The second test data is obtained by data processing of the first test data. The data processing mode comprises an inversion operation and the like.

In one embodiment, the logic unit 11 further includes a multiplexer (not shown). The multiplexer includes an input, a first output, and a second output. The input terminal is connected to the data access interface 100, the first output terminal is connected to the first testing module 110, and the second output terminal is connected to the second testing module 120.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a logic unit in a three-dimensional memory according to a second embodiment of the present application.

In this embodiment, the logic unit 11 includes a test module and a data access interface 100. The test module further includes a first test module 110 and a second test module 120, and the first test module 110 and the second test module 120 are respectively connected to the data access interface 100 to receive the relevant program instructions to perform the corresponding test tasks.

The logic unit 11 further includes a mapping table storage module 130, connected to the first test module 110, for storing the repaired storage array address mapping information.

In one embodiment, the memory arrays in the memory array unit 10 include a first memory array and a second memory array. The first storage array is a redundant storage array, which is a normal storage array that can be used to store data, but which is not typically used to store data. The second storage array is a normal data storage array in which data will typically be stored. The first and second memory arrays may be stored in different locations, such as different wafer regions. For example, referring to fig. 1, the memory array unit 10 is formed by stacking a plurality of wafers, and in an embodiment, the memory array corresponding to the lowest wafer serves as a first memory array, and the memory arrays corresponding to the other wafers above serve as second memory arrays. The first memory array may be disposed in different wafer regions, that is, in the memory array unit, a part of the memory arrays corresponding to each layer of wafer is taken out as the first memory array, and the rest is taken as the second memory array, referring to fig. 1, which corresponds to that in the memory array unit 10, the memory array in the rightmost column is taken as the first memory array, and the rest is taken as the second memory array. The projections of the first storage arrays in the vertical direction may be the same or different, and in an embodiment, referring to fig. 1, in the storage array unit 10, the rightmost column of the five lower layers of wafers serves as the first storage array, and the leftmost column of the five upper layers of wafers serves as the first storage array.

The data storage array and the redundant storage array are connected by a three-dimensional heterogeneous integrated structure. In one embodiment, the redundant storage array comprises a plurality of storage units, the data storage array comprises a plurality of data storage units, the redundant storage units correspond to the data storage units in positions, and the position correspondence comprises the projection complete coincidence or the projection partial coincidence. Specifically, referring to fig. 2, when the storage array corresponding to the lowest layer of wafer is used as the redundant storage array, the projections of the redundant storage unit and the data storage unit in the direction perpendicular to the bonding surface on the horizontal plane of the bonding surface are completely overlapped, that is, each data storage unit can find the redundant storage unit in the same column thereof, so that when the data storage unit is abnormal, the physical address of the abnormal storage unit in the address mapping information can be replaced by the physical address of the redundant storage unit in the same column thereof, so that the redundant storage unit can store data which needs to be stored in the abnormal storage unit, and the normal use of the data storage array is ensured. When the storage array corresponding to the lowest layer of wafer and the rightmost row of storage arrays are used as redundant storage arrays, the projection parts of the redundant storage units and the data storage units on the horizontal plane of the bonding surface in the direction perpendicular to the bonding surface are overlapped, and each data storage unit can also find the corresponding redundant storage unit in the same row. When the redundant memory cells in the same column are all occupied, the redundant memory cells in other positions are selected. Compared with the redundant memory cells in the same column as the abnormal memory cells, the redundant memory cells in other columns have better speed adaptability during data storage.

In the process of testing the second storage array by the first testing module 110, it is determined whether an abnormal data storage array exists in the second storage array. The abnormal data storage array is a damaged data storage array formed by various factors, such as overheating, excessive read-write times, damage caused by external force, circuit short circuit and the like, and the normal data storage task cannot be resumed. When it is detected that an abnormal data storage array exists in the second storage array, the abnormal data storage array is replaced with the first storage array.

In one embodiment, when it is detected that an abnormal data storage array exists in the second storage array, the first test module 110 replaces the abnormal data storage array that cannot be used further with the first storage array in the following manner. The first testing module 110 is configured to modify the physical address information of the abnormal data storage array stored in the mapping table storage module 130 into the physical address information of the first storage array. The mapping table storage module 130 stores a mapping relationship between a logical address required for data access and a physical address of the storage array. Each logical address is represented by its corresponding physical address. When the abnormal data storage array is detected, determining an address mapping relation corresponding to the physical address of the abnormal data storage array, namely determining a logical address corresponding to the physical address of the abnormal data storage array, and replacing the physical address of the abnormal data storage array in the address mapping relation with the physical address of the first storage array. Since the first storage array is a storage array that can be normally used, data access based on the address mapping relationship after replacement with the physical address of the first storage array can be normally performed. The replaced first storage array will perform normal data access tasks as the new second storage array.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a logic unit in a three-dimensional memory according to a third embodiment of the present invention.

On the basis of the above embodiment, the logic unit 11 further includes a storage control module 140. The memory control module 140 is connected to the first test module 110 and the second test module 120, and is used for writing data into the memory array or reading data from the memory array. In this embodiment, the storage control module 140 is indirectly connected to the first testing module 110 through the mapping table storage module 130.

In one embodiment, the above module units and the like may be connected to each other through a bus-like structure, so that the modules have connection transmission capability.

In one embodiment, the test module is a BIST test module. The first test module is a static BIST test module (SBIST, static built-in-self test), the second test module is a dynamic BIST test module (DBIST, dynamic built-in-self test), and the static BIST test module is used for performing conventional wafer-level initial test and repair process. The initial test is a static test, and is generally performed before the storage product is shipped after the storage product is manufactured. The dynamic BIST test module is used for performing damage of the memory array and performing corresponding processing. The dynamic BIST test module has a timing inspection mechanism, and can test and repair the memory array according to a preset period when the memory works normally.

The dynamic BIST test module may further include a temporary data register, a status register, a test control unit, a data comparison unit, and the like, for implementing the above test process. FIG. 6 is a schematic structural diagram of an embodiment of a dynamic BIST test module according to the present application. The dynamic BIST test module is mainly divided into three parts. The first part comprises a status register, a temporary data register and a test controller, and is used for controlling the starting and ending of the test flow and storing the test result. The second part comprises a memory reading device, a memory recording device and a data comparator, and is used for acquiring the data read from the storage array unit through the SRAM according to the control test command, and further processing and comparing the data to obtain a test result. The third part is SRAM, which is used to store the data read to the test module for testing, and to store the intermediate data and test result in the test process.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a logic unit in a three-dimensional memory according to an embodiment of the present invention.

In this embodiment, the logic unit 11 includes an SBIST test module and a DBIST test module. The SBIST test module is connected with the data access interface and the memory controller through eFUSEs so as to realize initial test and repair of the memory through the memory controller. eFUSEs are one time programmable memories. eFUSEs were developed based on the electro-migration EM technology, and the electro-migration property can be used to create very small fuse structures. The generated EM fuse can be programmed on a chip, can be applied to a wafer detection stage, can also be applied to a packaging test stage and the like. Because eFUSEs are capable of being programmed only one fuse at a time, these fuses can reduce the cost of testing and self-repair when mated with the BIST test module. The DBIST test module is connected with the data access interface and is connected with the memory controller through the mapping table memory so as to realize the test and repair method for the memory array.

Referring to fig. 8, fig. 8 is a flowchart illustrating a first embodiment of a memory detection method according to the present application. Which comprises the following steps:

s11: and a first test module in the logic unit tests the data storage array in the storage array unit according to a preset period so as to determine abnormal storage bits in the data storage array.

S12: causing a replacement storage bit in the redundant storage array to store data of the abnormal storage bit in the data storage array based on the replacement address association table.

The first testing module tests the data storage array according to a preset period, determines an abnormal storage bit in the data storage array and an address of the abnormal storage bit, then determines a replacement storage bit in the redundant storage array for replacing the abnormal storage bit, and the physical address of the replacement storage bit is associated with the physical address of the abnormal storage bit to generate an address association table. According to the address association table, the test module replaces the physical address of the abnormal storage bit in the address mapping information with the physical address of the replacement storage bit according to the address association table, so that the replacement storage bit can store data which needs to be stored in the abnormal storage bit, and detection and repair of the data storage array are completed.

Referring to fig. 9, fig. 9 is a flowchart illustrating a second embodiment of the memory detection method of the present application. Which is a further extension of step S11. Which comprises the following steps:

s21: the first test module reads first data from a target storage array in the storage array unit and obtains second data based on the first data.

The test module selects a target storage array to be tested from the normal second storage array unit, and reads data stored in the target storage array as first data. And after the first data are read, inverting the first data to obtain second data.

S22: and writing the second data into the target storage array to replace the first data in the target storage array.

And writing the second data into the corresponding target storage array which stores the first data.

S23: and reading data corresponding to the second data from the target storage array to obtain third data.

And reading the data stored in the target storage array again, and taking the read data as third data.

S24: and matching the third data with the second data.

And matching the read third data with the previous second data, wherein the matching is successful if the third data is completely the same as the previous second data, otherwise, the matching is failed, and if the matching is successful, the step S25 is executed. Unsuccessfully, step S29 is performed.

S25: and writing the first data into the target storage array to replace the second data in the target storage array.

S26: and reading data corresponding to the first data from the target storage array to obtain fourth data.

And writing the first data read for the first time into the target storage array again, reading the target storage array after the writing is finished, and taking the read data as fourth data.

S27: and matching the fourth data with the first data.

And matching the read fourth data with the previous first data, wherein if the fourth data is completely the same as the previous first data, the matching is successful, and if the fourth data is not completely the same as the previous first data, the matching is failed, and if the matching is successful, the step S28 is executed. Otherwise, step S29 is executed.

S28: the target storage array test is successful.

And matching is successful, which indicates that the data storage function of the target storage array is normal and the test is successful.

S29: and judging that the target storage array corresponding to the first data is an abnormal storage array.

And if the third data and the second data are unsuccessfully matched or the fourth data and the first data are unsuccessfully matched, indicating that the data storage function of the target storage array is abnormal, and judging that the target storage array corresponding to the first data is an abnormal storage array. Further, according to a data matching result of the third data and the second data, or a data matching result of the fourth data and the first data, the abnormal storage bit therein and the physical address of the corresponding abnormal storage bit can be determined.

S30: and replacing the physical address in the mapping relation corresponding to the abnormal storage array with the physical address of the redundant storage array.

And replacing the physical address in the address mapping relation corresponding to the abnormal storage bit in the abnormal storage array in the mapping table storage module with the physical address of the redundant storage array with the normal data storage function so that the memory can continuously and normally finish data access.

Specifically, the physical address corresponding to the abnormal storage bit in the address mapping relation is replaced by the physical address of the replacement storage bit with a normal function based on the address association information in the replacement address association table.

In an embodiment, the test module further includes a register, and during the test, the test module can store data during the test into the register. The data includes first test data and second test data. The first test data is raw data read directly from the memory array. The second test data is obtained by data processing of the first test data. The data processing mode comprises an inversion operation and the like. For example, when the first data is read from the target memory array, the first data is stored in the register for a subsequent test, and when the second data is obtained by inverting the first data, the second data is stored in the register for a subsequent test procedure.

The detection method may be performed according to a preset period to ensure continuity of use of the three-dimensional memory.

As shown in fig. 10, fig. 10 is a schematic structural diagram of an embodiment of an electronic device according to the present application.

The electronic device embodiment of the present application includes a processor 210 and a memory 220. Memory 220 may be any of the embodiments of the three-dimensional memory described above in this application, and possible combinations. The Memory 220 may include a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, and other media capable of storing program instructions, or may also be a server storing the program instructions, and the server may send the stored program instructions to other devices for operation, or may self-operate the stored program instructions.

Alternatively, the memory 220 is used for storing a computer program, and the processor 210 is used for executing the computer program to implement any one of the embodiments and possible combinations of the data processing methods described above in the present application to implement the detection of the memory. The processor 210 may be an integrated circuit chip having the processing capability of signal sequences. The processor 210 may also be a general purpose processor, a digital signal sequence processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

In summary, by arranging the test module in the logic unit, the test module can be used for testing and repairing the storage array in the storage array unit according to a preset period, so that a damaged storage array in the storage array unit can be detected in time, corresponding repair processing is performed, the abnormal data storage array is replaced by the reserved redundant storage array in the storage array unit to complete the repair of the storage array unit, and the overall continuous use of the memory is not affected, so that the reject ratio of finished products in the production process of the memory can be effectively reduced, and the problem of operation fatigue of the memory in the long-term operation process can be solved. And the detection and repair process is completed through the detection module in the storage and editable gate array, the CPU does not need to be processed frequently, the power consumption of the CPU is saved, and the resource consumption and the cost for completing the detection and repair process are low.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated units in the other embodiments described above may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims

1. A three-dimensional memory, the three-dimensional memory comprising:

a memory array unit including a data memory array and a redundant memory array;

the logic unit is connected with the storage array unit through a three-dimensional heterogeneous integrated structure to form the three-dimensional storage;

the logic unit comprises a first testing module and a second testing module, wherein the first testing module is used for testing the data storage array according to a preset period so as to determine the address of an abnormal storage bit in the data storage array, the redundant storage array comprises a replacement storage bit, the address of the replacement storage bit is used for being associated with the address of the abnormal storage bit to generate a replacement address association table, so that the replacement storage bit in the redundant storage array stores the data stored in the abnormal storage bit based on the replacement address association table, and the data storage array is repaired.

2. The three-dimensional memory according to claim 1, wherein the logic unit comprises a data access interface, the test module further comprises a second test module, and the first test module and the second test module are respectively connected with the data access interface;

the second testing module is used for carrying out initial testing on the three-dimensional memory, and the initial testing is wafer-level testing.

3. The method of claim 2, wherein the second test module is implemented based on one-time programmable memory.

4. The three-dimensional memory according to claim 2, wherein the logic unit further comprises a multiplexer, the multiplexer comprising an input, a first output, and a second output, the input being coupled to the data access interface, the first output being coupled to the first test module, the second output being coupled to the second test module.

5. The three-dimensional memory according to claim 1, wherein the first test module includes a register for storing first test data and second test data generated during a test of the memory array in the memory array unit, the first test data is original data read from the memory array, and the second test data is obtained by data processing of the first test data.

6. The three-dimensional memory according to claim 1, wherein the logic unit comprises a mapping table storage module, connected to the first test module, for storing the storage array address mapping information repaired based on the replacement address association table.

7. The three-dimensional memory according to claim 6, wherein the first testing module is configured to modify the address of the exceedingly stored bit stored by the mapping table storage module to an address of a replacement stored bit in the redundant memory array based on the replacement address association table.

8. The three-dimensional memory according to claim 1,

the data storage array and the redundancy storage array are connected through a three-dimensional heterogeneous integrated structure;

the redundant storage array comprises a plurality of redundant storage units, the data storage array comprises a plurality of data storage units, the redundant storage units correspond to the data storage units in positions, and the position correspondence comprises projection complete coincidence or projection partial coincidence.

9. The three-dimensional memory according to claim 1, wherein the logic unit comprises a memory control module connected to the first test module and the second test module to read data from or write data to the memory array unit to complete the test.

10. A method for memory detection, the method comprising:

a first test module in the logic unit tests a data storage array in a storage array unit according to a preset period so as to determine abnormal storage bits in the data storage array;

causing a replacement storage bit in the redundant storage array to store data of an abnormal storage bit in the data storage array based on a replacement address association table;

the replacement address association table is generated based on the association relationship between the address of the replacement storage bit and the address of the abnormal storage bit, and the logic unit and the storage array unit are connected through a three-dimensional heterogeneous integrated structure to form a three-dimensional memory.

11. The method of claim 10, wherein the testing the data storage array in the storage array unit by the first testing module in the logic unit according to a preset cycle to determine the abnormal storage bit in the data storage array comprises:

the first test module reads first data from a target storage array in the storage array unit and obtains second data based on the first data;

writing the second data to the target storage array, replacing the first data in the target storage array;

reading data corresponding to the second data from the target storage array to obtain third data;

matching the third data with the second data;

if the matching is successful, writing the first data into the target storage array to replace the second data in the target storage array;

reading data corresponding to the first data from the target storage array to obtain fourth data;

matching the fourth data with the first data;

if the third data and the second data are unsuccessfully matched or the fourth data and the first data are unsuccessfully matched, judging that the target storage array corresponding to the first data is an abnormal storage array, and determining the abnormal storage bit in the abnormal storage array according to the matching result of the third data and the second data and/or the matching result of the fourth data and the first data.

12. The method of claim 11, wherein causing the replacement storage bit in the redundant storage array to store data for the exceedingly stored bit in the data storage array based on a replacement address association table comprises:

and replacing the physical address corresponding to the abnormal storage bit in the address mapping relation with the physical address of the replacement storage bit based on the replacement address association table.

13. The method of claim 11, further comprising:

the method further comprises the following steps:

if the third data and the second data are unsuccessfully matched or the fourth data and the first data are successfully matched, judging that the target storage array corresponding to the first data is successfully detected and is a normal storage array.

14. An electronic device, characterized in that the electronic device comprises a processor and a memory, the memory being a three-dimensional memory according to any of claims 1-9, or the memory being adapted to store a computer program, the processor being adapted to execute the computer program to implement the method according to any of claims 10-13.