JP2008177389A - Semiconductor wafer, ferroelectric storage device, electronic apparatus, and method of testing ferroelectric storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce time taken to test reliability in a ferroelectric storage device, to improve the reliability, and to reduce manufacturing costs. <P>SOLUTION: A semiconductor wafer W has: a plurality of semiconductor chips CH; a chip TCH for testing; and wiring L1, L2x, and L2y, each arranged between semiconductor chips, for connecting the chip for testing and the semiconductor chips, wherein the semiconductor chip is configured such that it includes ferroelectric memory cell arrays and a test circuit, and the test circuit is configured such that it is driven by signals applied from the chip for the testing through the wiring. The test circuit is also configured such that it has a plurality of memory cells for redundancy compensation and a memory circuit for storing the results of a fatigue test. When the number of the ferroelectric memory cells determined to be defective exceeds the number of memory cells for redundancy, a failure determination is performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer, a ferroelectric memory device, an electronic apparatus, and a method for testing a ferroelectric memory device.

  In general, a reliability test of a semiconductor memory device takes a long time. In particular, a ferroelectric memory device writes / reads data using the polarization phenomenon of a ferroelectric material, and thus a test on the amount of polarization is indispensable for guaranteeing its quality.

  This test is called a fatigue (fatigue property) test, in which a ferroelectric is stressed by repeating a write or read operation a predetermined number of times, and thereafter it is tested whether it operates normally. .

However, the guarantee of the number of times of writing (reading) of the ferroelectric memory device is, for example, on the order of 10 ¹² times, and even if it is operated on the order of several hundreds ns per cycle, a time of several decades is required per bit. It is. Further, in a megabit class storage device, it takes an immense amount of time to perform a fatigue test on all bits.

  Further, such a reliability test is often performed after packaging a semiconductor chip. Therefore, even a semiconductor chip determined to be defective in the reliability test is packaged, resulting in an increase in manufacturing cost. Furthermore, since feedback of test results also takes time, for example, a large number of defective chips may be manufactured without correcting the manufacturing process.

  Therefore, in order to perform the test in the semiconductor wafer state, a device such as a test for every one chip (or 2 to 4 chips) using a probe card has been devised, but there is a limit to reducing the time required for the reliability test. was there.

In addition, as a prior art concerning a reliability test, there exist some which are shown, for example in the following patent documents 1-3, and the following patent document 1 discloses the technique regarding the improvement of the data retention characteristic of a non-volatile memory | storage device. Patent Documents 2 and 3 listed below disclose techniques for testing the deterioration of ferroelectric memory cells.
Japanese Patent Application Laid-Open No. 9-82774 Japanese Patent Laid-Open No. 2003-249074 JP 2003-308700 A

  An object of the present invention is to provide a ferroelectric memory device that can reduce the time required for a reliability test, a test method thereof, and the like. Another object is to improve the reliability of the ferroelectric memory device. Another object is to reduce the manufacturing cost of the ferroelectric memory device.

  (1) A semiconductor wafer according to the present invention includes a plurality of semiconductor chips, a test chip, and a wiring that connects the test chip and the semiconductor chip and is disposed between the semiconductor chips. The semiconductor chip has a ferroelectric memory cell array and a test circuit, and the test circuit is driven by a signal applied from the test chip via the wiring.

  According to such a configuration, a plurality of semiconductor chips can be collectively tested in a wafer state. Therefore, the time required for a test (for example, a reliability test) can be reduced.

  For example, the test circuit has an all address selection circuit, selects all addresses, and collectively performs a write operation on the ferroelectric memory cells. According to such a configuration, batch writing of the ferroelectric memory cell array of a plurality of semiconductor chips becomes possible.

  For example, the test circuit performs a fatigue test by repeatedly performing the write operation. According to such a configuration, a fatigue test of a plurality of semiconductor chips can be performed at a time in a wafer state.

  For example, the test circuit includes a circuit for sequentially reading the ferroelectric memory cells. According to such a configuration, the data of the memory cells after the fatigue test can be read sequentially.

  For example, the test circuit includes a count circuit that counts the number of ferroelectric memory cells determined to be defective by the fatigue test. According to this configuration, the number of defective memory cells can be recognized.

  For example, the test circuit includes a storage circuit that stores a result of the fatigue test. According to such a configuration, it is possible to easily determine whether or not the semiconductor chip is defective.

  For example, the test circuit includes a plurality of redundant relief memory cells and a memory circuit that stores the result of the fatigue test, and the failure test of the fatigue test is performed by determining the number of ferroelectric memory cells determined to be defective. Is performed when the number of redundant memory cells is exceeded. According to such a configuration, it is possible to perform defect determination in consideration of redundancy relief.

  For example, a TEG (test element group) is arranged on the test chip. According to such a configuration, the test chip can be effectively used.

  (2) A ferroelectric memory device according to the present invention includes a semiconductor chip cut out from the semiconductor wafer. According to such a configuration, the quality of the ferroelectric memory device can be improved because the quality is determined by the test. In addition, since the tests can be performed collectively in the wafer state, the test time can be shortened and the manufacturing cost of the ferroelectric memory device can be reduced.

  (3) An electronic apparatus according to the present invention includes the ferroelectric memory device. With this configuration, the reliability of the electronic device can be improved. In addition, the manufacturing cost of the electronic device can be reduced.

  Here, the electronic device refers to a general device having a certain function provided with the ferroelectric memory device according to the present invention, and the configuration thereof is not particularly limited. For example, the electronic device includes the ferroelectric memory device. It includes all devices that require a storage device, such as computer devices in general, mobile phones, PHS (Personal Handyphone System), PDA (Personal Digital Assistant), electronic notebook, IC (integrated circuit) card.

  (4) A method for testing a ferroelectric memory device according to the present invention includes a plurality of semiconductor chips, a test chip, a wiring that connects the test chip and the semiconductor chip, and is disposed between the semiconductor chips. , A ferroelectric memory cell array formed on the semiconductor chip, and a ferroelectric memory device having a test circuit, the test circuit from the test chip via the wiring The ferroelectric memory cell array in a plurality of semiconductor chips is collectively tested by driving the.

  According to this method, a plurality of semiconductor chips can be collectively tested in the wafer state. Therefore, the time required for the test can be reduced. In addition, since the tests can be performed collectively in the wafer state, the test time can be shortened and the manufacturing cost of the ferroelectric memory device can be reduced.

  For example, the test circuit has an all address selection circuit, selects all addresses, collectively performs a write operation on the ferroelectric memory cell, and further performs the write operation repeatedly. According to this method, a so-called fatigue test of the ferroelectric memory cell array of a plurality of semiconductor chips can be performed at once.

  For example, the test circuit includes a circuit for sequentially reading the ferroelectric memory cells, and a circuit for comparing read data of the ferroelectric memory with predetermined data, and reading the ferroelectric memory cells. If the data is different from the predetermined data, it is determined as defective. According to this method, the quality of the ferroelectric memory cell can be easily determined.

  For example, the test circuit includes a count circuit, and counts the number of ferroelectric memory cells determined to be defective. According to this method, the number of defective memory cells can be recognized.

  For example, the ferroelectric memory cell array has a plurality of redundant relief memory cells, the test circuit has a memory circuit for storing the results of the fatigue test, and is determined to be defective. When the number of memory cells exceeds the number of redundant memory cells, predetermined data is stored in the storage circuit. According to such a configuration, it is possible to perform defect determination in consideration of redundancy relief. Further, by looking at data in the memory circuit, it can be easily determined whether or not the semiconductor chip is defective.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.
(Storage device configuration)
FIG. 1 is a plan view showing a configuration of a ferroelectric memory device (semiconductor wafer) according to the present embodiment. As shown in the drawing, a plurality of semiconductor chips CH are formed on the semiconductor wafer W. Here, a test chip TCH is provided at a substantially central portion of the semiconductor wafer W. In addition, a ferroelectric memory device is formed on the plurality of semiconductor chips CH. This ferroelectric memory device has a memory cell array and a peripheral circuit section. The memory cell array is composed of a plurality of memory cells MC arranged in an array, and each memory cell is arranged at the intersection of the word line WL and the bit line BL (see FIG. 9). In addition, as the peripheral circuit, for example, a word line control unit, a plate line control unit, a bit line control unit, etc., a circuit necessary for driving (reading / writing) a memory cell, as well as a reliability test described in detail later. A test circuit is arranged.

  The plurality of semiconductor chips CH and the test chip TCH are connected via wirings (trunk lines) L2x and L2y and wirings (branch lines) L1 formed in a scribe region (scribe line, region between semiconductor chips) SA. .

  Specifically, the wiring L2x extends between the semiconductor chips CH in the x direction. Further, the wiring L2y extends between the semiconductor chips in the y direction. Further, the wiring L2x and each semiconductor chip CH are connected by a wiring L1 extending in the y direction. Here, the wiring L1 is connected to a predetermined region of the semiconductor chip CH. In FIG. 1, a wiring L1 is connected toward the upper side extending in the x direction of each semiconductor chip. By wiring in this way, the layout of the test circuit is the same in each semiconductor chip, and it is easy to manufacture. Note that the number of wirings L1, L2x, and L2y and the layout thereof can be changed as appropriate. Also, the number of these wirings is not necessarily one, and may be a plurality as described later. Although not shown, the wirings L2x and L2y are also connected via contact holes. Thus, the wirings L1, L2x, and L2y are composed of two or more layers. Further, these wirings are formed by using a sputtering method, a plating method, or the like in a wafer process.

  FIG. 2 shows a partially enlarged view of the scribe area SA of the semiconductor wafer W. As shown in the figure, four wirings L2xa to L2xd extend in the x direction and are connected to the pads Pa to Pd of the semiconductor chip CH by the wirings L1a to L1d via the contact holes C1a to C1d. More specifically, a probe (needle) of a probe card is brought into contact with a pad (not shown) of the test chip TCH, and signals necessary for the pads Pa to Pd via the wirings L1a to L1d, L2x, and L2y ( Potential).

  As described above, in the present embodiment, pads and test circuits for signals necessary for the reliability test are provided on the semiconductor chip CH, and the semiconductor chip CH is formed in the scribe area SA by the control circuit formed on the test chip TCH. A potential can be applied to the pads Pa to Pd through the wirings L1, L2x, and L2y. In other words, the reliability test of a plurality of semiconductor chips (ferroelectric memory devices) CH can be collectively performed in a wafer state.

  In addition, since the test chip TCH is provided in the substantially central portion of the wafer, a control circuit that can withstand large driving can be provided in such a region, and the reliability test of a plurality of semiconductor chips CH can be performed efficiently. it can.

  FIG. 3 is a plan view showing the configuration of another ferroelectric memory device (semiconductor wafer) of the present embodiment. In FIG. 3, a plurality of test chips TCH are provided on a semiconductor wafer W. The test chip CH is provided for each mask shot region MS.

  Thus, by providing a plurality of test chips TCH in the semiconductor wafer W, the number of semiconductor chips CH controlled by one test chip TCH can be reduced. Therefore, it is possible to cope with an increase in the number of chips per wafer accompanying an increase in the size of the semiconductor wafer W or a reduction in the chip size. Further, it is possible to reduce a risk that the test chip TCH becomes defective due to adhesion of foreign matters in the manufacturing process and the test becomes impossible.

  Furthermore, by providing the test chip TCH for each mask shot region MS, the manufacturing process can be simplified. Note that the test chip TCH formed in one mask shot region MS may be used to test the semiconductor chip CH formed in the mask shot region MS, or a certain range of semiconductor chips CH from the test chip TCH may be tested. You may test. In FIG. 3, the test chip TCH is provided at the lower left corner of the mask shot area MS, but it may be arranged at another location (for example, substantially the center of the mask shot area MS).

  Thus, according to the present embodiment, a plurality of semiconductor chips can be collectively tested in the wafer state. Therefore, the time required for the test can be reduced. Further, the manufacturing cost of the ferroelectric memory device can be reduced.

In particular, this embodiment is suitable for use in a fatigue test that requires a test time among reliability tests. Moreover, as will be described later, the number of signals used in the fatigue test is limited. For example, a power supply potential, a ground potential, a test mode switching signal, and a test input signal are applied to the pads Pa to Pd. Further, a pad or wiring for a test address increment clock or a test circuit reset signal may be provided. As described above, if the number of signal lines is 4 to 6, and at most about 10, the signal lines can be easily routed using the scribe area. Therefore, the number of signal lines is preferably 10 or less.
(Test method)
Next, a fatigue test method (test method) for the ferroelectric memory device (semiconductor wafer) will be described with reference to FIGS.

  FIG. 4 is a flowchart showing a fatigue test method for the ferroelectric memory device according to the present embodiment.

  As shown in the figure, when the test is started (Start) S41, a continuous writing sequence S42 is performed. Next, it is determined whether or not there is a normal test chip (whether or not the test chip is operable) (S43). If it is operating (Yes), a continuous reading sequence (fatigue test) is performed. S44 is performed. Thereafter, a general test sequence (another test performed in a wafer state) S45 is performed, and an end (End) S46 is performed. When the test chip is not operating (S43: No), the process proceeds to the general test sequence S45.

  FIG. 5 is a flowchart showing the continuous writing sequence of FIG. As shown in the figure, a test chip is selected (S51), and the probe card is brought into contact therewith. At this time, a connection check is performed to determine whether or not the probe (needle) is hitting the pad of the test chip (S52, S53). If the probe is connected (Yes), the write test signal is enabled (Enable). (S54), and the entire address selection circuit is enabled (S55). Next, write (write) processing is performed on all addresses at once (S56), and the process ends in S59. If the probe is not connected, the next test chip S57 is selected. However, for all the test chips (when there is one test chip on the wafer), the flow is terminated, and when there is another test chip (S58: No), the process returns to the connection check S52.

Here, in batch writing, writing is performed a plurality of times (for example, about 10 ⁹ times) to all memory cells (ferroelectric capacitors) as described later. By such processing, the memory cell is in a state of fatigue (degradation of the ferroelectric capacitor). Note that the number of times of writing requires 10 ¹² to 10 ¹⁵ times, but the number of times can be reduced by performing an acceleration test (such as a high potential test or a high temperature test).

  Therefore, if the reading test is performed by the subsequent continuous reading sequence S44 (FIG. 4) and the normal reading can be performed, the fatigue test is passed.

  FIG. 6 is a flowchart showing the continuous reading sequence of FIG. As shown in the figure, the read test signal is enabled (S61), and the address A (n) is initialized (n = 0) (S62). Next, the address A (n) is selected (S63), and the data at the address is read (S64). Next, it is determined whether or not the read data is the expected value (“1” or “0”) (S65). If the read data matches the expected value (Yes), the address A (n) is the maximum address. It is determined whether or not the value is (max) (S66). If it is not the maximum value (No), the address n is set to n + 1 (S67). Next, n + 1 addresses are selected (S63). In this manner, the address is counted up by one, all the memory cells are sequentially read, and the read data is determined. When the address reaches the maximum value, the flow ends (S68).

  Here, the expected value is, for example, data written at the end of the continuous write sequence (S42). Note that predetermined data may be written separately from the continuous writing sequence (S42), and the data may be used as an expected value.

  If the read data is different from the expected value (S65: No), the number of error memory cells is counted up (S69). Next, it is determined whether or not the error count (number of error memory cells) is larger than the redundancy possible number (redundant memory cell number) (S70). If the error count is less than the redundancy possible number (No), the process returns to step S66. If the error count exceeds the redundancy possible number (S70: Yes), an error flag is set (S71) and the process is terminated (S68).

  As described above, according to the present embodiment, the write operation (fatigue test) can be collectively performed on a plurality of memory cells in the memory cell array by all the address circuits in the test circuit.

  Further, according to the present embodiment, the data in the memory cells can be read sequentially by the circuit for sequentially reading the memory cells in the test circuit. Therefore, the quality of the memory cell can be easily determined by comparing the data with data (expected value) that should have been written.

Therefore, the fatigue test of the number of semiconductor chips × the number of memory cells can be performed at a time in the wafer state. For example, if it takes 40 minutes to write 10 ⁹ times of 1 bit (one memory cell), a test time of “40 minutes × number of memories in memory cell array × number of chips on wafer” is required. The test time can be reduced to 40 minutes.

  Further, the quality of the semiconductor chip (ferroelectric memory device) itself can be easily determined by counting the number of defective memory cells and comparing with the number of redundant memory cells. Further, when the semiconductor chip is defective, an error flag is set, so that the quality of the semiconductor chip (error determination) can be easily confirmed in the subsequent test process.

  FIG. 7 is a flowchart showing the general test sequence of FIG. As shown in the drawing, the semiconductor chip CH is selected (S75), and the probe card is brought into contact therewith. At this time, a connection check is performed to determine whether or not the probe (needle) hits the pad of the semiconductor chip CH (S76). If the probe (needle) is connected (Yes), an error flag is detected (S77) and an error is detected. Determination (S78) is performed. If there is no error (No), a general test is performed (S79). As this general test, for example, 1) Open / Short test, 2) DC test, 3) Function test (various memory operation tests without speed of memory logic check), 4) AC test, 5) Special mode test ( For example, a non-memory logic operation test) is performed. Next, the quality of the general test is determined (S80), and it is determined whether the general test has been performed for all the semiconductor chips CH (S81). If yes (Yes), the flow ends (S86). If no (No), the next semiconductor chip CH is selected (S85), and the process returns to the connection check S76.

  If there is an error in the error determination (S78) (Yes), it is checked whether the error storage unit (error input unit) itself is broken (S82 to S84). Here, a ferroelectric capacitor is used as the error storage unit. That is, writing “1” or “0” to the ferroelectric capacitor is used as an error flag. Therefore, so-called reverse writing is performed to determine whether the ferroelectric capacitor itself is broken and an error flag is detected or an error flag is set. That is, the write test reset signal is enabled (S82), and the detected write ("1" or "0") data is reset (reverse data is written). Next, reverse data is read (S83), and it is determined whether there is a change in data (S84). If the data does not change (No), the error storage unit is broken, and the process returns to step S79 to perform the general test. When there is a change in data (S84: Yes), the error storage unit is not broken and is judged to be defective in the fatigue test (see S71 in FIG. 6). Judge as bad. Therefore, the next semiconductor chip is selected (S85), and the process returns to the connection check S76.

Thus, in the present embodiment, the general test can be efficiently performed by checking the error flag of the fatigue test. Further, since the same ferroelectric capacitor as that of the memory cell is used for the error memory portion, its manufacture becomes easy. In addition, a test with high reliability can be performed by incorporating the determination of pass / fail of the error storage unit in the test flow.
(Test circuit)
Next, an example of a test circuit used in the above test method will be described.

  First, an example of a test circuit used in the continuous write sequence of the above test method will be described.

  FIG. 8 is a block diagram showing the relationship between the full address selection circuit 110, the test selection circuit 120, and the memory cell 100. FIG. 9 is a circuit diagram showing a configuration of the memory cell, and FIG. 10 is a circuit diagram showing a Y address selection circuit (YSW) 130.

  As shown in FIG. 8, the test selection circuit 120 receives a test signal (Test), a first signal (Tin), and a second signal (Din). The test selection circuit 120 is connected to the full address selection circuit 110. This address all selection circuit 110 is connected to the memory cell array 100. Specifically, it is connected to the word line WL of each memory cell. The Y address selection circuit 130 is provided for each bit line BL.

This address all selection circuit 110 sets all word lines to the H level in response to the test signal. That is, all the memory cells MC are selected. Next, for example, by applying an L level signal to the plate lines PL of all the memory cells and applying an H level signal to the bit lines BL, “1” data is written in all the memory cells. Next, by applying an H level signal to the plate line PL of all the memory cells and applying an L level signal to the bit line BL, “0” data is written in all the memory cells. In this manner, the writing of data “1” and “0” is repeated a predetermined number of times (for example, 10 ¹⁰ times).

FIG. 11 shows a specific circuit example of the all address selection circuit 110 and shows the relationship between the test selection circuit 120 and the memory cell MC. FIG. 12 shows a specific circuit example of the test selection circuit 120. In the circuits shown in FIGS. 11 and 12, a word line decoder 110d, a NOR circuit 110o, and an inverter used for selecting a normal memory cell MC are used. All the word lines WL can be selected. Therefore, all addresses can be selected with a simple configuration. Further, since the inverted signal from the inverter of the NOR circuit 110o by the inverter and the output signal (pl) from the test selection circuit 120 are combined by the NAND circuit 111a and inverted by the inverter, the plate line PL is driven, so that the fatigue test can be easily performed. It can be performed. The Y address selection circuit 130 that drives the bit line BL is controlled by two outputs (Twlsel, dl) of the test selection circuit. The above circuit is merely an example, and various modifications can be made.

  Next, a test circuit used in the continuous reading sequence of the above test method will be described.

  13 shows an example of an address burst shift register circuit, FIG. 14 shows an example of an expected value generation circuit, and FIG. 15 shows an example of an error monitor circuit. FIG. 16 is a diagram showing a connection configuration of these circuits.

  As shown in the figure, the address burst shift register circuit 131 shifts the memory cell MC (n) connected to one bit line BL to the MC (n) by the shift register 131a based on the clock (TCK) signal and the test signal (Test). 0) to MC (n) are sequentially selected. The data of the selected memory cell MC is amplified by the sense amplifier SA, compared with the expected value by the expected value comparison circuit 162, and error determination is performed. This expected value is output from the expected value generation circuit 141. Here, even-numbered I / O and odd-numbered I / O are controlled separately. Therefore, it is possible to detect a defect due to the coupling capacitance between I / Os.

  When the two inputs (read data and expected value) of the expected value comparison circuit 162 are different, for example, “1” is output and the error counter 164 counts the error. Thus, the number of errors counted for each bit line BL is input to the error determination circuit 165, and an error flag signal is output when the total number of errors exceeds the number of redundant repairable memory cells. This error flag signal is used as a read stop signal RR. That is, after the error flag signal (Err Flg) is output, the reading is stopped and it is determined that the chip is defective.

  Further, the error flag signal is input to the error monitor circuit 151 and an error flag is set. That is, a signal indicating an error is stored (held or latched). Here, an error flag is set by applying a potential between the electrodes of the ferroelectric capacitor Ca (FIG. 15) and writing "1" data. The two electrodes of the ferroelectric capacitor Ca are connected to the monitor pads 166a and 166b, and it can be determined whether or not an error flag is set by reading the potential between these pads. FIG. 17 shows a circuit example of the error flag determination circuit. As shown in the figure, the potential between the pads is amplified by an amplifier AP, and the presence / absence of an error flag is output. The amplifier AP is operated by an amplifier activation signal ap.

  In FIG. 16, an error flag is set if there is at least one defect for each I / O (for each bit line) (failure that cannot be redundantly repaired). The error counter 164 may be further aggregated and compared with the redundant relief number or a processing flow may be used.

  AD represents an address decoder, I / O represents an input / output unit, TR represents a test reset signal, and TM represents a test mode signal. T (i) is a selection signal that is an output signal of the address burst shift register circuit 131, and WD is an input signal of the address all selection circuit 110. In this example, a ferroelectric capacitor is used as the error storage unit, but a latch circuit (flip-flop circuit) or the like may be used. Also, various modifications can be made to the circuits shown in FIGS.

  As described above in detail, according to the present embodiment, the time required for the reliability test (particularly the fatigue test) can be reduced. Therefore, throughput can be improved and TAT (turn around time) can be shortened. Further, the test accuracy can be improved, and the reliability of the ferroelectric memory device can be improved. In addition, the test result can be fed back to the manufacturing process at an early stage, and the manufacturing cost of the ferroelectric memory device can be reduced.

  Furthermore, a reliability test of an actual device can be easily performed instead of a selective test using a conventional TEG or some semiconductor chips. Therefore, investigation of the cause such as product analysis when defects frequently occur can be examined in detail. For example, it is possible to accurately grasp the occurrence of a defect due to the position of the semiconductor wafer and the cause thereof. Of course, it is possible to conduct fatigue tests on all actual devices.

  In the above embodiment, the 1T1C ferroelectric memory has been described as an example. However, the present invention can also be applied to a 2T2C ferroelectric memory. In addition, the application state of the potentials of the word line, plate line, and bit line during the fatigue test can be changed as appropriate. In short, different potentials may be applied alternately between the electrodes of the ferroelectric capacitor. In the above embodiment, a control circuit for applying a potential to the wirings L1, L2x, L2y, etc. is formed on the test chip. May be provided with a TEG (a test element, a wiring, a film, or the like). Thereby, TEGs that are often arranged in the scribe region can be collectively arranged on the test chip. Conversely, it is possible to secure a scribe region for routing the wiring for the test.

  In addition, the examples and application examples described through the embodiments of the invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements. The present invention is described in the description of the embodiments described above. It is not limited.

It is a top view which shows the structure of the ferroelectric memory device (semiconductor wafer) of this Embodiment. FIG. 3 is a diagram showing a partially enlarged view of a scribe area SA of a semiconductor wafer W. It is a top view which shows the structure of the other ferroelectric memory device (semiconductor wafer) of this Embodiment. 3 is a flowchart showing a fatigue test method for the ferroelectric memory device according to the present embodiment. FIG. 5 is a flowchart showing a continuous writing sequence of FIG. 4. FIG. 5 is a flowchart showing a continuous reading sequence of FIG. 5 is a flowchart showing a general test sequence of FIG. 3 is a block diagram showing a relationship among an address full selection circuit 110, a test selection circuit 120, and a memory cell 100. FIG. It is a circuit diagram which shows the structure of a memory cell. 3 is a circuit diagram showing a Y address selection circuit (YSW) 130. FIG. FIG. 3 is a diagram showing a specific circuit example of an address all selection circuit 110 and a relationship with a test selection circuit 120 and a memory cell MC. 3 is a diagram illustrating a specific circuit example of a test selection circuit 120. FIG. It is a figure which shows the example of an address burst shift register circuit. It is a figure which shows the example of an expected value generation circuit. It is a figure which shows the example of an error monitor circuit. It is a figure which shows the connection structure of the circuit of FIGS. It is a figure which shows the circuit example of an error flag determination circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Memory cell array, 110 ... Address all selection circuit, 120 ... Test selection circuit, 130 ... Y address selection circuit, 131 ... Address burst shift register circuit, 131a ... Shift register, 141 ... Expected value generation circuit, 151 ... Error monitor circuit 161 ... Expected value comparison circuit, 165 ... Error determination circuit, 166a, 166b ... Monitor pad, ap ... Amplifier activation signal, AD ... Address decoder, BL ... Bit line, Ca ... Ferroelectric capacitor, CH ... Semiconductor chip, C1a to C1d ... contact hole, I / O ... input / output unit, L1, L1a-L1d, L2x, L2y, L2a-L2d ... wiring, MC ... memory cell, MS ... mask shot region, PL ... plate line, Pa-Pd ... pad, RR ... read stop signal, SA ... scribe area, SA ... sen Amplifier, TR ... test reset signal, TM ... test mode signal, TCH ... test chip, W ... semiconductor wafer, WL ... wordline

Claims (15)

A plurality of semiconductor chips;
A test chip;
Connecting the test chip and the semiconductor chip, and having a wiring disposed between the semiconductor chips,
The semiconductor chip has a ferroelectric memory cell array and a test circuit,
The semiconductor wafer, wherein the test circuit is driven by a signal applied from the test chip via the wiring. The test circuit includes:
2. The semiconductor wafer according to claim 1, further comprising an all-address selection circuit, wherein all addresses are selected, and a write operation is collectively performed on the ferroelectric memory cells.   The semiconductor wafer according to claim 2, wherein the test circuit performs a fatigue test by repeatedly performing the write operation.   4. The semiconductor wafer according to claim 2, wherein the test circuit includes a circuit for sequentially reading the ferroelectric memory cells.   5. The semiconductor wafer according to claim 3, wherein the test circuit includes a count circuit that counts the number of ferroelectric memory cells determined to be defective by the fatigue test.   6. The semiconductor wafer according to claim 5, wherein the test circuit has a memory circuit for storing the result of the fatigue test.   The test circuit includes a plurality of redundant relief memory cells and a memory circuit for storing the result of the fatigue test. The fatigue test is performed by determining whether the number of ferroelectric memory cells determined to be defective is redundant. 6. The semiconductor wafer according to claim 5, wherein the semiconductor wafer is formed when the number of memory cells for use is exceeded.   8. The semiconductor wafer according to claim 1, wherein a TEG is disposed on the test chip.   A ferroelectric memory device comprising a semiconductor chip cut out from the semiconductor wafer according to claim 1.   An electronic apparatus comprising the ferroelectric memory device according to claim 9. A plurality of semiconductor chips;
A test chip;
A semiconductor wafer having a wiring connected between the test chip and the semiconductor chip and disposed between the semiconductor chips,
A test method for a ferroelectric memory device having a ferroelectric memory cell array and a test circuit formed on the semiconductor chip,
A test method for a ferroelectric memory device, wherein the ferroelectric memory cell array in a plurality of semiconductor chips is collectively tested by driving the test circuit from the test chip via the wiring. The test circuit includes:
12. The fatigue test according to claim 11, further comprising an all-address selection circuit, selecting all addresses, performing a write operation on the ferroelectric memory cells at once, and repeating the write operation. Method for testing a ferroelectric memory device.   The test circuit includes a circuit for sequentially reading the ferroelectric memory cells and a circuit for comparing read data of the ferroelectric memory with predetermined data, and the read data of the ferroelectric memory cell is 13. The method for testing a ferroelectric memory device according to claim 11, wherein a failure is determined when the data differs from predetermined data.   14. The method of testing a ferroelectric memory device according to claim 13, wherein the test circuit includes a count circuit and counts the number of ferroelectric memory cells determined to be defective. The ferroelectric memory cell array has a plurality of redundant relief memory cells,
The test circuit has a memory circuit for storing the result of the fatigue test, and when the number of ferroelectric memory cells determined to be defective exceeds the number of memory cells for redundancy, a predetermined circuit is stored in the memory circuit. 15. The method for testing a ferroelectric memory device according to claim 14, wherein data is stored.

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