CN115510798A - Chip typesetting method and device, computer readable storage medium and terminal equipment - Google Patents
Chip typesetting method and device, computer readable storage medium and terminal equipment Download PDFInfo
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Abstract
A chip typesetting method and device, a computer readable storage medium and a terminal device are provided, the method comprises: obtaining a typesetting area for typesetting in a wafer and the sizes of a plurality of chips to be distributed; changing the placing sequence of the chips to be placed, and placing the chips to be placed for multiple times in the composition area based on the sizes of the chips to be placed to obtain multiple placement results, wherein each placement result comprises the placing positions of the chips to be placed in the composition area; and acquiring the area utilization rate of the typesetting area corresponding to each layout result, and determining the final layout result based on the area utilization rate so as to obtain the final placing position of the chip to be laid in the typesetting area. The method and the device can improve the typesetting efficiency of the chip during typesetting and improve the area utilization rate of the wafer.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for chip layout, a computer-readable storage medium, and a terminal device.
Background
Chip placement, also known as layout planning (floor plan), is required during semiconductor chip manufacturing. The main purpose of chip typesetting is to improve the area utilization rate of the wafer. At present, the chip typesetting is mainly carried out in a manual typesetting mode.
However, the existing chip typesetting mode depends on manual experience, and the typesetting efficiency is very low. In addition, when the chip typesetting is performed manually, because it is difficult to find a better typesetting mode among multiple typesetting due to the limitation of manual typesetting times and typesetting modes, the area utilization rate of the wafer is generally low.
Disclosure of Invention
The embodiment of the application provides a chip typesetting method and device, a computer readable storage medium and a terminal device, which can improve the typesetting efficiency of chip typesetting and improve the area utilization rate of a wafer.
In order to solve the foregoing technical problem, in a first aspect, an embodiment of the present application provides a chip typesetting method, where the chip typesetting method includes: obtaining a typesetting area for typesetting in a wafer and the sizes of a plurality of chips to be distributed; changing the placing sequence of the plurality of chips to be placed, and performing multiple placement on the plurality of chips to be placed in the composition area based on the sizes of the plurality of chips to be placed to obtain a plurality of placement results, wherein each placement result comprises the placing positions of the plurality of chips to be placed in the composition area; and acquiring the area utilization rate of the typesetting area corresponding to each layout result, and determining the final layout result based on the area utilization rate to obtain the final placing position of the chip to be laid out in the typesetting area.
Optionally, the step of laying out the plurality of chips to be laid out in the layout area for one time includes: presetting a first direction and a second direction for moving a chip to be laid out in a typesetting area; based on the size of each chip to be distributed, determining the distribution result of the plurality of chips to be distributed by moving the chip to be distributed by a first renewable distance and a second renewable distance and determining the placing position of the chip to be distributed; the first updatable distance is the updatable distance of the chip to be laid out in the typesetting area along the first direction; the second updatable distance is an updatable distance of the chip to be laid out in the layout area along a second direction, and the first direction and the second direction are updatable directions of the position of the chip to be laid out relative to the initial position in the layout area.
Optionally, the step of moving the first renewable distance and the second renewable distance to the chip to be placed and determining the placement position of the chip to be placed based on the size of each chip to be placed includes: for each selected chip to be distributed, determining an initial position of the chip to be distributed in the typesetting area according to the size of the chip to be distributed, calculating a plurality of first renewable distances from the initial position according to step length, calculating a second renewable distance at a position corresponding to each first renewable distance, and updating along the second direction at a position corresponding to the maximum value of the second renewable distance to obtain a final position of the chip to be distributed, thereby obtaining a primary distribution result; wherein the update distance is a maximum value of the second updatable distance.
Optionally, the chip typesetting method further includes: obtaining the area utilization rate of the primary layout result; if the area utilization rate does not reach the preset threshold, changing the placing sequence of the plurality of chips to be distributed, and continuing executing the step of distributing the plurality of chips to be distributed in the typesetting area for one time until the area utilization rate with the layout result reaches the preset threshold.
Optionally, if the number of the first update positions where the maximum value of the second updatable distance is located is multiple, selecting a second update position farthest from the initial position, and updating the placement position of the chip to be placed along the second direction at the second update position.
Optionally, the updating the placement position of the chip to be placed along the second direction at the second updated position includes: judging the distance between the second updating position and a third updating position along the first direction, and if the distance is greater than or equal to the width of the chip to be distributed along the first direction, updating the placing position of the chip to be distributed along the second direction at the second updating position; and the third updating position is the updating position which is closest to the initial position in the plurality of first updating positions.
Optionally, the step of changing the placing order of the chips to be laid out and laying out the chips to be laid out for multiple times in the layout area based on the sizes of the chips to be laid out includes: and changing the placing sequence of the chips to be laid out for multiple times, and continuing to perform the step of laying out the chips to be laid out in the typesetting area for one time according to the changed placing sequence to obtain multiple laying out results.
Optionally, the step of obtaining the area utilization rate of the composition area corresponding to each layout result, and determining the final layout result based on the area utilization rate includes: calculating the occupied area of each chip to be laid out when the chip is laid out according to the placement position in each layout result, and the ratio of the area to the area of the layout area to be used as the area utilization rate; and selecting the layout result corresponding to the maximum area utilization rate as the final layout result.
Optionally, if the initial position is the upper right corner of the layout area, one of the first direction and the second direction is left, and the other direction is down; if the initial position is the lower right corner of the typesetting area, one of the first direction and the second direction is left, and the other direction is up; if the initial position is the upper left corner of the typesetting area, one of the first direction and the second direction is right, and the other direction is down; and if the initial position is the lower left corner of the typesetting area, one of the first direction and the second direction is right, and the other direction is up.
Optionally, the position of the chip to be laid out is a position of at least one vertex of the chip to be laid out in the typesetting area.
Optionally, the layout area is quadrilateral, and the shape of the chip is quadrilateral.
In a second aspect, the present application further discloses a chip typesetting apparatus, which includes: the obtaining module is used for obtaining a typesetting area for typesetting in the wafer and the sizes of a plurality of chips to be distributed; the layout module is used for changing the placing sequence of the chips to be laid out, and carrying out multiple layouts on the chips to be laid out in the layout area based on the sizes of the chips to be laid out to obtain multiple layout results, wherein each layout result comprises the placing positions of the chips to be laid out in the layout area; and the layout result determining module is used for obtaining the area utilization rate of the layout area corresponding to each layout result and determining the final layout result based on the area utilization rate so as to obtain the final placement position of the chip to be laid in the layout area.
In a third aspect, this application further discloses a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the method in the first aspect.
In a fourth aspect, an embodiment of the present application further discloses a terminal device, which includes a memory and a processor, where the memory stores a computer program executable on the processor, and the processor executes the steps of the method in the first aspect when executing the computer program.
Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:
according to the technical scheme, when the chips to be distributed are distributed in the layout area in the wafer, the placing sequence of the chips to be distributed is changed, the chips to be distributed are distributed for multiple times in the layout area according to the placing sequence based on the sizes of the chips to be distributed, and the layout result with the highest area utilization rate is selected from the layout results obtained through multiple times of layout to serve as the final layout result, so that the final placing position of the chips to be distributed in the layout area is obtained. According to the method and the device, the placing sequence is changed, the placing chips are placed according to different placing sequences to obtain different placing results, the placing positions of the chips in the different placing results are different, the area utilization rates of the type-setting areas corresponding to the different placing results are different, the placing result with the largest area utilization rate can be selected from the different placing results, and the placing position of the chip with the highest wafer area utilization rate is obtained, so that the type-setting efficiency is greatly improved, and the labor cost is saved; in addition, the area utilization rate of the wafer can be improved during chip typesetting; thereby avoiding the waste of wafer materials and reducing the production cost.
Further, for each selected chip to be distributed, determining an initial position of the chip to be distributed in the typesetting area according to the size of the chip to be distributed, calculating a plurality of first renewable distances according to step length from the initial position, calculating a second renewable distance at a position corresponding to each first renewable distance, and updating along a second direction at a position corresponding to the maximum value of the second renewable distance to obtain a final position of the chip to be distributed, thereby obtaining a primary distribution result. According to the method, the plurality of first renewable distances are calculated in the first direction, the second renewable distance is calculated at the position corresponding to each renewable distance, and the maximum value of the second renewable distance is selected to place the chips to be distributed, so that the chips to be distributed can fully utilize the area in the typesetting area, and the area utilization rate of the wafer during chip typesetting is further improved.
Drawings
Fig. 1 is a flowchart of a chip typesetting method according to an embodiment of the present application;
FIG. 2 is a diagram illustrating a chip layout according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another chip layout provided in the embodiments of the present application;
fig. 4 is a schematic diagram of a specific application scenario provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a chip composition device according to an embodiment of the present application.
Detailed Description
As described in the background art, the conventional chip typesetting mode depends on manual experience, and the typesetting efficiency is very low. In addition, when the chip typesetting is carried out manually, the area utilization rate of the wafer is low.
According to the method and the device, the placing sequence is changed, the placing chips are placed according to different placing sequences to obtain different placing results, the placing positions of the chips in the different placing results are different, the area utilization rates of the type-setting areas corresponding to the different placing results are different, the placing result with the largest area utilization rate can be selected from the different placing results, and the placing position of the chip with the highest wafer area utilization rate is obtained, so that the type-setting efficiency is greatly improved, and the labor cost is saved; in addition, the area utilization rate of the wafer during chip typesetting can be improved; thereby avoiding the waste of wafer materials and reducing the production cost.
Furthermore, in the method, a plurality of first renewable distances are calculated in the first direction, a second renewable distance is calculated at a position corresponding to each renewable distance, and the maximum value of the second renewable distance is selected to place the chips to be laid out, so that the chips to be laid out can fully utilize the area in the layout area, and the area utilization rate of the wafer during chip layout is further improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below.
Fig. 1 is a flowchart of a chip layout method according to an embodiment of the present application.
The chip typesetting method in the embodiment of the application can be used in terminal equipment, that is, the terminal equipment can execute the steps of the method, and a chip or a chip module in the terminal equipment can execute the steps of the method. The terminal device may be a mobile phone, a computer, a tablet computer, or the like.
Specifically, the chip typesetting method may include the steps of:
step 101: obtaining a typesetting area for typesetting in a wafer and the sizes of a plurality of chips to be laid out;
step 102: changing the placing sequence of the plurality of chips to be placed, and performing multiple placement on the plurality of chips to be placed in the composition area based on the sizes of the plurality of chips to be placed to obtain a plurality of placement results, wherein each placement result comprises the placing positions of the plurality of chips to be placed in the composition area;
step 103: and acquiring the area utilization rate of the typesetting area corresponding to each layout result, and determining the final layout result based on the area utilization rate so as to obtain the final placing position of the chip to be laid in the typesetting area.
It should be noted that the sequence numbers of the steps in this embodiment do not represent a limitation on the execution sequence of the steps.
It is understood that in the specific implementation, the chip typesetting method may be implemented by using a software program running in a processor integrated within a chip or a chip module. The method may also be implemented by combining software and hardware, and the present application is not limited thereto.
In the specific implementation of step 101, the size of the layout area and the size of the chip to be laid out may be preset. The layout area may be an area in the wafer for laying out chips. The layout region may be a regular shape or an irregular shape. Accordingly, the shape of the chip to be laid out may also be a regular shape, or an irregular shape. For example, the regular shape may be a triangle, a quadrangle, a pentagon, a circle, and the like.
The following embodiments all take the layout area and the shape of the chip to be laid out as a quadrilateral as an example, but do not represent a limitation to the present application.
In the specific implementation of step 102, the placing order of the chips to be laid out is changed, and the chips are laid out for multiple times. That is, the placing order adopted each time the chip to be placed is different. The placing sequence of the chips represents the sequence adopted in chip layout. The layout results obtained by arranging the chips in different placing sequences are different, that is, the placing positions of the chips to be arranged in the typesetting area can be different, so that the area utilization rates of the typesetting areas corresponding to the layout results are different.
In a specific embodiment, when the plurality of chips to be placed are placed according to each placing order, a layout idea of a box algorithm (also referred to as a Bottom-left algorithm) may be used for reference. The boxing algorithm is applied to chip layout, each chip to be laid out can be initially placed at the upper right corner of the typesetting area, the maximum distance that the chip to be laid out can move downwards is calculated firstly, and after the chip to be laid out is moved downwards by the maximum distance, whether the chip to be laid out can move to the left at the current position is checked. And if so, calculating the maximum distance that the chip to be distributed can move leftwards, and moving the chip to be distributed leftwards by the maximum distance. Checking whether the chip to be laid out can move downwards at the current position, and if so, continuing to move downwards; the above steps are repeated until the chip to be distributed can not move downwards and leftwards any more, and the placement of the chip to be distributed is finished; when all the chips to be laid out are laid out according to the method, one-time layout is finished.
Therefore, in the specific implementation of step 103, the area utilization rate of the layout region corresponding to each layout result is obtained through calculation, and the final layout result is determined based on the area utilization rate. And arranging the chips to be arranged according to the final placement position in the final arrangement result, so that the maximum utilization rate of the wafer area can be realized.
Take the example that the chip to be laid out includes chip 1-chip 5. The placing sequence 1 is as follows: chip 1, chip 2, chip 3, chip 4 and chip 5; the placing sequence 2 is as follows: chip 1, chip 4, chip 2, chip 3 and chip 5. The layout result 1 of the chips arranged in the placement order 1 is shown in fig. 2, and the layout result 2 of the chips arranged in the placement order 2 is shown in fig. 3.
With reference to fig. 2 and fig. 3, when the chips are laid out according to the placement order 1, the placement positions of the chip 1, the chip 2, the chip 3, and the chip 4 in the layout area 100 of the wafer are as shown in fig. 2. Wherein the chip 4 is placed on the chip 3. Then, the chip 5 cannot be placed in the upper right corner of the current layout area, and the placement of the chip 5 cannot be completed. Only four chips 1-4 can be placed in the typesetting area. When the chips are arranged according to the arrangement sequence 2, five chips 1 to 5 can be arranged in the typesetting area. The area utilization rate of the typesetting area corresponding to the layout result 2 is greater than that of the typesetting area corresponding to the layout result 1. Therefore, the layout result 2 is selected as the final layout result.
According to the technical scheme, the placing positions of the chips to be placed are optimized, so that more chips to be placed are placed in the same type-setting area, and the effect of improving the area utilization rate of the wafer when the chips are placed is achieved.
In a specific implementation, the placing order of the plurality of chips to be laid out may be changed for a plurality of times, and the step of laying out the plurality of chips to be laid out in the layout area for one time may be continuously performed according to the plurality of changed placing orders, so as to obtain a plurality of laying out results.
In another embodiment, a plurality of chips to be placed may be placed at a time as follows: based on the size of each chip to be distributed, determining the distribution result of a plurality of chips to be distributed by moving the chip to be distributed by a first renewable distance and a second renewable distance and determining the placing position of the chip to be distributed; the first renewable distance is the renewable distance of the chip to be laid out in the typesetting area along the first direction; the second renewable distance is the renewable distance of the chip to be laid out in the typesetting area along the second direction, and the first direction and the second direction are the renewable directions of the position of the chip to be laid out in the typesetting area relative to the initial position.
In specific implementation, if the initial position is the upper right corner of the layout area, one of the first direction and the second direction is left, and the other direction is down; if the initial position is the lower right corner of the typesetting area, one direction of the first direction and the second direction is left, and the other direction is up; if the initial position is the upper left corner of the typesetting area, one of the first direction and the second direction is right, and the other direction is down; if the initial position is the lower left corner of the layout area, one of the first direction and the second direction is right, and the other direction is up.
In specific implementation, the position of the chip to be laid out in the layout area is the position of at least one vertex of the chip to be laid out in the layout area. That is, in the case where the size of the chip is known, the position of the chip is characterized by the position of the vertex of the chip.
Further, for each selected chip to be distributed, determining an initial position of the chip to be distributed in the typesetting area according to the size of the chip to be distributed, calculating a plurality of first renewable distances from the initial position according to the step length, calculating a second renewable distance at a position corresponding to each first renewable distance, and updating along a second direction at a position corresponding to the maximum value of the second renewable distance to obtain a final position of the chip to be distributed, thereby obtaining a primary distribution result; wherein the update distance is a maximum value of the second updatable distance.
With reference to fig. 4, the step of one layout will be described in detail with the chip to be laid out as the chip 4. In this embodiment, the initial position is the upper right corner of the layout area, the first direction is left, and the second direction is down.
The position of the chip is represented by the lower left vertex position of the chip. The initial position of the chip 4 is a position P1. And moving the chip 4 leftwards according to the step length to obtain a plurality of positions P2, …, pn, wherein each position corresponds to a first renewable distance. A second updatable distance for the chip 4 to move down is calculated at each position. As shown in fig. 4, at position P2, the second renewable distance of the chip 4 is d1; at position Pn, the second updatable distance of chip 4 is d2. After comparison, d2 is the maximum value of all the second renewable distances, and therefore, the chip 4 is moved to the left to the position Pn and then moved downwards by the distance d2, and the final placement position of the chip 4 is obtained as the position F.
Further, after the chip 4 is moved to the position F, the chip 5 may be continuously laid out, thereby obtaining a layout result as shown in fig. 3.
By adopting the chip layout mode of the embodiment of the application, the layout result of the chip can be optimized without changing the placing sequence of the chip. That is to say, compared with the boxing algorithm in the prior art, the layout of a larger number of chips can be realized in the same typesetting area, so that the area utilization rate of the wafer is increased. Furthermore, the chip layout method in the embodiment of the present application combines with changing the placement sequence for multiple layouts, so that a layout result meeting requirements can be obtained more quickly, a better layout result can be obtained, and the area utilization rate of the wafer is further improved.
In a combination mode, acquiring the area utilization rate of a primary layout result; if the area utilization rate does not reach the preset threshold, changing the placing sequence of the chips to be distributed, and continuing to perform the step of distributing the chips to be distributed in the typesetting area for one time until the area utilization rate with the distribution result reaches the preset threshold.
Specifically, the area utilization ratio may be a ratio of an area occupied by the chip to be laid out in the layout area to an area of the layout area. The area utilization rate can be an index for measuring the quality of the layout result, and the higher the area utilization rate is, the better the layout result is.
In this embodiment, the requirement of the chip layout, that is, the preset threshold of the area utilization rate, may be preset. Each time the layout is completed, the layout result of the layout can be verified, namely whether the area utilization rate of the layout result reaches a preset threshold or not is judged; if the area utilization rate of the layout result does not reach the preset threshold, changing the placing sequence of the chips to be laid out, and continuing to perform the step of laying out the chips to be laid out in the typesetting area once. And if the area utilization rate of the layout result reaches a preset threshold, stopping the layout step, and taking the layout result as a final layout result.
It should be noted that the preset threshold may be any implementable value such as 85% or 90%, and may be adaptively set according to an actual application scenario, which is not limited in this application.
In another combination mode, the placing order of the chips to be laid out can be changed for multiple times, and the step of laying out the chips to be laid out in the typesetting area for one time is continuously executed according to the changed placing orders, so that multiple laying-out results are obtained.
In this embodiment, the number of times of layout of the chip layout may be preset. Firstly, the placing sequence of the chips to be distributed with the quantity of the times is obtained, then the chips are distributed in sequence, and a plurality of times of distribution results are obtained. And selecting a final layout result according to the area utilization rate in the multiple layout results.
In the step of one layout, if the number of the first updating positions where the maximum value of the second updatable distances is located is multiple, the second updating position which is farthest from the initial position is selected, and the placing position of the chip to be laid out is updated along the second direction at the second updating position.
The farthest distance from the initial position in this embodiment may refer to the farthest distance from the initial position in the first direction.
With continued reference to FIG. 4, at both position Pn and position Pm, the second updatable distance of the chip 4 is a maximum value d2. And selecting the position Pn as a second updating position if the position Pn is farther from the initial position P1 than the position Pm. Therefore, the chip 4 is moved to the left to the position Pn and then moved down by the distance d2, and the final placement position of the chip 4 is obtained as the position F.
According to the method for selecting the second updating position, the chip can be ensured to fully fill the typesetting area when the chip is typeset, and the waste of the area in the typesetting area is avoided.
Further, when the placing position of the chip to be placed is updated at the second updating position along the second direction, the distance between the second updating position and the third updating position along the first direction is judged, and if the distance is greater than or equal to the width of the chip to be placed along the first direction, the placing position of the chip to be placed is updated at the second updating position along the second direction; and the third updating position is the updating position which is closest to the initial position in the plurality of first updating positions.
In the embodiment, by comparing the distance between the second update position and the third update position along the first direction with the width of the chip to be placed along the first direction, the relationship between the width of the maximum value of the second updatable distance and the width of the chip to be placed can be obtained, that is, whether the chip to be placed can be moved at the second update position is obtained, so that the correct placement of the chip is ensured.
With continued reference to FIG. 4, at both position Pn and position Pm, the second updatable distance of the chip 4 is a maximum value d2. The position Pm is a third update position closest to the initial position, and the position Pn is a second update position. The widths of the position Pm and the position Pn are larger than the width of the chip 4, so that the chip 4 can be moved downwards at the position Pn by a distance d2, and the final placement position of the chip 4 is obtained as a position F.
Conversely, if the widths of the position Pm and the position Pn are smaller than the width of the chip 4, it means that the chip 4 cannot be moved downward at the position Pn, and the placement of the chip 4 cannot be completed at this time.
The applicant compares the final layout result obtained by the scheme of the application with the layout result obtained by the traditional Bottom-left algorithm, and for the same group of chips to be laid out, the area utilization rate corresponding to the final layout result in the application is 2-7 percentage points higher than that corresponding to the traditional layout result.
Compared with the chip typesetting mode mainly based on horizontal movement in the prior art, the chip typesetting method and the chip typesetting device have the advantages that the chip is subjected to layout in combination with the size and the moving direction of the chip to be laid out during the chip typesetting, and the layout efficiency and the wafer area utilization rate are greatly improved compared with those of the prior art. The chip typesetting mode breaks through the thinking dilemma of chip typesetting in the prior art, and the new chip typesetting mode is not simple change which can be obtained by carrying out multiple experiments on the prior art.
Referring to fig. 5, the embodiment of the present application further discloses a chip typesetting apparatus 50. The chip composition apparatus 50 may include:
an obtaining module 501, configured to obtain a layout area for layout in a wafer and sizes of a plurality of chips to be laid out;
a layout module 502, configured to change a placement order of a plurality of chips to be laid out, and perform multiple layouts on the plurality of chips to be laid out in a layout area based on sizes of the plurality of chips to be laid out, so as to obtain a plurality of layout results, where each layout result includes a placement position of the plurality of chips to be laid out in the layout area;
the layout result determining module 503 is configured to obtain an area utilization rate of the layout area corresponding to each layout result, and determine a final layout result based on the area utilization rate, so as to obtain a final placement position of the chip to be laid out in the layout area.
In one non-limiting embodiment, the layout module 502 includes: the direction setting unit is used for presetting a first direction and a second direction for moving the chip to be laid out in the typesetting area; and the layout unit is used for determining the layout results of the plurality of chips to be laid out by moving the first renewable distance and the second renewable distance to the chips to be laid out and determining the placing positions of the chips to be laid out based on the size of each chip to be laid out.
Further, the layout unit determines an initial position of the chip to be laid out in the layout area according to the size of the chip to be laid out for each selected chip to be laid out, calculates a plurality of first renewable distances according to the step length from the initial position, calculates a second renewable distance at a position corresponding to each first renewable distance, and updates along a second direction at a position corresponding to the maximum value of the second renewable distance to obtain a final position of the chip to be laid out, so as to obtain a primary layout result.
Further, if the number of the first update positions where the maximum value of the second updatable distances is located is multiple, the layout unit selects a second update position farthest from the initial position, and updates the placement position of the chip to be laid out along the second direction at the second update position.
Further, the layout unit determines a distance between the second update position and the third update position along the first direction, and updates the placement position of the chip to be laid out along the second direction at the second update position if the distance is greater than or equal to the width of the chip to be laid out along the first direction.
Further, the layout module 502 further includes: the calculation unit is used for acquiring the area utilization rate of the primary layout result; and the circulating unit is used for changing the placing sequence of the chips to be distributed when the area utilization rate does not reach the preset threshold, and continuing to perform the step of distributing the chips to be distributed in the typesetting area for one time until the area utilization rate with the distribution result reaches the preset threshold.
For more details of the working principle and the working mode of the chip typesetting apparatus 50, reference may be made to fig. 1 to 4 and the related description of the corresponding embodiments, which are not repeated herein.
In a specific implementation, the Chip typesetting device may correspond to a Chip having a Chip typesetting function in the terminal device, such as a System-On-a-Chip (SOC), a baseband Chip, and the like; or the terminal equipment comprises a chip module with a chip typesetting function; or to a chip module having a chip with a data processing function, or to a terminal device.
Each module/unit included in each apparatus and product described in the above embodiments may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device and product applied to or integrated with the chip module, each module/unit included in the device and product may be implemented by hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least part of the modules/units may be implemented by a software program running on a processor integrated inside the chip module, and the rest (if any) part of the modules/units may be implemented by hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by hardware such as a circuit, different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by hardware such as a circuit.
The embodiment of the present application further discloses a storage medium, which is a computer readable storage medium, on which a computer program is stored, and when the computer program runs, the steps of the foregoing method may be executed. The storage medium may include ROM, RAM, magnetic or optical disks, etc. The storage medium may further include a non-volatile (non-volatile) memory or a non-transient (non-transient) memory, etc.
The embodiment of the application also discloses a terminal device, which can comprise a memory and a processor, wherein the memory is stored with a computer program capable of running on the processor. The processor, when executing the computer program, may perform the steps of the method as described above. The terminal device includes, but is not limited to, a mobile phone, a computer, a tablet computer, and other terminal devices.
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship.
The "plurality" appearing in the embodiments of the present application means two or more.
The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.
The term "connection" in the embodiment of the present application refers to various connection manners such as direct connection or indirect connection, so as to implement communication between devices, which is not limited in this embodiment of the present application.
It should be understood that, in the embodiment of the present application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will also be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory. Volatile memory may be Random Access Memory (RAM) which acts as external cache memory. By way of example and not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (enhanced SDRAM), synchronous DRAM (SLDRAM), synchronous Link DRAM (SLDRAM), and direct bus RAM (DR RAM).
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. The procedures or functions according to the embodiments of the present application are wholly or partially generated when the computer instructions or the computer program are loaded or executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods described in the embodiments of the present application.
Although the present application is disclosed above, the present application is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and it is intended that the scope of the present disclosure be defined by the appended claims.
Claims (14)
1. A method of chip layout, comprising:
obtaining a typesetting area for typesetting in a wafer and the sizes of a plurality of chips to be distributed;
changing the placing sequence of the plurality of chips to be placed, and placing the plurality of chips to be placed in the composition area for a plurality of times based on the sizes of the plurality of chips to be placed to obtain a plurality of placing results, wherein each placing result comprises the placing positions of the plurality of chips to be placed in the composition area;
and acquiring the area utilization rate of the typesetting area corresponding to each layout result, and determining the final layout result based on the area utilization rate so as to obtain the final placing position of the chip to be laid in the typesetting area.
2. The chip layout method according to claim 1, wherein the step of laying out the plurality of chips to be laid out in the layout area at a time comprises:
presetting a first direction and a second direction for moving a chip to be laid out in a typesetting area;
based on the size of each chip to be distributed, determining the distribution result of the plurality of chips to be distributed by moving the chip to be distributed by a first renewable distance and a second renewable distance and determining the placing position of the chip to be distributed;
the first renewable distance is the renewable distance of the chip to be laid out in the typesetting area along the first direction; the second updatable distance is an updatable distance of the chip to be laid out in the layout area along a second direction, the first direction and the second direction are updatable directions of the position of the chip to be laid out in the layout area relative to an initial position, and the initial position is a preset position in the layout area.
3. The chip composition method according to claim 2, wherein the step of determining the placement position of the chip to be laid out by moving the chip to be laid out by the first renewable distance and the second renewable distance based on the size of each chip to be laid out comprises:
for each selected chip to be distributed, determining the initial position of the chip to be distributed in the typesetting area according to the size of the chip to be distributed;
calculating a plurality of first renewable distances according to step length from the initial position, calculating a second renewable distance at a position corresponding to each first renewable distance, and updating along the second direction at a position corresponding to the first renewable distance corresponding to the maximum value of the second renewable distance to obtain a final position of the chip to be laid out, so as to obtain a primary layout result;
wherein the update distance is a maximum value of the second updatable distance.
4. The chip typesetting method according to claim 3, further comprising:
obtaining the area utilization rate of the primary layout result;
if the area utilization rate does not reach the preset threshold, changing the placing sequence of the plurality of chips to be placed, and continuing to execute the step of placing the plurality of chips to be placed in the type setting area for one time until the area utilization rate with the placing result reaches the preset threshold.
5. The chip layout method according to claim 3, wherein if there are a plurality of first update positions where the maximum value of the second updatable distance is located, selecting a second update position farthest from the initial position, and updating the placement position of the chip to be laid out at the second update position along the second direction, where the first update position corresponds to the maximum value of the second updatable distance, and the second update position represents a first update position farthest from the initial position among the plurality of first update positions.
6. The method for chip typesetting according to claim 5, wherein the updating the placement position of the chip to be laid out along the second direction at the second updating position comprises:
judging the distance between the second updating position and a third updating position along the first direction, and if the distance is greater than or equal to the width of the chip to be laid out along the first direction, updating the placing position of the chip to be laid out along the second direction at the second updating position;
and the third updating position is the updating position which is closest to the initial position in the plurality of first updating positions.
7. The chip layout method according to claim 2, wherein the step of changing the placement order of the plurality of chips to be laid out and laying out the plurality of chips to be laid out in the layout area a plurality of times based on the sizes of the plurality of chips to be laid out includes:
and changing the placing sequence of the chips to be laid out for multiple times, and continuing to perform the step of laying out the chips to be laid out in the typesetting area for one time according to the changed placing sequences to obtain a plurality of layout results.
8. The chip typesetting method according to any one of claims 1-7, wherein the step of obtaining the area utilization ratio of the typesetting area corresponding to each layout result and determining the final layout result based on the area utilization ratio comprises:
calculating the occupied area of each chip to be laid out when the chip is laid out according to the placement position in each layout result, and the ratio of the area to the area of the layout area to be used as the area utilization rate;
and selecting the layout result corresponding to the maximum area utilization rate as the final layout result.
9. The chip layout method according to any one of claims 2 to 7, wherein if the initial position is the upper right corner of the layout area, one of the first direction and the second direction is left, and the other direction is down; if the initial position is the lower right corner of the typesetting area, one of the first direction and the second direction is left, and the other direction is up; if the initial position is the upper left corner of the typesetting area, one of the first direction and the second direction is right, and the other direction is down; and if the initial position is the lower left corner of the typesetting area, one of the first direction and the second direction is right, and the other direction is up.
10. The chip layout method according to any one of claims 1 to 7, wherein the position of the chip to be laid out is a position of at least one vertex of the chip to be laid out within the layout area.
11. The method for chip typesetting according to any one of claims 1 to 7, wherein the typesetting area is quadrilateral, and the shape of the chip is quadrilateral.
12. A chip composing device, comprising:
the obtaining module is used for obtaining a typesetting area for typesetting in the wafer and the sizes of a plurality of chips to be laid out;
the layout module is used for changing the placing sequence of the chips to be laid out, and carrying out multiple layouts on the chips to be laid out in the layout area based on the sizes of the chips to be laid out to obtain multiple layout results, wherein each layout result comprises the placing positions of the chips to be laid out in the layout area;
and the layout result determining module is used for obtaining the area utilization rate of the layout area corresponding to each layout result and determining the final layout result based on the area utilization rate so as to obtain the final placement position of the chip to be laid in the layout area.
13. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a computer, performs the steps of the chip composition method according to any one of claims 1 to 11.
14. A terminal device comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor executes the computer program to perform the steps of the chip composition method according to any one of claims 1 to 11.
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