CN115509093A

CN115509093A - Method for setting alignment mark

Info

Publication number: CN115509093A
Application number: CN202211196891.3A
Authority: CN
Inventors: 李峰; 居碧玉; 陈辉; 刘伟林; 许文霞; 岳鹏
Original assignee: Hua Hong Semiconductor Wuxi Co Ltd
Current assignee: Hua Hong Semiconductor Wuxi Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2022-12-23

Abstract

The application discloses a setting method of an alignment mark, which comprises the following steps: obtaining the key size of a target graph in a layout, wherein the layout is applied to the manufacturing process of a target device, and the target graph is the graph of the target device at the current level; taking the key size of the target graph as the key size of an alignment mark, and inserting the alignment mark into a target area in the layout; and operating the target device by inserting the layout of the alignment mark. According to the method, the key size of the graph of the target device at the level in the layout is obtained, the key size is used as the key size of the alignment mark, and the alignment mark is inserted into the target area, so that the target device is operated according to the layout.

Description

Method for setting alignment mark

Technical Field

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a setting method of an alignment mark.

Background

In the semiconductor integrated circuit manufacturing industry, it is necessary to align the pattern of the layer with the pattern of the preceding layer, i.e., to perform photolithography alignment before photolithography exposure, and the purpose of this is to overlay the image on the mask plate on the pattern formed on the wafer with maximum accuracy.

In view of this, in the related art, in order to assist the interlayer alignment of the semiconductor device, an alignment mark (alignment mark) is usually formed on the pattern layer, so that the subsequent pattern layer ensures the alignment overlay of the pattern layer according to the alignment mark of the layer. Hereinafter, a description will be given by taking a lithography apparatus of ASML (advanced semiconductor material technology, ASML) corporation, the netherlands as an example.

In the manufacturing process of semiconductor products, after an ASML standard alignment mark (standard alignment mark) is formed, the shape of the ASML standard alignment mark is affected by different devices in subsequent manufacturing processes (e.g., chemical Vapor Deposition (CVD) process, etching (etch) process, etc.), so that the alignment of the lithography equipment is affected, the overlay error (overlay) difference of different regions of the wafer is large, and the yield of the products is reduced.

Disclosure of Invention

The application provides a setting method of an alignment mark, which can solve the problem that the alignment mark provided in the related technology is easily influenced by the subsequent preparation process, so that the alignment error is larger, and the method comprises the following steps:

obtaining the key size of a target graph in a layout, wherein the layout is applied to the manufacturing process of a target device, and the target graph is the graph of the target device at the current level;

taking the key size of the target graph as the key size of an alignment mark, and inserting the alignment mark into a target area in the layout;

and operating the target device by inserting the layout of the alignment mark.

In some embodiments, the target device comprises a power device.

In some embodiments, the target area is an area where a scribe-lane pattern is located.

In some embodiments, during the operation of the target device through the layout into which the alignment mark is inserted, the overlay error of the current level is determined by measuring the topography of the target device.

In some embodiments, during the operation of the target device by inserting the layout of the alignment mark, a CVD process and/or an etching process is performed after the alignment mark is formed.

In some embodiments, the layout is a layout applied to a lithographic apparatus of ASML corporation.

The technical scheme at least comprises the following advantages:

the key size of the graph of the target device at the level in the layout is obtained, the key size is used as the key size of the alignment mark, and the alignment mark is inserted into the target area, so that the target device is operated according to the layout.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flowchart of a setting method of an alignment mark according to an exemplary embodiment of the present application.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

According to the standard of ASML photoetching equipment, in the setting process of a layout, the standard key size of an alignment mark is divided according to an equal division method to obtain the required alignment mark. For example, if the standard critical dimension is 8 micrometers (μm), the alignment mark may be disposed by dividing the width occupied by the standard critical dimension into three width regions of 2.6 micrometers, 2.8 micrometers and 2.6 micrometers. The standard critical dimension is divided to set the alignment mark, which does not consider the critical dimension of the device, thereby causing the subsequent overlay error problem.

Referring to fig. 1, which shows a flowchart of a setting method of an alignment mark according to an exemplary embodiment of the present application, as shown in fig. 1, the method includes:

s1, obtaining the key size of a target graph in a layout, wherein the layout is applied to the manufacturing process of a target device, and the target graph is the graph of the target device at the current level.

Wherein the layout is a layout applied to a lithographic apparatus of ASML corporation. For example, the layout is applied to the manufacturing process of the power device, and the layout is a layout corresponding to the gate sidewall of the power device, so that in this step, the target pattern is a pattern corresponding to the gate sidewall, and the key size of the pattern corresponding to the gate sidewall can be obtained.

And S2, taking the key size of the target graph as the key size of the alignment mark, and inserting the alignment mark into a target area in the layout.

For example, the target region may be a region where a scribe-lane pattern is located in the layout, and after obtaining a critical dimension of the target pattern, the critical dimension of the target pattern is used as a critical dimension of the alignment mark (for example, the target pattern is a pattern corresponding to a gate sidewall, and the critical dimension of the target pattern is 1 micron, and the critical dimension of the alignment mark is determined to be 1 micron), and the alignment mark is inserted into the region where the scribe-lane pattern is located.

And S3, operating the target device through the layout of the inserted alignment mark.

The target device can be operated by inserting the layout of the alignment mark, and the overlay error of the layer can be judged by measuring the appearance of the target device in the operation process. Wherein, in the operation process, after the alignment mark is formed, a CVD process and/or an etching process are required to be carried out. For example, after the layout is subjected to photoetching and etching, an alignment mark is formed, a subsequent level photoetching process can be carried out through the alignment mark, after the alignment mark is formed, the subsequent process also comprises a CVD (chemical vapor deposition) process and an etching process, and as the key size of the alignment mark is the same as that of a target pattern, the alignment mark is operated under the same preparation process, so that the stability and the anti-noise capability of the alignment mark can be improved, and the alignment mark is more accurate.

In summary, in the embodiment of the present application, the key size of the graph of the target device at this level in the layout is obtained, the key size is used as the key size of the alignment mark, and the alignment mark is inserted into the target region, so that the target device is operated according to the layout.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A method of setting an alignment mark, comprising:

and operating the target device by inserting the layout of the alignment mark.

2. The method of claim 1, wherein the target device comprises a power device.

3. The method of claim 2, wherein the target area is an area where a scribe-lane pattern is located.

4. A method according to any one of claims 1 to 3, wherein during operation of the target device by inserting the layout of the alignment marks, the overlay error at the current level is determined by measuring the topography of the target device.

5. The method according to claim 4, wherein during the operation of the target device by inserting the layout of the alignment mark, a CVD process and/or an etching process is further performed after the formation of the alignment mark.

6. The method according to claim 5, wherein the layout is a layout applied to a lithographic apparatus of ASML corporation.