CN115508692A

CN115508692A - Testability circuit of integrated circuit chip

Info

Publication number: CN115508692A
Application number: CN202211246802.1A
Authority: CN
Inventors: 卢君明; 许程凯
Original assignee: Shanghai Kingchip Electronics Technology Co ltd
Current assignee: Shanghai Kingchip Electronics Technology Co ltd
Priority date: 2022-10-12
Filing date: 2022-10-12
Publication date: 2022-12-23

Abstract

The invention discloses a testability circuit of an integrated circuit chip, which belongs to the field of integrated circuits and comprises a counting and setting device, a signal multiplexer, a signal latch and an output multiplexer. By using the time division multiplexing method, the observation of important analog-digital interface signals and digital signals in a digital-analog mixed chip is realized, and the chip plays an important role in the application development process, particularly in the design and debugging process of application software developed by an MCU chip application engineer.

Description

Testability circuit of integrated circuit chip

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a testability circuit of an integrated circuit chip.

Background

With the development of integrated circuit technology, the scale of functions and devices of the integrated circuit rapidly expands, the circuit structure becomes more and more complex, and the testing and debugging of the chip become more and more difficult. The complexity of the function causes the test fee to be used in the cost constitution of the product and becomes an important component, and the test time directly influences the time for the product to appear on the market and further influences the economic benefit. One of the most efficient methods to control the cost of testing currently employs design for test (DFT) techniques in chip design. The circuit design engineer must consider the test requirement while designing the system and the circuit, and the standard of a circuit is measured by considering not only the performance quality and the number of devices, but also the testability, whether the test is convenient, whether the test code is easy to generate and the like, which is the testability design of the integrated circuit.

Testability design has been widely used in digital circuits, and EDA tools assist designers in automatic design, such as DFT compiler of Synopsys, to realize testability design conveniently. However, for digital-analog mixed interface signals or internal signals which need to be tested and observed in a normal working mode, a standard testability design method does not exist in the existing EDA tool at present.

In addition, the testability design realized by the EDA tool is mainly applied to testing chip products in the production test process, and the chip is not a good solution for observing internal key signals in the application development process, especially in the MCU chip design debugging process of application engineers developing application software.

Disclosure of Invention

The present invention is directed to a testability circuit of an integrated circuit chip to solve the above problems.

In order to achieve the purpose, the invention provides the following technical scheme:

a testability circuit of an integrated circuit chip comprises a counting and setting device, a signal multiplexer, a signal latch and an output multiplexer,

the counting and setting device is connected with the signal multiplexer and is used for selecting the appointed input signal of the signal multiplexer;

the signal multiplexer is used for selecting a signal to be observed according to a selection signal output by the counting and setting device and sending the signal to the signal latch and the output multiplexer;

the signal latch is used for latching the observation signal selected by the signal multiplexer and sending the observation signal to the output multiplexer;

the output multiplexer is connected with two selection signals SEL0 and SEL1, and the signals output by the selection signal multiplexer are directly output or output after latching or output signals under a normal mode are selected through the two selection signals SEL0 and SEL 1;

as a further technical scheme of the invention: the count and setting unit latches a designated selection signal or counts from 0 to a maximum count value to obtain a selection signal according to a count enable signal and a set enable signal.

As a further technical scheme of the invention: and the output end of the output multiplexer is also connected with the digital output module.

As a further technical scheme of the invention: and the digital output module processes the signal selected by the output multiplexer and outputs the processed signal to the PAD port.

As a further technical scheme of the invention: the counter and setter is connected with a signal set _ en and a signal cnt _ en, and the set _ en is a set function when the signal set _ en is 1, and at this time, regardless of the value of the signal cnt _ en, it sets the input 7-bit signal a [6 ] = a [6 ].

As a further technical scheme of the invention: when the signal cnt _ en is 1, the counting and setting device performs a continuous counting function between 0 and the maximum counting value, and performs a wrap-around operation after counting to the maximum value, that is, performs a counting function between 0 and the maximum counting value continuously.

As a further technical scheme of the invention: the digital output module is an output IO module.

Compared with the prior art, the invention has the beneficial effects that:

the testability circuit for the digital-analog hybrid chip can conveniently and quickly observe the digital-analog hybrid interface signals in the chip and provide real-time monitoring for the internal signals of the chip in a normal working mode. By using the time division multiplexing method, the observation of important analog-digital interface signals and digital signals in a digital-analog mixed chip is realized, and the chip plays an important role in the application development process, particularly in the design and debugging process of application software developed by an MCU chip application engineer.

Drawings

Fig. 1 is a block diagram of the circuit configuration of the present invention.

Fig. 2 is a waveform diagram of a different configuration of the present invention.

Fig. 3 is an enlarged view of a first portion of the waveform of fig. 2.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Embodiment 1, as shown in fig. 1-3, a testability circuit for an integrated circuit chip, comprising: a count and set, signal multiplexer, signal latch (REG in fig. 1) and output multiplexer;

the count and setter latches a designated selection signal or counts from 0 to a maximum count value to obtain a selection signal according to a count enable signal and a set enable signal. For selecting a given input signal of the signal multiplexer.

The signal multiplexer is used for selecting the signal to be observed according to the selection signal output by the counting and setting device and sending the signal to the signal latch and the output multiplexer.

The signal latch is used for latching the observation signal selected by the signal multiplexer and sending the observation signal to the output multiplexer.

The output multiplexer can select the signal output by the signal multiplexer to be directly output or output after latching through two selection signals of SEL0 and SEL1, and can also select the output signal in a normal mode.

And the digital output module processes the signal selected by the output multiplexer and outputs the processed signal to the PAD port.

Embodiment 2, based on embodiment 1, the digital output module may be a standard output IO module.

The working principle is as follows:

the counting and setting device can realize the functions of setting and counting. A set function is shown in fig. 1 when set _ en is 1, and this sets the input 7-bit signal a [6 ]. This function is used to directly select a signal for output observation.

When cnt _ en is 1 in fig. 1, the counting and setting unit performs a continuous counting function between 0 and the maximum count value, and performs a wrap-around operation after counting to the maximum value, that is, performs a counting function of 0 to the maximum count value continuously. This function is used to output all signals in sequential succession.

When both set _ en and cnt _ en are 0, the counter and setter keeps the previous bit position or count value unchanged.

The signal multiplexer is a module realized by a digital standard unit, and the output signal of the signal multiplexer is the selected observation signal D _ sel. A specific signal multiplexer, which can include 7 selection signals S0-S6, 128 internal signals; where the 7 select signals S0-S6 come from the output of the count and set device. And 128 internal signals are distributed as follows, the first 8 signals, namely D0-D7, are fixed to 10101010 (AA) and are start codes; the last 8 signals D120-D127, fixed as 11110000 (F0), are end codes; the middle 112 signals are the key signals of the internal circuit, such as the interface signals of the analog module and the digital module, the externally input PAD signal, the key signals of the internal digital signal, and the like, which need to be tested and observed. The purpose of the configuration is that when cnt _ en is 1, when all internal signals to be observed are sequentially and continuously output, a head code (AA) and a tail code (F0) of the signals are continuously output, and the time sequence position of the key signals is conveniently positioned.

The input of the signal latch is the observation signal D _ sel selected by the signal multiplexer, which can be implemented by a register, and the latched output is fed to the output multiplexer. The signal latch is used for carrying out signal sampling correction on the observation signal selected by the signal multiplexer once to obtain a latched signal D _ sel _ reg, so that the pulse widths of signals observed by the PAD port can be kept consistent, and a burr signal is prevented from being sent to the PAD port when the selection of the multi-path selection signal is switched.

The output multiplexer can select the signal output by the signal multiplexer to directly output D _ SEL or output D _ SEL _ reg after latching through two selection signals SEL0 and SEL1, and can also select the output signal Out _ signal in a normal mode.

The final output of the output multiplexer is shown in the table below in combination with the count and the control signal of the setter. In the table, x represents 0 and 1, namely, unrelated items.

Table 1: outputting a final output signal table of the multi-path selector;

where both set _ en and cnt _ en are 0, the output of the counter and setter remains unchanged, determined by the previous state value.

Through the output multiplexer, the signals to be detected or observed can be output through the PAD pins which are idle under normal functions, and the PAD resources increased due to testability requirements are reduced to the maximum extent.

And the digital output module processes the signal selected by the output multiplexer and outputs the processed signal to the PAD port. The module may be a standard output IO module.

Fig. 2 and 3 are two operational waveforms, respectively. In fig. 2, the first part is configured as 0110, all the internal signals to be observed are latched and output sequentially, D _ sel _ reg; the second part is configured to 1010, specify a latch output of the selection signal, D _ sel _ reg; the third part is configured as 1000, and the output signal configuration in the normal mode outputs Out _ signal.

FIG. 3 is an amplified waveform for the first portion of FIG. 2, and it can be seen that the PAD waveform follows the sequentially successive latched outputs D _ sel _ reg of the internal signal to be observed; the start code AA and end code F0 can be seen, as well as the intermediate signal output.

The testability circuit for the digital-analog hybrid chip can conveniently and quickly observe the digital-analog hybrid interface signals in the chip and provide internal signals of the chip under a real-time monitoring normal working mode. By using a time division multiplexing method, the observation of important analog-digital interface signals and digital signals in a digital-analog hybrid chip is realized, and the chip plays a very important role in the application development process, particularly in the process of designing and debugging the application software developed by an application engineer of an MCU chip.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Furthermore, it should be understood that although the present specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it is to be understood that all embodiments may be combined as appropriate by one of ordinary skill in the art to form other embodiments as will be apparent to those of skill in the art from the description herein.

Claims

1. A testability circuit for an integrated circuit chip comprising a count and set-up device, a signal multiplexer, a signal latch, and an output multiplexer,

the output multiplexer is connected with two selection signals SEL0 and SEL1, and the signals output by the selection signal multiplexer are directly output or output after latching or output signals under a normal mode are selected through the two selection signals SEL0 and SEL 1.

2. The integrated circuit chip testability circuit of claim 1, wherein the count and set unit latches the select signal or counts from 0 to a maximum count value to obtain the select signal based on a count enable signal and a set enable signal.

3. The integrated circuit chip testability circuit of claim 1, wherein the output of the output multiplexer is further coupled to a digital output module.

4. The integrated circuit chip testability circuit of claim 3, wherein the digital output module processes the signal selected by the output multiplexer and outputs the processed signal to the PAD port.

5. The testability circuit of an integrated circuit chip according to claim 1, wherein the count and set device is connected with a signal set _ en and a signal cnt _ en, and the signal set _ en is a set function when being 1, and when the signal cnt _ en is set to a value of the input 7-bit signal a [6 ] = a [6 ].

6. The circuit of claim 1, wherein the count and set unit performs a continuous count function between 0 and a maximum count value when the signal cnt _ en is 1, and performs a wrap-around operation after counting to the maximum value, i.e., performs the count function between 0 and the maximum count value continuously.

7. The integrated circuit chip testability circuit according to claim 4, wherein the digital output module is an output IO module.