CN115499036B - Parallel capturing method and storage medium for broadband spread spectrum signal - Google Patents

Parallel capturing method and storage medium for broadband spread spectrum signal Download PDF

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CN115499036B
CN115499036B CN202211417114.7A CN202211417114A CN115499036B CN 115499036 B CN115499036 B CN 115499036B CN 202211417114 A CN202211417114 A CN 202211417114A CN 115499036 B CN115499036 B CN 115499036B
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signal
code
speed
carrier
carrier doppler
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CN115499036A (en
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赵洪博
杨旭
冯文全
刘万兴
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Hefei Kongtian Xingyun Technology Co ltd
Hefei Innovation Research Institute of Beihang University
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Hefei Kongtian Xingyun Technology Co ltd
Hefei Innovation Research Institute of Beihang University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
    • G01S19/29—Acquisition or tracking or demodulation of signals transmitted by the system carrier including Doppler, related
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
    • G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/708—Parallel implementation

Abstract

The invention discloses a broadband spread spectrum signal parallel capturing method and a storage medium, wherein the method comprises the steps of obtaining a high-speed digital baseband coding signal after a radio frequency input signal is subjected to radio frequency front end, ADC sampling and coding, then obtaining a low-speed original bit expansion signal through local decoding deserializing and serial-parallel conversion, and generating a low-speed synchronous channel associated clock signal; multiplying the output carrier signal with fixed phase offset by the low-speed original bit-spread signal generated in the first step, and stripping the carrier Doppler in the original signal; carrying out partial matched filtering and coherent integration on the output pseudo code signal with fixed phase offset and the signal generated in the second step, and carrying out FFT operation on a coherent integration result; and performing peak detection on the FFT result of the third step. If the correct correlation peak is found, calculating the corresponding carrier Doppler and code phase; if no relevant peak is found, the carrier Doppler frequency point is switched, and the search is continued. The invention is simple to realize and has accurate capture result.

Description

Parallel capturing method and storage medium for broadband spread spectrum signal
Technical Field
The invention relates to the technical field of satellite communication, in particular to a broadband spread spectrum signal parallel acquisition method.
Background
The spread spectrum signal has the characteristics of good concealment and strong anti-interference performance, and is widely applied to various communication, navigation and data chain transmission systems. The pseudo code rate of common spread spectrum signals (such as Beidou and GPS) is not more than 10.23Mcps, the length of pseudo codes is not more than 1023, the spread spectrum gain is low, the signal bandwidth is narrow, and the anti-interference and confidentiality capabilities are limited. With the progress of the aircraft communication frequency band from the traditional L, S frequency band to higher Ku and Ka frequency bands, user channel resources are increasingly abundant, a broadband spread spectrum system with the bandwidth of hundreds of megahertz is gradually applied, the frequency spectrum of a broadband spread spectrum signal is more concealed and has higher confidentiality, stronger interference resistance and good application prospect.
An FPGA (Field Programmable Gate Array) is a Programmable digital device, and the basic structure of the FPGA comprises a Programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded special hard core and a bottom layer embedded functional unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, so that the FPGA can be widely applied to the fields of software radio, digital image processing, data centers, artificial intelligence acceleration and the like.
Disclosure of Invention
The present invention provides a method for acquiring wideband spread spectrum signals in parallel, which can solve at least one of the above problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
a parallel acquisition method of broadband spread spectrum signals comprises the following steps,
step (ii) of1. Radio frequency input signal
Figure 463280DEST_PATH_IMAGE001
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
Figure 260334DEST_PATH_IMAGE002
And Q branch signal
Figure 806853DEST_PATH_IMAGE003
Wherein k represents the kth clock cycle, and the high-speed digital baseband coded signal is converted into a low-speed original bit-spreading signal after being subjected to local decoding deserialization and serial-parallel conversion respectively
Figure 980346DEST_PATH_IMAGE004
And
Figure 991027DEST_PATH_IMAGE005
simultaneously generating a low-speed synchronous channel associated clock signal;
driving a plurality of local carrier Doppler generators by the low-speed synchronous associated clock signal generated in the first step, wherein the carrier signal output by each carrier Doppler generator
Figure 148863DEST_PATH_IMAGE006
And
Figure 244995DEST_PATH_IMAGE007
with fixed phase offset
Figure 691020DEST_PATH_IMAGE008
Wherein i represents the ith carrier Doppler generator, j represents the jth clock cycle, and the carrier Doppler frequency points are searched in a segmented manner under the control of a state machine; carrier signal output by each carrier Doppler generator
Figure 759470DEST_PATH_IMAGE006
And
Figure 898328DEST_PATH_IMAGE007
with the low-speed original bit-spread signal generated in the first step
Figure 481756DEST_PATH_IMAGE009
And
Figure 731472DEST_PATH_IMAGE010
multiplying to obtain multiplied signal
Figure 903696DEST_PATH_IMAGE011
And
Figure 213454DEST_PATH_IMAGE012
for stripping large carrier doppler in the original signal;
driving a plurality of local pseudo-code generators by the low-speed synchronous associated clock signal generated in the first step; local pseudo-code signal output by each pseudo-code generator
Figure 284179DEST_PATH_IMAGE013
With fixed phase offset
Figure 337585DEST_PATH_IMAGE014
Wherein i represents the ith pseudo-code generator, k represents the kth clock cycle, and the local pseudo-code Doppler frequency point is adjusted under the control of the state machine; local pseudo-code signal output by each pseudo-code generator
Figure 115048DEST_PATH_IMAGE013
With the signal generated in the second step
Figure 595708DEST_PATH_IMAGE011
And
Figure 888149DEST_PATH_IMAGE012
carrying out partial matched filtering and coherent integration, and carrying out FFT operation on a coherent integration result;
fourthly, noise floor statistics is carried out on signal segments with correlation peak values appearing in FFT results of the third step, if the correlation peak ratio statistical noise is larger than a Threshold value Threshold, a correct correlation peak is found, carrier Doppler and code phase corresponding to the found correlation peak are calculated at the moment, and the carrier Doppler and the code phase are output backwards and transmitted to a tracking circuit; if no correlation peak is found, the carrier Doppler frequency point is switched through the state machine, and the search is continued.
Further, the step one specifically comprises the following steps,
s11, original radio frequency input signal
Figure 745247DEST_PATH_IMAGE015
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
Figure 626484DEST_PATH_IMAGE016
And Q branch signal
Figure 278045DEST_PATH_IMAGE017
Of a signal
Figure 323362DEST_PATH_IMAGE016
Sum signal
Figure 656254DEST_PATH_IMAGE017
Are equal in code rate, are all
Figure 205047DEST_PATH_IMAGE018
；
S12, high-speed digital baseband coding signal
Figure 293089DEST_PATH_IMAGE016
And
Figure 747073DEST_PATH_IMAGE017
after being processed by local decoding deserializing and deserializing respectively, the signals are changed into low-speed original spread signals
Figure 680394DEST_PATH_IMAGE019
And
Figure 349272DEST_PATH_IMAGE020
simultaneously generating a low-speed synchronous channel clock signal having a frequency of
Figure 545899DEST_PATH_IMAGE021
，
Figure 34649DEST_PATH_IMAGE021
Size and high speed sampling clock
Figure 37240DEST_PATH_IMAGE022
Is related to the serial-to-parallel ratio N in the relationship of
Figure 560625DEST_PATH_IMAGE023
；
Wherein the content of the first and second substances,
Figure 903052DEST_PATH_IMAGE024
Figure 144677DEST_PATH_IMAGE025
wherein
Figure 685380DEST_PATH_IMAGE026
Is the original radio frequency signal of the input,
Figure 955DEST_PATH_IMAGE027
is Doppler frequency after zero intermediate frequency processing, and the sampling clock frequency of the high-speed digital baseband coding signal is
Figure 601700DEST_PATH_IMAGE022
；
Then
Figure 65043DEST_PATH_IMAGE028
Figure 596387DEST_PATH_IMAGE029
。
Figure 94365DEST_PATH_IMAGE019
Is a high-speed digital baseband coded signal
Figure 600432DEST_PATH_IMAGE016
The sampled vector after the low-speed extraction is performed,
Figure 754333DEST_PATH_IMAGE020
is a high-speed digital baseband coded signal
Figure 636838DEST_PATH_IMAGE017
Sampling vectors after low-speed extraction, wherein braces are used for representing vector intervals after sampling, and vector elements are represented in the braces.
Further, the second step specifically comprises the steps of,
s21, driving a plurality of local carrier Doppler generators by using the low-speed synchronous associated clock signal generated in the step S12, wherein the carrier signals output by the carrier Doppler generators have fixed phase deviation
Figure 989322DEST_PATH_IMAGE030
Of orthogonal signals
Figure 853242DEST_PATH_IMAGE031
And
Figure 291177DEST_PATH_IMAGE032
；
namely, the carrier amplitude of the ith carrier Doppler generator in the jth clock cycle is recorded as
Figure 977373DEST_PATH_IMAGE031
And
Figure 184363DEST_PATH_IMAGE032
i =1,2, …, N, then:
Figure 235496DEST_PATH_IMAGE033
Figure 160727DEST_PATH_IMAGE034
s22, carrier signals output by each carrier Doppler generator
Figure 385035DEST_PATH_IMAGE031
And
Figure 899061DEST_PATH_IMAGE032
and the low-speed original bit-spread signal generated in S12
Figure 183412DEST_PATH_IMAGE019
And
Figure 330360DEST_PATH_IMAGE020
multiplying to strip off the large carrier doppler in the original signal, the multiplied signal being
Figure 296042DEST_PATH_IMAGE035
And
Figure 477624DEST_PATH_IMAGE036
；
Figure 932876DEST_PATH_IMAGE037
Figure 832699DEST_PATH_IMAGE038
Figure 588690DEST_PATH_IMAGE035
and
Figure 624779DEST_PATH_IMAGE036
i.e. large carrier doppler in the original signal is stripped.
Further, the third step specifically comprises the steps of,
s31, driving a plurality of local pseudo-code generators by using the low-speed synchronous associated clock signal generated in the step S12, wherein each pseudo-code generator outputs a local pseudo-code signal
Figure 250933DEST_PATH_IMAGE039
With fixed phase offset
Figure 372473DEST_PATH_IMAGE040
；
S32, utilizing the on-chip distributed RAM of the FPGA to open up
Figure 679957DEST_PATH_IMAGE041
Block buffer region, starting from the initial address of each block buffer region, storing a local pseudo code signal output by pseudo code generator
Figure 836132DEST_PATH_IMAGE039
While the multiplied signal in S22 is simultaneously processed
Figure 633187DEST_PATH_IMAGE035
And
Figure 242023DEST_PATH_IMAGE036
writing in turn
Figure 336886DEST_PATH_IMAGE041
A block cache region;
s33, read from buffer
Figure 347568DEST_PATH_IMAGE035
And
Figure 315524DEST_PATH_IMAGE036
into the block parallel correlator of the I branch and into the block parallel correlator of the Q branchAnd coherent integration, namely performing FFT (fast Fourier transform) processing on a coherent integration result, and sending the FFT result to a peak value detection circuit to detect a correlation peak.
Further, the fourth step is to perform noise floor statistics on the signal segments with the correlation peak values appearing in the FFT result of the third step, and if the correlation peak ratio statistical noise is greater than a Threshold value Threshold, the correct correlation peak is considered to be found, and at this time, the carrier doppler and code phase corresponding to the found correlation peak are calculated and transmitted to the tracking circuit; if no correlation peak is found, switching the carrier Doppler frequency point through a state machine, and continuing to search, specifically including,
s41, caching the square of the amplitude of the FFT operation result in the step S33, and counting the cached data as
Figure 349339DEST_PATH_IMAGE042
Counting the time period
Figure 60943DEST_PATH_IMAGE042
Max _ point, while calculating the Noise estimate value Noise if
Figure 191710DEST_PATH_IMAGE043
Noise x Threshold, where Threshold represents a Threshold value, then the position where max _ point appears is deemed to be indeed the correlation peak position;
s42, if the correlation peak is found in the step S41, a code phase of the position of the correlation peak is deduced according to the FFT operation times in the step S41, a Doppler frequency shift value is deduced according to the position of the maximum spectrum peak in the FFT result, and then the code phase and the Doppler frequency shift value are transmitted to a tracking circuit;
and S43, if no correlation peak is found in the step S41, switching the carrier Doppler frequency point through the state machine, returning to the step S21, and continuing searching until all Doppler intervals are searched.
In another aspect, the present invention also discloses a computer readable storage medium storing a computer program, which when executed by a processor causes the processor to perform the steps of the above method.
According to the technical scheme, compared with the narrow-band spread spectrum signal, the bandwidth of the wide-band spread spectrum signal is wider, and the AD sampling rate is required to be as high as hundreds of megahertz and exceeds the direct processing capacity of most rear-end devices. At present, the mainstream spread spectrum fast acquisition algorithm aims at narrowband spread spectrum signals below 10Mbps, and no effective acquisition method is found for broadband spread spectrum signals. In order to solve the problem, the invention provides a parallel capturing method and a storage medium for broadband spread spectrum signals, which enable a back-end processing device to realize the rapid capturing of the broadband spread spectrum signals under bearable clock frequency under the condition of not reducing the sampling rate of a front end.
The invention comprises the following steps: the method comprises the following steps: the radio frequency input signal is subjected to radio frequency front end, ADC sampling and coding to obtain a high-speed digital baseband coding signal, then a low-speed original bit expansion signal is obtained through local decoding deserializing and serial-parallel conversion, and a low-speed synchronous channel associated clock signal is generated; step two: the low speed synchronous associated clock signal generated in the first step drives a plurality of local carrier Doppler generators. Multiplying the output carrier signal with fixed phase offset by the low-speed original bit-spread signal generated in the first step, and stripping the carrier Doppler in the original signal; step three: the low speed synchronous associated clock signal generated in the first step drives a plurality of local pseudo-code generators. Carrying out partial matched filtering and coherent integration on the output pseudo code signal with fixed phase offset and the signal generated in the second step, and carrying out FFT operation on a coherent integration result; step four: and performing peak detection on the FFT result of the third step. If the correct correlation peak is found, calculating the corresponding carrier Doppler and code phase; if no relevant peak is found, the carrier Doppler frequency point is switched, and the search is continued. The device of the invention consists of a front-end radio frequency processing circuit, an analog intermediate frequency processing circuit, a digital coding circuit and a baseband processing circuit. The invention utilizes the principle of 'space displacement time' and the principle of partial matched filtering to complete the capture of the broadband spread spectrum signal. Firstly, carrying out local decoding deserializing and serial-parallel conversion processing on two paths of mutually orthogonal high-speed digital baseband coding signals, converting the signals into low-speed original bit extension signals, and generating low-speed synchronous channel associated clock signals; then, a plurality of local carrier Doppler generators with fixed phase difference and a plurality of local pseudo-code generators are driven by a low-speed synchronous associated clock signal, and high-speed local carrier and pseudo-code signals are widened in space (circuit area); then multiplying the bit-spread signal by a plurality of local carriers for stripping larger Doppler, and sending the multiplication result and the local pseudo code signal into a partial matched filter for coherent integration processing; and finally, carrying out FFT operation on the result of coherent integration processing, comparing a peak signal with a noise bottom, if the ratio of the correlation peak to the noise bottom is greater than a threshold value, determining that a correct correlation peak is found, calculating carrier Doppler and code phase positions corresponding to the found correlation peak, outputting the carrier Doppler and code phase positions backwards and transmitting the carrier Doppler and code phase positions to a tracking circuit, and otherwise, switching carrier Doppler frequency points and continuing searching. To this end, parallel acquisition of the entire wideband spread spectrum signal is accomplished.
Through the steps, the broadband spread spectrum signal parallel capturing method and the storage medium realize the rapid capturing of the broadband spread spectrum signal through the space displacement time principle and the partial matching filtering principle. Because the bandwidth of the wideband spread spectrum signal is wider, its acquisition process requires a higher AD sampling rate, which is beyond the capability of most backend devices to directly process. By means of parallel expansion of the local carrier Doppler generator and the local pseudo code generator, the requirement of a system processing clock, namely the principle of space replacement time, is effectively reduced under the condition of utilizing more hardware resources, and the parallel capture algorithm technology is feasible and simple to implement; the partial matched filter and FFT algorithm is a capture algorithm commonly used at present, and a good balance point between hardware resources and time overhead can be obtained by adjusting parameters of the algorithm.
According to the design of the invention, the invention realizes a broadband spread spectrum signal parallel capturing method and a storage medium, the algorithm realization complexity is low, the capturing result is accurate, and the method is particularly suitable for the broadband spread spectrum signal capturing under a large dynamic scene.
According to the design of the invention, the invention realizes a broadband spread spectrum signal parallel capturing method and a storage medium, the algorithm is easy to integrate, and the reconstruction and the upgrade of the capturing algorithm in the existing narrow-band receiver are convenient.
Drawings
FIG. 1 is a hardware block diagram of an apparatus according to an embodiment of the present invention;
FIG. 2 is a diagram of an algorithmic digital logic framework according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a baseband signal deserializing sequence according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a carrier Doppler NCO parallel expansion design according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating the design of parallel code NCO expansion according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of PMF-FFT processing according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a process of noise floor statistics according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
The embodiment of the invention utilizes the principle of 'space replacement time' and the principle of partial matched filtering to complete the capture of the broadband spread spectrum signal. Because the broadband spread spectrum signal often has the characteristics of high intermediate frequency (> 300 MHz), large bandwidth (> 200 MHz), large Doppler (> 2 MHz), high code rate (> 100 MHz) and the like, and even the clock rate inside a high-end FPGA chip is often difficult to exceed 200MHz, the general narrowband spread spectrum receiving scheme is no longer suitable for receiving the broadband spread spectrum signal. However, we know that a large amount of logic resources (LUT, D flip-flop, distributed RAM, multiplier, etc.) are provided inside a large-capacity FPGA chip, and if an original baseband signal running on a high-speed clock is converted to a low-speed clock in a "space replacement time" manner, the processing of the original signal can be completed by using the large amount of logic resources inside the large-capacity FPGA chip, and meanwhile, the coherent integration is performed on the original signal and a local code division block by using a partial matching filtering principle, so that the capture processing capability with the highest efficiency can be achieved, and the influence of large carrier doppler on code rate deviation can be greatly alleviated. The following is a detailed description:
as shown in fig. 1, the present invention is a hardware frame diagram of a system circuit of the apparatus, an input broadband radio frequency signal sequentially passes through a Low Noise Amplifier (LNA), an anti-mirror filter (SAW), a down converter, an anti-aliasing filter, an analog Automatic Gain Control (AGC), and AD sampling to obtain an intermediate frequency digital signal, the intermediate frequency digital signal is encoded into a high-speed digital code stream by a JESD204B, and then the high-speed digital code stream is sent to an FPGA chip, and baseband signal processing is completed inside the FPGA chip, where the baseband processing mainly refers to a parallel capture algorithm proposed by the present invention. The invention provides a broadband spread spectrum signal parallel capturing method and a storage medium based on FPGA (field programmable gate array), which are shown in figure 2 and are a digital logic framework diagram of the algorithm of the invention. The specific implementation steps are as follows:
the first step is as follows: radio frequency input signal
Figure 517518DEST_PATH_IMAGE001
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
Figure 835367DEST_PATH_IMAGE002
And Q branch signal
Figure 350662DEST_PATH_IMAGE003
Wherein k represents the kth clock cycle, and the high-speed digital baseband coded signal is converted into a low-speed original bit-spreading signal after being subjected to local decoding deserialization and serial-parallel conversion respectively
Figure 335935DEST_PATH_IMAGE004
And
Figure 583377DEST_PATH_IMAGE005
and simultaneously generating a low-speed synchronous channel associated clock signal.
Inputting orthogonal high-speed digital baseband coding signals to be processed by the FPGA as follows:
Figure 388522DEST_PATH_IMAGE024
Figure 441929DEST_PATH_IMAGE025
wherein
Figure 281709DEST_PATH_IMAGE026
Is the original radio frequency signal of the input,
Figure 949319DEST_PATH_IMAGE027
is Doppler frequency after zero intermediate frequency processing, and the sampling clock frequency of the high-speed digital baseband coding signal is
Figure 507340DEST_PATH_IMAGE022
. I branch signal
Figure 98858DEST_PATH_IMAGE016
And Q branch signal
Figure 996407DEST_PATH_IMAGE017
Of a signal
Figure 647968DEST_PATH_IMAGE016
Sum signal
Figure 427705DEST_PATH_IMAGE017
Are equal in code rate, are all
Figure 822914DEST_PATH_IMAGE018
；
To pair
Figure 827167DEST_PATH_IMAGE016
And
Figure 649629DEST_PATH_IMAGE017
after local decoding and deserializing, low-speed original spreading is obtainedBit signal
Figure 916663DEST_PATH_IMAGE019
And
Figure 53246DEST_PATH_IMAGE020
and generating a low speed synchronous channel clock having a frequency of
Figure 722125DEST_PATH_IMAGE021
，
Figure 715489DEST_PATH_IMAGE021
Size of and sampling clock frequency of high-speed digital baseband coding signal
Figure 469818DEST_PATH_IMAGE022
Related to the series-parallel ratio N in the relationship of
Figure 659360DEST_PATH_IMAGE023
. Low speed original bit-spread signal
Figure 182745DEST_PATH_IMAGE019
And
Figure 347010DEST_PATH_IMAGE020
can be expressed as:
Figure 526319DEST_PATH_IMAGE044
Figure 67021DEST_PATH_IMAGE045
；
Figure 444913DEST_PATH_IMAGE019
is a high-speed digital baseband coded signal
Figure 45659DEST_PATH_IMAGE016
The sampled vector after the low-speed extraction is performed,
Figure 695952DEST_PATH_IMAGE020
is a high-speed digital baseband coded signal
Figure 40345DEST_PATH_IMAGE017
Sampling vectors after low-speed extraction, wherein braces "{ }" represent vector intervals after sampling, and vector elements are represented in the braces { }.
Fig. 3 is a schematic diagram of a baseband signal deserialization timing.
The second step is that: the low-speed synchronous associated clock signal generated in the first step drives a plurality of local carrier Doppler generators, and the carrier signal output by each carrier Doppler generator
Figure 272744DEST_PATH_IMAGE006
And
Figure 982074DEST_PATH_IMAGE007
with fixed phase offset
Figure 932712DEST_PATH_IMAGE008
Wherein i represents the ith carrier Doppler generator, j represents the jth clock cycle, and the carrier Doppler frequency points are searched in a segmented manner under the control of a state machine; carrier signal output by each carrier Doppler generator
Figure 815217DEST_PATH_IMAGE006
And
Figure 354652DEST_PATH_IMAGE007
with the low-speed original bit-spread signal generated in the first step
Figure 297200DEST_PATH_IMAGE009
And
Figure 735135DEST_PATH_IMAGE010
multiplying to obtain multiplied signal
Figure 359014DEST_PATH_IMAGE011
And
Figure 566005DEST_PATH_IMAGE012
for stripping large carrier doppler in the original signal;
the local carrier Doppler generator is mainly composed of NCO in FPGA, driving clock frequency of NCO and sampling clock frequency of high-speed digital baseband coding signal
Figure 679454DEST_PATH_IMAGE022
Is equal to
Figure 794565DEST_PATH_IMAGE022
Driven by a clock of (2), each time a clock cycle passes
Figure 18873DEST_PATH_IMAGE046
A carrier phase point is obtained. If N carrier phase points are obtained, N clock cycles are required, that is, N clock cycles are required
Figure 345949DEST_PATH_IMAGE047
. But of a broadband baseband signal
Figure 302404DEST_PATH_IMAGE022
Often > 300MHz, such high sample rate carrier NCO cannot be implemented on a device, thus requiring parallel spread design of the NCO.
FIG. 4 is a schematic diagram of a parallel spread design of a carrier Doppler NCO. By the first step, a low speed associated clock can be generated
Figure 714931DEST_PATH_IMAGE021
In a
Figure 742930DEST_PATH_IMAGE021
At a sampling rate of (3), where N carrier NCO's are used to operate simultaneously, then in one clock cycle
Figure 111463DEST_PATH_IMAGE048
N carrier phase values may also be obtained. Will each beThe fixed phase offset between the signals generated by the individual carrier NCO is set to
Figure 566715DEST_PATH_IMAGE030
Then, at this time, the sampling result of the N parallel carrier NCO under the low-speed clock can be equivalent to the sampling result of the 1 carrier NCO under the high-speed clock. The carrier amplitude of the ith carrier NCO in the jth clock cycle is recorded as
Figure 138642DEST_PATH_IMAGE031
And
Figure 704752DEST_PATH_IMAGE032
(i =1,2, …, N), then there are:
Figure 6421DEST_PATH_IMAGE033
Figure 819525DEST_PATH_IMAGE034
carrier signal output by each carrier Doppler generator
Figure 941065DEST_PATH_IMAGE031
And
Figure 310866DEST_PATH_IMAGE032
and the low-speed original bit-spread signal generated in the first step
Figure 404724DEST_PATH_IMAGE019
And
Figure 201779DEST_PATH_IMAGE020
multiplying, the multiplied signal being recorded as
Figure 810615DEST_PATH_IMAGE035
And
Figure 905478DEST_PATH_IMAGE036
then, there are:
Figure 916160DEST_PATH_IMAGE037
Figure 884116DEST_PATH_IMAGE038
Figure 917931DEST_PATH_IMAGE035
and
Figure 629535DEST_PATH_IMAGE036
i.e. large carrier doppler in the original signal is stripped.
The third step: the low-speed synchronous associated clock signal generated in the first step drives a plurality of local pseudo-code generators; local pseudo-code signal output by each pseudo-code generator
Figure 494723DEST_PATH_IMAGE013
With fixed phase offset
Figure 835179DEST_PATH_IMAGE014
Wherein i represents the ith pseudo code generator, k represents the kth clock cycle, and the Doppler frequency point of the local pseudo code is adjusted under the control of a state machine; local pseudo-code signal output by each pseudo-code generator
Figure 418607DEST_PATH_IMAGE013
With the signal generated in the second step
Figure 933902DEST_PATH_IMAGE011
And
Figure 591280DEST_PATH_IMAGE012
carrying out partial matched filtering and coherent integration, and carrying out FFT operation on a coherent integration result;
fig. 5 is a schematic diagram of code NCO parallel expansion design. Similar to the second step, the code NCO is also usedAnd (5) designing line expansion. At low speed clock
Figure 901038DEST_PATH_IMAGE021
Then, N code NCO's are used to work simultaneously, and the fixed phase offset between pseudo code signals generated by the code NCO's is set to
Figure 971762DEST_PATH_IMAGE040
The method can be equivalent to the sampling result of 1 code NCO under a high-speed clock. The local pseudo-code signal output by the ith code NCO in the kth clock cycle is recorded as
Figure 212120DEST_PATH_IMAGE039
. Then utilizing on-chip distributed RAM of FPGA to open up
Figure 51900DEST_PATH_IMAGE041
A block buffer for storing an initial phase fixed offset of
Figure 532560DEST_PATH_IMAGE040
Local pseudo code signal of
Figure 90580DEST_PATH_IMAGE039
Simultaneously, the signal in the second step after the large carrier wave Doppler in the original signal is stripped
Figure 619781DEST_PATH_IMAGE049
And
Figure 314068DEST_PATH_IMAGE050
also written in turn
Figure 231208DEST_PATH_IMAGE041
A block buffer.
As shown in fig. 6, a schematic diagram of PMF-FFT processing is shown. To pair
Figure 197896DEST_PATH_IMAGE049
And
Figure 593106DEST_PATH_IMAGE050
coherent integration under PMF (partial matched filtering) can be performed to obtain:
Figure 407478DEST_PATH_IMAGE051
Figure 229940DEST_PATH_IMAGE052
wherein the content of the first and second substances,
Figure 434657DEST_PATH_IMAGE053
is the number of data that are partially coherently integrated (accumulated),
Figure 633557DEST_PATH_IMAGE054
is the number of the sub-blocks,
Figure 302436DEST_PATH_IMAGE055
() The function is a local pseudo-code sequence,
Figure 482750DEST_PATH_IMAGE056
。
to pair
Figure 237079DEST_PATH_IMAGE057
And
Figure 974091DEST_PATH_IMAGE058
performing FFT processing, and obtaining a pseudo code phase point at a correlation peak:
Figure 497477DEST_PATH_IMAGE059
wherein the content of the first and second substances,
Figure 865004DEST_PATH_IMAGE060
is a pseudo code phase point, one pseudo code period has NUM _ PN chips,
Figure 106629DEST_PATH_IMAGE022
is the rate of sampling of the sample to be measured,
Figure 381753DEST_PATH_IMAGE061
is the duration of the coherent integration and,
Figure 25224DEST_PATH_IMAGE062
performing FFT operation times corresponding to the correlation peak; the FFT operation is a fast fourier transform.
Similarly, the carrier doppler value can be obtained as:
Figure 550271DEST_PATH_IMAGE063
wherein, among others,
Figure 279192DEST_PATH_IMAGE027
is the value of the carrier doppler (c) and,
Figure 358007DEST_PATH_IMAGE021
is the down-sampling rate of the sample,
Figure 855984DEST_PATH_IMAGE053
is the number of data accumulated by the partial coherent integration,
Figure 565314DEST_PATH_IMAGE054
is the number of the sub-blocks,
Figure 515953DEST_PATH_IMAGE064
is the number of points of the FFT operation, m is the index value of the FFT,
Figure 398458DEST_PATH_IMAGE065
the function is a local pseudo-code sequence,
Figure 937893DEST_PATH_IMAGE066
the function is a signal stripped of the large carrier doppler in the original signal,
Figure 880441DEST_PATH_IMAGE056
the number of the accumulation ranges is represented,
Figure 318375DEST_PATH_IMAGE057
represents the value of the coherent integration of the pseudo code generated by the ith local pseudo code generator and the original I-path signal,
Figure 676676DEST_PATH_IMAGE058
the value of the coherent integration of the pseudo code generated by the ith local pseudo code generator and the original Q path signal is represented, and n represents the nth sampling of the partial coherent integration;
the fourth step: noise bottom statistics is carried out on signal segments with correlation peak values appearing in the FFT result of the third step, if the correlation peak ratio statistical noise is larger than a Threshold value Threshold, a correct correlation peak is considered to be found, carrier Doppler and code phase corresponding to the found correlation peak are calculated, and the carrier Doppler and code phase are output backwards and transmitted to a tracking circuit; if no correlation peak is found, the carrier Doppler frequency point is switched through the state machine, and the search is continued. The Threshold value Threshold here reflects a multiple relationship, and if the correlation peak-to-peak value is greater than the Threshold multiple of the statistical noise power, it indicates that the correlation peak-to-peak value found is sufficiently high.
After coherent integration in the third step, the expression of the Q branch output is as follows:
Figure 149245DEST_PATH_IMAGE067
Figure 262695DEST_PATH_IMAGE068
the corresponding I branch outputs are as follows:
Figure 374876DEST_PATH_IMAGE069
Figure 599184DEST_PATH_IMAGE070
to eliminate initial phase difference
Figure 660681DEST_PATH_IMAGE071
Will have an influence on
Figure 945032DEST_PATH_IMAGE072
And
Figure 295242DEST_PATH_IMAGE073
add after squaring, and is recorded as
Figure 323241DEST_PATH_IMAGE042
Obtaining:
Figure 504823DEST_PATH_IMAGE074
in the formula (I), the compound is shown in the specification,
Figure 881447DEST_PATH_IMAGE075
in order to be a noise term, the noise term,
Figure 781270DEST_PATH_IMAGE076
is the power of the mid-band pass signal,
Figure 347380DEST_PATH_IMAGE077
the function is an auto-correlation function that,
Figure 649049DEST_PATH_IMAGE078
is the difference between the actual intermediate frequency and the nominal intermediate frequency,
Figure 947306DEST_PATH_IMAGE079
is the difference between the true code phase and the local code phase,
Figure 334425DEST_PATH_IMAGE080
representing chi-squared distribution, the above equation illustrates the result after addition
Figure 704226DEST_PATH_IMAGE042
Accord with freedomA non-central chi-square distribution with a degree of 2,
Figure DEST_PATH_IMAGE081
in order to be a non-centering parameter,
Figure 784702DEST_PATH_IMAGE061
is the first coherent integration duration; .
Will be provided with
Figure 581757DEST_PATH_IMAGE042
Caching and counting for a period of time
Figure 190593DEST_PATH_IMAGE042
The maximum value max _ point, and the Noise estimation value Noise is calculated at the same time, the statistics of the Noise can be performed by selecting any branch without the occurrence of the correlation peak, if the statistics is performed, the maximum value max _ point is the maximum value max _ point, and the Noise estimation value Noise is calculated by selecting any branch without the occurrence of the correlation peak
Figure 301768DEST_PATH_IMAGE043
Noise x Threshold, then the position where max _ point appears is considered to be the correlation peak position, i.e. the correct correlation peak is considered to be found; the capture probability can be expressed as:
Figure 312450DEST_PATH_IMAGE082
in the formula (I), the compound is shown in the specification,
Figure 280406DEST_PATH_IMAGE083
a class of bessel functions that is of the order 0,
Figure 563488DEST_PATH_IMAGE075
in order to be a noise term, the noise term,
Figure 275092DEST_PATH_IMAGE076
which is the power of the mid-band pass signal, threshold is the Threshold value,
Figure 140280DEST_PATH_IMAGE061
is the time length of one-time coherent integration, and z is the integration variable. As shown in fig. 7, is a noise floor systemAnd (4) calculating a process schematic diagram.
If the correlation peak is found in the above steps, the code phase of the position of the correlation peak is deduced according to the FFT operation times in the third step, the Doppler frequency shift value is deduced according to the position of the maximum spectrum peak in the FFT result, then the code phase and the Doppler frequency shift value are transmitted to a tracking circuit, and a tracking start signal is synchronously given. If no relevant peak is found in the steps, the carrier Doppler frequency point is switched through the state machine, and the searching is continued until all Doppler intervals are searched.
From the above, the broadband spread spectrum signal parallel acquisition method according to the embodiment of the present invention realizes the fast acquisition of the broadband spread spectrum signal by the "space replacement time" principle and the partial matched filtering principle, and effectively reduces the overall hardware cost of the receiver.
In yet another aspect, the present invention also discloses a computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of any of the methods described above.
In yet another aspect, the present invention also discloses a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of any of the methods described above.
In a further embodiment provided by the present application, there is also provided a computer program product comprising instructions which, when run on a computer, cause the computer to perform the steps of any of the methods of the above embodiments.
It can be understood that the system provided by the embodiment of the present invention corresponds to the method provided by the embodiment of the present invention, and for the explanation, examples and beneficial effects of the relevant contents, reference may be made to the corresponding parts in the above method.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by a computer program, which may be stored in a non-volatile computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (9)

1. A method for parallel acquisition of a wideband spread spectrum signal, comprising the steps of,
step one, radio frequency input signal
Figure 974898DEST_PATH_IMAGE001
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
Figure 497146DEST_PATH_IMAGE002
And Q branch signal
Figure 336926DEST_PATH_IMAGE003
Wherein k represents the kth clock cycle, and the high-speed digital baseband coded signal is converted into a low-speed original bit-spreading signal after being subjected to local decoding deserialization and serial-parallel conversion respectively
Figure 817586DEST_PATH_IMAGE004
And
Figure 703503DEST_PATH_IMAGE005
simultaneously generating a low-speed synchronous channel associated clock signal;
driving a plurality of local carrier Doppler generators by the low-speed synchronous associated clock signal generated in the first step, wherein the carrier signal output by each carrier Doppler generator
Figure 560600DEST_PATH_IMAGE006
And
Figure 254887DEST_PATH_IMAGE007
with fixed phase offset
Figure 906448DEST_PATH_IMAGE008
Wherein i represents the ith carrier Doppler generator, j represents the jth clock cycle, and the carrier Doppler frequency points are searched in a segmented manner under the control of a state machine; carrier signal output by each carrier Doppler generator
Figure 420606DEST_PATH_IMAGE006
And
Figure 815815DEST_PATH_IMAGE007
with the low-speed original bit-spread signal generated in the first step
Figure 364608DEST_PATH_IMAGE009
And
Figure 452650DEST_PATH_IMAGE010
multiplying to obtain multiplied signal
Figure 313159DEST_PATH_IMAGE011
And
Figure 246480DEST_PATH_IMAGE012
for stripping large carrier doppler in the original signal;
driving a plurality of local pseudo-code generators by the low-speed synchronous associated clock signal generated in the first step; local pseudo-code signal output by each pseudo-code generator
Figure 915358DEST_PATH_IMAGE013
With fixed phase offset
Figure 174301DEST_PATH_IMAGE014
Wherein i represents the ith pseudo-code generator, k represents the kth clock cycle, and the local pseudo-code Doppler frequency point is adjusted under the control of the state machine; local pseudo-code signal output by each pseudo-code generator
Figure 131893DEST_PATH_IMAGE013
With the signal generated in the second step
Figure 134484DEST_PATH_IMAGE011
And
Figure 657869DEST_PATH_IMAGE012
performing partial matched filtering and coherent integration, and performing FFT operation on the coherent integration resultCalculating;
fourthly, carrying out noise bottom statistics on the signal segments with the correlation peak values appearing in the FFT result of the third step, if the correlation peak ratio statistical noise is larger than a Threshold value Threshold, determining that a correct correlation peak is found, calculating carrier Doppler and code phase corresponding to the found correlation peak, and outputting the carrier Doppler and code phase backwards
The output is transmitted to a tracking circuit; if no correlation peak is found, the carrier Doppler frequency point is switched through the state machine, and the search is continued.
2. The method of parallel acquisition of a wideband spread spectrum signal according to claim 1, wherein: the step one specifically comprises the following steps of,
s11, original radio frequency input signal
Figure 822134DEST_PATH_IMAGE015
After zero intermediate frequency, anti-aliasing filtering, ADC sampling and coding processing, the two paths of mutually orthogonal high-speed digital baseband coding signals are changed into two paths of mutually orthogonal high-speed digital baseband coding signals which are I branch signals respectively
Figure 657235DEST_PATH_IMAGE016
And Q branch signal
Figure 197938DEST_PATH_IMAGE017
Signal of
Figure 575830DEST_PATH_IMAGE016
Sum signal
Figure 176575DEST_PATH_IMAGE017
Are equal in code rate, are all
Figure 108759DEST_PATH_IMAGE018
；
S12, high-speed digital baseband coding signal
Figure 453153DEST_PATH_IMAGE016
And
Figure 951130DEST_PATH_IMAGE017
after being processed by local decoding deserializing and serial-parallel conversion respectively, the signals become low-speed original extension bit signals
Figure 457198DEST_PATH_IMAGE019
And
Figure 266891DEST_PATH_IMAGE020
simultaneously generating a low-speed synchronous channel clock signal having a frequency of
Figure 149396DEST_PATH_IMAGE021
，
Figure 501880DEST_PATH_IMAGE021
Size and high speed sampling clock
Figure 178849DEST_PATH_IMAGE022
Is related to the serial-to-parallel ratio N in the relationship of
Figure 85625DEST_PATH_IMAGE023
；
Wherein the content of the first and second substances,
Figure 771822DEST_PATH_IMAGE024
Figure 978812DEST_PATH_IMAGE025
wherein
Figure 92262DEST_PATH_IMAGE026
Is the original radio frequency signal of the input,
Figure 610968DEST_PATH_IMAGE027
is a channelDoppler frequency after zero intermediate frequency processing, a sampling clock frequency of the high-speed digital baseband coded signal of
Figure 835276DEST_PATH_IMAGE022
；
Then
Figure 162352DEST_PATH_IMAGE028
Figure 446703DEST_PATH_IMAGE029
Figure 62492DEST_PATH_IMAGE019
Is a high-speed digital baseband coded signal
Figure 90491DEST_PATH_IMAGE016
The sampled vector after the low-speed extraction is performed,
Figure 272073DEST_PATH_IMAGE020
is a high-speed digital baseband coded signal
Figure 727325DEST_PATH_IMAGE017
Sampling vectors after low-speed extraction, wherein braces are used for representing vector intervals after sampling, and vector elements are represented in the braces.
3. The method of parallel acquisition of a wideband spread spectrum signal according to claim 2, wherein: the second step specifically comprises the following steps of,
s21, driving a plurality of local carrier Doppler generators by using the low-speed synchronous associated clock signal generated in the step S12, wherein the carrier signals output by the carrier Doppler generators have fixed phase deviation
Figure 220624DEST_PATH_IMAGE030
Of orthogonal signals
Figure 786734DEST_PATH_IMAGE031
And
Figure 822823DEST_PATH_IMAGE032
；
that is, the carrier amplitude of the ith carrier Doppler generator in the jth clock cycle is recorded as
Figure 917818DEST_PATH_IMAGE031
And
Figure 39358DEST_PATH_IMAGE032
i =1,2, …, N, then:
Figure 409159DEST_PATH_IMAGE033
Figure 565334DEST_PATH_IMAGE034
s22, carrier signals output by each carrier Doppler generator
Figure 362389DEST_PATH_IMAGE031
And
Figure 564700DEST_PATH_IMAGE032
and the low-speed original bit-spread signal generated in S12
Figure 472613DEST_PATH_IMAGE019
And
Figure 483295DEST_PATH_IMAGE020
multiplying to strip off the large carrier Doppler in the original signal, after multiplicationIs a signal of
Figure 451251DEST_PATH_IMAGE035
And
Figure 16224DEST_PATH_IMAGE036
；
Figure 727828DEST_PATH_IMAGE037
Figure 858595DEST_PATH_IMAGE038
Figure 997453DEST_PATH_IMAGE035
and
Figure 908777DEST_PATH_IMAGE036
i.e. large carrier doppler in the original signal is stripped.
4. The method of parallel acquisition of a wideband spread spectrum signal according to claim 2, wherein: the third step specifically comprises the following steps of,
s31, driving a plurality of local pseudo-code generators by using the low-speed synchronous associated clock signal generated in the step S12, wherein each pseudo-code generator outputs a local pseudo-code signal
Figure 424072DEST_PATH_IMAGE039
With fixed phase offset
Figure 409345DEST_PATH_IMAGE040
；
S32, utilizing the on-chip distributed RAM of the FPGA to open up
Figure 719104DEST_PATH_IMAGE041
Block bufferA storage region for storing a local pseudo code signal output by a pseudo code generator from the initial address of each buffer region
Figure 993090DEST_PATH_IMAGE039
While multiplying the signal in S22
Figure 46497DEST_PATH_IMAGE035
And
Figure 886277DEST_PATH_IMAGE036
writing in turn
Figure 366937DEST_PATH_IMAGE041
A block cache region;
s33, read from buffer
Figure 518433DEST_PATH_IMAGE035
And
Figure 109951DEST_PATH_IMAGE036
and the block parallel correlator of the I branch and the block parallel correlator of the Q branch are subjected to coherent integration, the result of the coherent integration is subjected to FFT (fast Fourier transform) processing, and the result of the FFT is sent to a peak value detection circuit to detect a correlation peak.
5. The method of parallel acquisition of wideband spread spectrum signals according to claim 1, wherein: the fourth step specifically comprises the following steps of,
s41, caching the square of the amplitude of the FFT operation result in the step S33, and counting the cached data as
Figure 69817DEST_PATH_IMAGE042
Counting the time period
Figure 721378DEST_PATH_IMAGE042
Max _ point, while calculating the Noise estimate value Noise if
Figure 969957DEST_PATH_IMAGE043
Noise x Threshold, where Threshold represents a Threshold value, then the position where max _ point appears is deemed to be indeed the correlation peak position;
s42, if the correlation peak is found in the step S41, a code phase of the position of the correlation peak is deduced according to the FFT operation times in the step S41, a Doppler frequency shift value is deduced according to the position of the maximum spectrum peak in the FFT result, and then the code phase and the Doppler frequency shift value are transmitted to a tracking circuit;
and S43, if no correlation peak is found in the step S41, switching the carrier Doppler frequency point through the state machine, returning to the step S21, and continuing searching until all Doppler intervals are searched.
6. The method of parallel acquisition of a wideband spread spectrum signal according to claim 4, wherein: the FFT processing of the coherent integration result specifically includes,
to pair
Figure 365166DEST_PATH_IMAGE044
And
Figure 179538DEST_PATH_IMAGE045
coherent integration under PMF can be performed:
Figure 595476DEST_PATH_IMAGE046
Figure 862509DEST_PATH_IMAGE047
wherein, the first and the second end of the pipe are connected with each other,
Figure 61409DEST_PATH_IMAGE048
is the number of data accumulated by the partial coherent integration,
Figure 730288DEST_PATH_IMAGE049
is the number of the sub-blocks,
Figure 192494DEST_PATH_IMAGE050
the function is a local pseudo-code sequence,
Figure 946823DEST_PATH_IMAGE051
the function is a signal stripped of the large carrier doppler in the original signal,
Figure 949414DEST_PATH_IMAGE052
the number of the accumulation ranges is represented,
Figure 472799DEST_PATH_IMAGE053
represents the value of the coherent integration of the pseudo code generated by the ith local pseudo code generator and the original I-path signal,
Figure 230540DEST_PATH_IMAGE054
the value of the coherent integration of the pseudo code generated by the ith local pseudo code generator and the original Q path signal is represented, and n represents the nth sampling of the partial coherent integration;
to pair
Figure 472165DEST_PATH_IMAGE053
And
Figure 12868DEST_PATH_IMAGE054
performing FFT processing, and obtaining a pseudo code phase point at a correlation peak:
Figure 390760DEST_PATH_IMAGE055
wherein, the first and the second end of the pipe are connected with each other,
Figure 460347DEST_PATH_IMAGE056
is a pseudo code phase point, one pseudo code period has NUM _ PN chips,
Figure 923689DEST_PATH_IMAGE022
is the rate of sampling of the sample to be measured,
Figure 268083DEST_PATH_IMAGE057
is the duration of the coherent integration and,
Figure 500481DEST_PATH_IMAGE058
performing FFT operation times corresponding to the correlation peak;
similarly, the carrier doppler value is obtained as:
Figure 865603DEST_PATH_IMAGE059
wherein the content of the first and second substances,
Figure 816242DEST_PATH_IMAGE027
is the value of the carrier doppler (c) and,
Figure 698747DEST_PATH_IMAGE021
is the down-sampling rate of the sample,
Figure 51231DEST_PATH_IMAGE048
is the number of data accumulated by the partial coherent integration,
Figure 462621DEST_PATH_IMAGE060
is the number of points of the FFT operation, and m is the index value of the FFT.
7. The method of parallel acquisition of a wideband spread spectrum signal according to claim 6, wherein:
after coherent integration in the third step, the expression of the Q branch output is as follows:
Figure 900555DEST_PATH_IMAGE061
Figure 586752DEST_PATH_IMAGE062
the corresponding I branch outputs are as follows:
Figure 387217DEST_PATH_IMAGE063
Figure 500667DEST_PATH_IMAGE064
to eliminate the initial phase difference
Figure 425898DEST_PATH_IMAGE065
Will have an influence on
Figure 650206DEST_PATH_IMAGE066
And
Figure 446123DEST_PATH_IMAGE067
add after squaring, and is recorded as
Figure 464895DEST_PATH_IMAGE042
Obtaining:
Figure 877422DEST_PATH_IMAGE068
in the formula (I), the compound is shown in the specification,
Figure 905421DEST_PATH_IMAGE069
in order to be a noise term, the noise term,
Figure 680479DEST_PATH_IMAGE070
is the power of the mid-band pass signal,
Figure 135731DEST_PATH_IMAGE071
the function is an auto-correlation function and,
Figure 769974DEST_PATH_IMAGE072
is the difference between the actual intermediate frequency and the nominal intermediate frequency,
Figure 804926DEST_PATH_IMAGE073
is the difference between the true code phase and the local code phase,
Figure 106595DEST_PATH_IMAGE074
representing chi-squared distribution, the above equation illustrates the result after addition
Figure 732748DEST_PATH_IMAGE042
Conforming to the non-central chi-square distribution with the degree of freedom of 2,
Figure 447763DEST_PATH_IMAGE075
in order to be a non-centering parameter,
Figure 817565DEST_PATH_IMAGE057
is the first coherent integration duration;
will be provided with
Figure 973740DEST_PATH_IMAGE042
Caching, and counting for a period of time
Figure 770794DEST_PATH_IMAGE042
Max _ point, while calculating the Noise estimate value Noise if
Figure 848472DEST_PATH_IMAGE043
Noise x Threshold, wherein Threshold represents a Threshold value, and the position where max _ point appears is considered to be the correlation peak position, that is, the correct correlation peak is considered to be found; the capture probability is expressed as:
Figure 756385DEST_PATH_IMAGE076
in the formula (I), the compound is shown in the specification,
Figure 767066DEST_PATH_IMAGE077
a class of bessel functions that is of the order 0,
Figure 735022DEST_PATH_IMAGE069
in order to be a noise term, the noise term,
Figure 424630DEST_PATH_IMAGE070
which is the power of the mid-band pass signal, threshold is the Threshold value,
Figure 136234DEST_PATH_IMAGE057
is the time length of one-time coherent integration, and z is the integration variable.
8. The method of parallel acquisition of a wideband spread spectrum signal according to claim 7, wherein: the Noise is counted by selecting any branch without the occurrence of the correlation peak.
9. A computer-readable storage medium, storing a computer program which, when executed by a processor, causes the processor to carry out the steps of the method according to any one of claims 1 to 8.
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