CN101726746A - Intermediate frequency direct sequence spread spectrum receiver for satellite ranging - Google Patents

Abstract

The invention relates to an intermediate frequency direct sequence spread spectrum receiver for satellite ranging, which consists of 37 parts of a front-end A/D, an FFT module, a local PN code generator, a correlator, an automatic threshold calculation module and the like. The connection relationship is as follows: the output of the front-end A/D and the output of a carrier tracking loop NCO are respectively connected to an in-phase branch multiplier and an orthogonal branch multiplier, the input of the front-end A/D and the input of the carrier tracking loop NCO enter into an in-phase branch FIR low-pass filter and an orthogonal branch FIR low-pass filter, consequently, on the one hand, the output is sent to an integral zero clearing device, then the output which is sent to the FFT module, a branch 1 local PN code memory ROM and a branch 2 local PN code memory ROM enters into a branch 1 complex multiplier and a branch 2 complex multiplier, the output is sent to a branch 1 root mean square module and a branch 2 root mean square module, the output is sent to the threshold calculation module and a capturing and judging module for carrying out code catching; and on the other hand, the output is sent to the correlator and the local PN code generator for carrying out code tracking. The output of the correlator is simultaneously sent into a frequency discriminator/phase discriminator of the carrier tracking loop and then enters into a loop filter of the carrier tracking loop, and the output of the loop filter of the carrier tracking loop enters into the carrier tracking loop NCO for carrying out carrier tracking.

Description

A kind of intermediate frequency direct sequence spread spectrum receiver that is used for satellite ranging

(1) technical field

The present invention relates to a kind of band spread receiver, relate in particular to a kind of intermediate frequency direct sequence spread spectrum receiver that is used for satellite ranging, this invention belongs to technical field of satellite communication.

(2) background technology

Development along with spationautics, the survey of deep space strategy of China is formally launched, and bear first fruit, in October, 2007, the Chang'e I moon probing satellite succeeds in sending up, and has passed a large amount of moon telemetries back, for utilizing, China surveys space, utilize space to step the first step, simultaneously, the success of moon exploration will be established technical foundation for China carries out survey of deep space.

In the survey of deep space process, it is significant constantly to understand the residing exact position of satellite, location to satellite not only can make land station understand the duty of satellite, residing position constantly, and can provide foundation for change rail, the attitude adjustment of satellite.The principle of range finding is to measure the propagation delay time of radio signal to measured target, thereby calculates and target range.The satellite ranging system of China mainly is divided into two kinds, sidetone (continuant) range measurement system and pseudo-code (spread spectrum) range measurement system at present.Continuant range finding is main by sending the continuous distance measuring signal of a series of different frequencies, the time-delay of measuring each frequency signal that receives, and highest frequency component is called as the range finding clock, has determined the precision of side-tone ranging, and other component is used for fuzzy distance solution.The pseudo-random code ranging signal is by sending specific spread spectrum code sequence, and the phase place time-delay of the spread spectrum code sequence that instrumented satellite returns can obtain the distance between land station and the satellite.Compare with side-tone ranging, pseudo-random code ranging has the distance accuracy height, no fuzzy distance is big, antijamming capability is strong, and anti-fading ability is strong, and the anti-multipath interference performance is strong, good confidentiality, have advantages such as CDMA ability, pseudo-random code ranging is the important means of satellite observing and controlling, and China's satellite ranging mode just more and more adopts the pseudo-random code ranging mode at present.

The precision of pseudo-random code ranging is by the spreading rate decision of spreading code, and the high more distance measuring precision of spreading rate is high more, and the no fuzzy distance of range finding is by the length decision of ranging code.Ranging code is long more, and the distance range that can measure is big more.In order to improve distance accuracy, increase maximum measuring distance, need to improve the spreading rate of spreading code, and select longer spreading code, but spreading rate is high more, requirement to hardware is high more, the difficulty that realizes is big more, and the spreading code cycle is long more, and the difficulty of catching is big more, the time of catching is long more, therefore design a kind of can be significant to the band spread receiver that high spreading rate long code is caught fast.

(3) summary of the invention

1, purpose: the purpose of this invention is to provide a kind of intermediate frequency direct sequence spread spectrum receiver that is used for satellite ranging.This band spread receiver can be caught fast to the long code of high spreading rate, and has higher distance accuracy.

2, technical scheme: as shown in Figure 1, a kind of intermediate frequency direct sequence spread spectrum receiver that is used for satellite ranging of the present invention, composition comprises: the front end analog-to-digital conversion module (is called for short front-end A/D) 10, in-phase branch multiplier 20, in-phase branch finite impulse response low-pass filter (being called for short in-phase branch FIR low-pass filter) 21, quadrature branch multiplier 30, quadrature branch finite impulse response low-pass filter (being called for short quadrature branch FIR low-pass filter) 31, integration zero clearing device 40, buffer 41, fast Fourier transform module (being called for short the FFT module) 42, branch road 1 complex multiplier 50, branch road 1 local pseudo-random code storage ROM (read-only memory) (being called for short branch road 1 local PN sign indicating number storage ROM) 51, branch road 1 inverse fast fourier transform module (being called for short branch road 1IFFT module) 52, branch road 1 mean square root module 53, branch road 2 complex multipliers 60, branch road 2 local pseudo-random code storage ROM (read-only memory) (being called for short branch road 2 local PN sign indicating number storage ROM) 61, branch road 2 inverse fast fourier transform modules (being called for short branch road 2IFFT module) 62, branch road 2 mean square root module 63, automatic threshold computing module 70, catch judge module 71, pseudo-random code reference position computing module (being called for short PN sign indicating number reference position computing module) 72, carrier frequency adjustment module 73, local pseudo-random code maker (being called for short local PN code generator) 80, correlator 81, code tracking loop mean square root module 82, code tracking loop phase detector 83, code tracking loop loop filter 84, code tracking loop totalizer 85, code tracking loop digital controlled oscillator (being called for short code tracking loop NCO) 86, code tracking loop Doppler effect correction module 87, carrier tracking loop frequency discrimination/phase detector 90, carrier tracking loop loop filter 91, carrier tracking loop totalizer 92 and carrier tracking loop digital controlled oscillator (being called for short carrier tracking loop NCO) 93.

Wherein code tracking loop loop filter 84 is identical with carrier tracking loop loop filter 91 inner structures, has only the parameter difference, as shown in Figure 2: comprise straight-through branch amplifier 100, loop filter totalizer 101, integration branch amplifier 110, integration branch road totalizer 111 and integration branch road delay unit 112.

Above-mentioned all constituents, except that front-end A/D10 used the ready-made product of putting on the shelf, remainder was all realized in programmable gate array (FPGA).

Described front-end A/D10 carries out bandpass sampling with constant sampling rate to the 70M intermediate frequency spread-spectrum signal after nursing one's health, and the simulating signal of importing is transformed to digital signal, and front-end A/D10 uses ready-made product.

Carrier tracking loop NCO 93 uses direct frequency synthesizing algorithm (being called for short the DDS algorithm) to realize, be responsible for producing fixedly local carrier of the two-way identical with nominal intermediate frequency behind front-end A/D10 bandpass sampling, 90 ° of the phase phasic differences of two-way carrier wave, the signal behind the bandpass sampling of the output of carrier tracking loop NCO 93 and front-end A/D10 output is as the input of in-phase branch multiplier 20 and quadrature branch multiplier 30; In-phase branch multiplier 20 and quadrature branch multiplier 30 use the inner IP kernel of FPGA to realize, use as low-converter, input signal is down-converted to zero intermediate frequency, and in-phase branch multiplier 20 enters identical in-phase branch FIR low-pass filter 21 of structure and quadrature branch FIR low-pass filter 31 respectively with the result of quadrature branch multiplier 30 outputs; In-phase branch FIR low-pass filter 21 and quadrature branch FIR low-pass filter 31 adopt the FIR Structure Filter, use the inner IP kernel of FPGA to realize, be responsible for the signal after the down coversion is carried out filtering, frequency multiplication component and out-of-band noise after the filtering down coversion drop to the noise power in the baseband signal lower.

Result after the low-pass filtering exports to integration zero clearing device 40 on the one hand, carries out sign indicating number and catches, and exports to correlator 81 on the other hand and is used for code tracking.Integration zero clearing device 40 carries out the integration zero clearing respectively to in-phase branch FIR low-pass filter 21 and quadrature branch FIR low-pass filter 31 filtered results under the local PN sign indicating number clock control that code tracking loop NCO86 produces.The result of integration zero clearing device 40 outputs enters buffer 41, and the signal to homophase and quadrature branch carries out buffer memory simultaneously in buffer 41, and to adapt to the requirement of 42 pairs of input data rates of follow-up FFT module, buffer 41 uses the inner IP kernel of FPGA to realize.The homophase of exporting behind buffer 41 buffer memorys and the result of quadrature branch as the real part and the imaginary part input of FFT module 42, carry out Fast Fourier Transform (FFT) respectively in FFT module 42, FFT module 42 uses the inner IP kernel of FPGA to realize.The real part of FFT module 42 and imaginary part output are as one tunnel input of branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60, and branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60 use the inner IP kernel of FPGA to realize.Another road input of branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60 is provided by branch road 1 local PN sign indicating number storage ROM51 and branch road 2 local PN sign indicating number storage ROM61 respectively.The output of FFT module 42 successively with local PN sign indicating number storage ROM51 of branch road 1 and branch road 2 local PN sign indicating numbers storage ROM61 in the local PN sign indicating number the stored result after through the FFT conversion carry out complex multiplication.Local PN sign indicating number storage ROM51 of branch road 1 and branch road 2 local PN sign indicating numbers storage ROM61 use the inner IP kernels of FPGA to realize, the data of inside solidification are the result after code phase differs half the local PN sign indicating number of the two-way sequence FFT conversion of FFT length.Result after branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60 calculate sends into branch road 1 IFFT module 52 respectively and branch road 2 IFFT modules 62 are carried out inverse fast fourier transform, and branch road 1 IFFT module 52 and branch road 2 IFFT modules 62 use the inner IP kernel of FPGA to realize.Branch road 1 mean square root module 53 is sent in the output of branch road 1 IFFT module 52 and branch road 2 IFFT modules 62 respectively and branch road 2 mean square root module 63 are calculated corresponding root-mean-square value, and the JPL approximate data is adopted in the calculating of root-mean-square value, promptly utilizes formula $\sqrt{a^2+b^2}\≈\mathrm{Max}(\mathrm{abs}\left(a\right),\mathrm{abs}\left(b\right))+\frac{1}{2}\left(\mathrm{Min}(\mathrm{abs}\left(s\right),\mathrm{abs}\left(b\right))\right)$ Calculate root-mean-square value, calculate after the root-mean-square value, automatic threshold computing module 70 is sent in the output of branch road 1 mean square root module 53 and branch road 2 mean square root module 63 simultaneously, the state computation of relevant peaks goes out suitable threshold value according to this moment, output and branch road 1 mean square root module 53 with automatic threshold computing module 70, the output of branch road 2 mean square root module 63 is sent into simultaneously and is caught judge module 71, catches thresholding and branch road 1 mean square root module 53 of judge module 71 by relatively automatic threshold module 70 outputs, the correlation peak of the output of branch road 2 mean square root module 63 judges whether band spread receiver catches.Catch the output of judge module 71 and send into PN sign indicating number reference position computing module 72 and carrier frequency adjustment module 73 respectively.

When catching judge module 71 when judging that the spread spectrum answering machines are not caught, band spread receiver is operated in trapped state, and carrier frequency adjustment module 73 is being searched for all after dates of a sign indicating number, can adjust the frequency separation of output, thereby adjust the frequency of carrier tracking loop NCO 93 outputs, until finish catch till.PN sign indicating number reference position computing module 72 not outputs this moment.When catching judge module 71 when judging that the spread spectrum answering machines have been caught, will make band spread receiver change tracking mode over to by trapped state.At this moment, carrier frequency adjustment module 73 can stop to adjust, simultaneously code tracking loop Doppler effect correction module 87 is sent in output this moment, code tracking loop Doppler effect correction module 87 is according to the proportionate relationship between spreading rate and the carrier frequency, produce corresponding PN sign indicating number Doppler effect correction component, be used to adjust the sign indicating number clock of code tracking loop NCO 86 outputs, the compensating for doppler effect is to the influence of spreading code.And PN sign indicating number reference position computing module 72 will calculate the reference position of local PN by the position of when locking relevant peaks, and result calculated is sent into local PN code generator 80, adjust the phase place of the local PN sequence that local PN code generator 80 produces.

Local PN code generator 80 produce leading (PN-), on schedule (PN), (PN+) three tunnel local PN sign indicating numbers lag behind, this three tunnel local PN sign indicating number is the phase difference of half chip phase each other, and three tunnel local PN sign indicating numbers enter correlator 81 backs simultaneously and carry out related operation with the output of in-phase branch FIR low-pass filter 21 and quadrature branch FIR low-pass filter 31.Three road correlated results of output are sent into code tracking loop mean square root module 82 simultaneously and are calculated root mean square.Wherein correlated results need be sent into carrier tracking loop frequency discrimination/phase detector 90 on schedule, carries out being used for carrier track behind frequency discrimination, the phase demodulation.The result of code tracking loop mean square root module 82 outputs enters code tracking loop phase detector 83 phase demodulations, phase-demodulating principle be relatively leading relevant result and lag correlation the result, the phase place of determining code tracking loop NCO86 still lags behind in advance, and the result of phase demodulation sends into code tracking loop loop filter 84.The main effect of code tracking loop loop filter 84 is the high fdrequency components in the filtering error signal; and provide the memory of a short-term for phase-locked loop; when loop because when instantaneous noise and losing lock; can guarantee loop lock-on signal again rapidly; code tracking loop loop filter 84 uses desirable firstorder filter; structure as shown in Figure 2; by two branch roads: straight-through branch road and integration branch road are formed; straight-through branch road only contains a straight-through branch amplifier 100; the multiple that input signal is amplified appointment gets final product; the integration branch road comprises integration branch amplifier 110; integration branch road unit delay unit 112 and integration branch road totalizer 111 are formed; the signal of input can enter the integration branch road when entering straight-through branch road; input is by the amplifier amplification back of integration branch road with through the results added after the time-delay of integration branch road delay unit; result's one side after the addition is as the input of integration branch road delay unit; on the other hand as the output of integration branch road; pass through 101 additions of loop filter totalizer with the output of straight-through branch road; result after two branch road additions is as the output of code tracking loop loop filter 84; 84 outputs of code tracking loop loop filter are sent into code tracking loop totalizer 85 simultaneously with the output of code tracking loop Doppler effect correction module 87 and are carried out sum operation; result after the addition sends into code tracking loop NCO 86; adjust output PN sign indicating number clock frequency, the local PN sign indicating number clock of feasible output and the sign indicating number clock synchronization that receives.

The correlated results on schedule of correlator 81 outputs is sent into carrier tracking loop frequency discrimination/phase detector 90, carries out frequency discrimination, phase demodulation.Carrier tracking loop frequency discrimination/phase detector 90 uses cross product frequency discrimination/phase demodulation algorithms, calculates the frequency difference between input signal carrier wave and the local carrier and differs.The frequency difference that calculates and differ incoming carrier tracking loop loop filter 91, the structure of carrier tracking loop loop filter 91 and code tracking loop loop filter 84 are identical, but coefficient is different.The output of the output of carrier tracking loop loop filter 91 and carrier frequency adjustment module 73 is incoming carrier tracking loop totalizer 92 together, the tracking loop of incoming carrier as a result NCO 93 after the summation follows the tracks of the carrier wave of input signal, finishes despreading, demodulation to the input spread-spectrum signal.

3, advantage and effect: as can be seen from the above description, the intermediate frequency direct sequence spread spectrum receiver of this satellite ranging has following characteristics: adopt FFT part correlation arresting structure; Utilize ROM to store local FFT result calculated and input signal carries out related operation; One road FFT calculates the correlation of two-way simultaneously.The advantage that this structure is brought is as follows:

(1) adopt FFT part correlation arresting structure, whenever carry out the relevant peaks that a FFT computing can calculate the FFT length points, compare the method for matched filtering, significantly reduce resource consumption, the speed of catching is faster.

(2) utilize ROM to store local FFT result calculated and input signal carries out related operation, need not carry out the FFT computing, reduced local PN FFT conversion module, significantly reduced the consumption of resource local PN sign indicating number.Simultaneously can guarantee the requirement of catching under different carrier-to-noise ratios according to the length of the degree of depth of ROM and FFT.

(3) utilize one road FFT to calculate the correlation of two-way simultaneously, compare with independent F FT and calculate the two-way relevant peaks, have identical capture time, but reduced the resource consumption of one road FFT computing module, improved resource utilization.

(4) description of drawings

Fig. 1 intermediate frequency direct sequence spread spectrum receiver of the present invention structural representation;

Fig. 2 loop filter structure synoptic diagram of the present invention;

Symbol description is as follows among the figure:

10 front-end A/D; 20 in-phase branch multipliers;

21 in-phase branch FIR low-pass filters;

30 quadrature branch multipliers; 31 quadrature branch FIR low-pass filters;

40 integration zero clearing devices; 41 buffers; The 42FFT module;

50 branch roads, 1 complex multiplier; 51 branch roads, 1 local PN sign indicating number storage ROM;

52 branch road 1IFFT modules; 53 branch roads, 1 mean square root module;

60 branch roads, 2 complex multipliers; 61 branch roads, 2 local PN sign indicating number storage ROM;

62 branch road 2IFFT modules; 63 branch roads, 2 mean square root module;

70 automatic threshold computing modules; 71 catch judge module;

72PN sign indicating number reference position computing module; 73 carrier frequency adjustment module;

80 local PN code generators; 81 correlators; 82 code tracking loop mean square root module

83 code tracking loop phase detectors; 84 code tracking loop loop filters;

85 code tracking loop totalizers; 86 code tracking loop NCO;

87 code tracking loop Doppler effect correction modules; 90 carrier tracking loop frequency discrimination/phase detectors;

91 carrier tracking loop loop filters; 92 carrier tracking loop totalizers

93 carrier tracking loop NCO

100 straight-through branch amplifiers;

101 loop filter totalizers; 110 integration branch amplifiers;

111 integration branch road totalizers; 112 integration branch road delay units.

(5) embodiment

As shown in Figure 1, a kind of intermediate frequency direct sequence spread spectrum receiver that is used for satellite ranging of the present invention, composition comprises: the front end analog-to-digital conversion module (is called for short front-end A/D) 10, in-phase branch multiplier 20, in-phase branch finite impulse response low-pass filter (being called for short in-phase branch FIR low-pass filter) 21, quadrature branch multiplier 30, quadrature branch finite impulse response low-pass filter (being called for short quadrature branch FIR low-pass filter) 31, integration zero clearing device 40, buffer 41, fast Fourier transform module (being called for short the FFT module) 42, branch road 1 complex multiplier 50, branch road 1 local pseudo-random code storage ROM (read-only memory) (being called for short branch road 1 local PN sign indicating number storage ROM) 51, branch road 1 inverse fast fourier transform module (being called for short branch road 1IFFT module) 52, branch road 1 mean square root module 53, branch road 2 complex multipliers 60, branch road 2 local pseudo-random code storage ROM (read-only memory) (being called for short branch road 2 local PN sign indicating number storage ROM) 61, branch road 2 inverse fast fourier transform modules (being called for short branch road 2IFFT module) 62, branch road 2 mean square root module 63, automatic threshold computing module 70, catch judge module 71, pseudo-random code reference position computing module (being called for short PN sign indicating number reference position computing module) 72, carrier frequency adjustment module 73, local pseudo-random code maker (being called for short local PN code generator) 80, correlator 81, code tracking loop mean square root module 82, code tracking loop phase detector 83, code tracking loop loop filter 84, code tracking loop totalizer 85, code tracking loop digital controlled oscillator (being called for short code tracking loop NCO) 86, code tracking loop Doppler effect correction module 87, carrier tracking loop frequency discrimination/phase detector 90, carrier tracking loop loop filter 91, carrier tracking loop totalizer 92 and carrier tracking loop digital controlled oscillator (being called for short carrier tracking loop NCO) 93.

Wherein code tracking loop loop filter 84 is identical with carrier tracking loop loop filter 91 inner structures, has only the parameter difference, as shown in Figure 2: comprise straight-through branch amplifier 100, loop filter totalizer 101, integration branch amplifier 110, integration branch road totalizer 111 and integration branch road delay unit 112.

Above-mentioned all constituents, except that front-end A/D10 used the ready-made product of putting on the shelf, remainder was all realized in programmable gate array (FPGA).

Described front-end A/D10 carries out bandpass sampling with constant sampling rate to the 70M intermediate frequency spread-spectrum signal after nursing one's health, and the simulating signal of importing is transformed to digital signal, and front-end A/D10 uses ready-made product.

Carrier tracking loop NCO 93 uses direct frequency synthesizing algorithm (being called for short the DDS algorithm) to realize, be responsible for producing fixedly local carrier of the two-way identical with nominal intermediate frequency behind front-end A/D10 bandpass sampling, 90 ° of the phase phasic differences of two-way carrier wave, the signal behind the bandpass sampling of the output of carrier tracking loop NCO 93 and front-end A/D10 output is as the input of in-phase branch multiplier 20 and quadrature branch multiplier 30; In-phase branch multiplier 20 and quadrature branch multiplier 30 use the inner IP kernel of FPGA to realize, use as low-converter, input signal is down-converted to zero intermediate frequency, and in-phase branch multiplier 20 enters identical in-phase branch FIR low-pass filter 21 of structure and quadrature branch FIR low-pass filter 31 respectively with the result of quadrature branch multiplier 30 outputs; In-phase branch FIR low-pass filter 21 and quadrature branch FIR low-pass filter 31 adopt the FIR Structure Filter, use the inner IP kernel of FPGA to realize, be responsible for the signal after the down coversion is carried out filtering, frequency multiplication component and out-of-band noise after the filtering down coversion drop to the noise power in the baseband signal lower.

Result after the low-pass filtering exports to integration zero clearing device 40 on the one hand, carries out sign indicating number and catches, and exports to correlator 81 on the other hand and is used for code tracking.Integration zero clearing device 40 carries out the integration zero clearing respectively to in-phase branch FIR low-pass filter 21 and quadrature branch FIR low-pass filter 31 filtered results under the local PN sign indicating number clock control that code tracking loop NCO86 produces.The result of integration zero clearing device 40 outputs enters buffer 41, and the signal to homophase and quadrature branch carries out buffer memory simultaneously in buffer 41, and to adapt to the requirement of 42 pairs of input data rates of follow-up FFT module, buffer 41 uses the inner IP kernel of FPGA to realize.The homophase of exporting behind buffer 41 buffer memorys and the result of quadrature branch as the real part and the imaginary part input of FFT module 42, carry out Fast Fourier Transform (FFT) respectively in FFT module 42, FFT module 42 uses the inner IP kernel of FPGA to realize.The real part of FFT module 42 and imaginary part output are as one tunnel input of branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60, and branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60 use the inner IP kernel of FPGA to realize.Another road input of branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60 is provided by branch road 1 local PN sign indicating number storage ROM51 and branch road 2 local PN sign indicating number storage ROM61 respectively.The output of FFT module 42 successively with local PN sign indicating number storage ROM51 of branch road 1 and branch road 2 local PN sign indicating numbers storage ROM61 in the local PN sign indicating number the stored result after through the FFT conversion carry out complex multiplication.Local PN sign indicating number storage ROM51 of branch road 1 and branch road 2 local PN sign indicating numbers storage ROM61 use the inner IP kernels of FPGA to realize, the data of inside solidification are the result after code phase differs half the local PN sign indicating number of the two-way sequence FFT conversion of FFT length.Result after branch road 1 complex multiplier 50 and branch road 2 complex multipliers 60 calculate sends into branch road 1IFFT module 52 respectively and branch road 2IFFT module 62 is carried out inverse fast fourier transform, and branch road 1IFFT module 52 and branch road 2IFFT module 62 use the inner IP kernel of FPGA to realize.Branch road 1 mean square root module 53 is sent in the output of branch road 1IFFT module 52 and branch road 2IFFT module 62 respectively and branch road 2 mean square root module 63 are calculated corresponding root-mean-square value, and the JPL approximate data is adopted in the calculating of root-mean-square value, promptly utilizes formula $\sqrt{a^2+b^2}\≈\mathrm{Max}(\mathrm{abs}\left(a\right),\mathrm{abs}\left(b\right))+\frac{1}{2}\left(\mathrm{Min}(\mathrm{abs}\left(s\right),\mathrm{abs}\left(b\right))\right)$ Calculate root-mean-square value, calculate after the root-mean-square value, automatic threshold computing module 70 is sent in the output of branch road 1 mean square root module 53 and branch road 2 mean square root module 63 simultaneously, the state computation of relevant peaks goes out suitable threshold value according to this moment, output and branch road 1 mean square root module 53 with automatic threshold computing module 70, the output of branch road 2 mean square root module 63 is sent into simultaneously and is caught judge module 71, catches thresholding and branch road 1 mean square root module 53 of judge module 71 by relatively automatic threshold module 70 outputs, the correlation peak of the output of branch road 2 mean square root module 63 judges whether band spread receiver catches.Catch the output of judge module 71 and send into PN sign indicating number reference position computing module 72 and carrier frequency adjustment module 73 respectively.

When catching judge module 71 when judging that the spread spectrum answering machines are not caught, band spread receiver is operated in trapped state, and carrier frequency adjustment module 73 is being searched for all after dates of a sign indicating number, can adjust the frequency separation of output, thereby adjust the frequency of carrier tracking loop NCO 93 outputs, until finish catch till.PN sign indicating number reference position computing module 72 not outputs this moment.When catching judge module 71 when judging that the spread spectrum answering machines have been caught, will make band spread receiver change tracking mode over to by trapped state.At this moment, carrier frequency adjustment module 73 can stop to adjust, simultaneously code tracking loop Doppler effect correction module 87 is sent in output this moment, code tracking loop Doppler effect correction module 87 is according to the proportionate relationship between spreading rate and the carrier frequency, produce corresponding PN sign indicating number Doppler effect correction component, be used to adjust the sign indicating number clock of code tracking loop NCO 86 outputs, the compensating for doppler effect is to the influence of spreading code.And PN sign indicating number reference position computing module 72 will calculate the reference position of local PN by the position of when locking relevant peaks, and result calculated is sent into local PN code generator 80, adjust the phase place of the local PN sequence that local PN code generator 80 produces.

Local PN code generator 80 produce leading (PN-), on schedule (PN), (PN+) three tunnel local PN sign indicating numbers lag behind, this three tunnel local PN sign indicating number is the phase difference of half chip phase each other, and three tunnel local PN sign indicating numbers enter correlator 81 backs simultaneously and carry out related operation with the output of in-phase branch FIR low-pass filter 21 and quadrature branch FIR low-pass filter 31.Three road correlated results of output are sent into code tracking loop mean square root module 82 simultaneously and are calculated root mean square.Wherein correlated results need be sent into carrier tracking loop frequency discrimination/phase detector 90 on schedule, carries out being used for carrier track behind frequency discrimination, the phase demodulation.The result of code tracking loop mean square root module 82 outputs enters code tracking loop phase detector 83 phase demodulations, phase-demodulating principle be relatively leading relevant result and lag correlation the result, the phase place of determining code tracking loop NCO86 still lags behind in advance, and the result of phase demodulation sends into code tracking loop loop filter 84.The main effect of code tracking loop loop filter 84 is the high fdrequency components in the filtering error signal; and provide the memory of a short-term for phase-locked loop; when loop because when instantaneous noise and losing lock; can guarantee loop lock-on signal again rapidly; code tracking loop loop filter 84 uses desirable firstorder filter; structure as shown in Figure 2; by two branch roads: straight-through branch road and integration branch road are formed; straight-through branch road only contains a straight-through branch amplifier 100; the multiple that input signal is amplified appointment gets final product; the integration branch road comprises integration branch amplifier 110; integration branch road unit delay unit 112 and integration branch road totalizer 111 are formed; the signal of input can enter the integration branch road when entering straight-through branch road; input is by the amplifier amplification back of integration branch road with through the results added after the time-delay of integration branch road delay unit; result's one side after the addition is as the input of integration branch road delay unit; on the other hand as the output of integration branch road; pass through 101 additions of loop filter totalizer with the output of straight-through branch road; result after two branch road additions is as the output of code tracking loop loop filter 84; 84 outputs of code tracking loop loop filter are sent into code tracking loop totalizer 85 simultaneously with the output of code tracking loop Doppler effect correction module 87 and are carried out sum operation; result after the addition sends into code tracking loop NCO 86; adjust output PN sign indicating number clock frequency, the local PN sign indicating number clock of feasible output and the sign indicating number clock synchronization that receives.

The correlated results on schedule of correlator 81 outputs is sent into carrier tracking loop frequency discrimination/phase detector 90, carries out frequency discrimination, phase demodulation.Carrier tracking loop frequency discrimination/phase detector 90 uses cross product frequency discrimination/phase demodulation algorithms, calculates the frequency difference between input signal carrier wave and the local carrier and differs.The frequency difference that calculates and differ incoming carrier tracking loop loop filter 91, the structure of carrier tracking loop loop filter 91 and code tracking loop loop filter 84 are identical, but coefficient is different.The output of the output of carrier tracking loop loop filter 91 and carrier frequency adjustment module 73 is incoming carrier tracking loop totalizer 92 together, the tracking loop of incoming carrier as a result NCO 93 after the summation follows the tracks of the carrier wave of input signal, finishes despreading, demodulation to the input spread-spectrum signal.

The intermediate frequency direct sequence spread spectrum receiver mainly utilizes the algorithm of FFT and line correlation to finish the catching of spreading code, and principle is: the discrete Fourier transformation of simple crosscorrelation sequence z (n) is:

$Z\left(k\right)=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}x\left(m\right)y(n+m)e^{-j2\mathrm{\πkn}/N}$

$=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}x\left(m\right)e^{j2\mathrm{\πkn}/N}\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}y(n+m)e^{-j2\mathrm{\πkn}/N}$

$=X^{*}\left(k\right)Y\left(k\right)$

Promptly the cross correlation value of two sequences can be carries out doing after complex conjugate multiplies each other contrary FFT conversion and obtains by calculating two sequence Fourier transform results.

Also line correlation is a kind of part correlation, need that at first the signal after sampling, down coversion, the filtering is carried out the integration zero clearing and reduce sampling rate, to simplify requirement to hardware, then the data after the integration zero clearing are carried out the FFT computing, with FFT computing output result in this locality the FFT value with reference to the PN sequence carry out complex multiplication, carry out contrary FFT computing afterwards, output is the multiple correlation result who receives PN signal and local PN signal.

The multiple correlation peak is carried out square law envelope detection (asking mould), and the thresholding at the line correlation peak of going forward side by side is judged to determine whether to obtain correct catching.If all do not obtain correct catching in the cycle at a spreading code, then show because the influence of frequency deviation has exceeded capture range, need to control the centre frequency of carrier tracking loop NCO 93 to next carrier frequency by carrier frequency adjustment module 73, carry out sign indicating number in cycle at a spreading code equally and catch, till obtaining correct catching.

Catch finish after, by catching judge module 71, receiver can calculate the reference position of spreading code, by this reference position, local PN maker 80 can generate and receive the local PN sign indicating number of PN sign indicating number near-synchronous, and phase differential between the two is within one half chip period.Local PN maker 80 produces on schedule simultaneously, lead and lag three road PN sign indicating numbers.

Tracking to the PN sign indicating number is to finish by digital delay phase-locked loop leading, that hysteresis serial correlator is constituted.

Claims (1)

1. intermediate frequency direct sequence spread spectrum receiver that is used for satellite ranging, it is characterized in that: its composition comprises: the front end analog-to-digital conversion module is front-end A/D (10), in-phase branch multiplier (20), in-phase branch finite impulse response low-pass filter is an in-phase branch FIR low-pass filter (21), quadrature branch multiplier (30), quadrature branch finite impulse response low-pass filter is a quadrature branch FIR low-pass filter (31), integration zero clearing device (40), buffer (41), fast Fourier transform module is FFT module (42), branch road 1 complex multiplier (50), branch road 1 local pseudo-random code storage ROM (read-only memory) is branch road 1 local PN sign indicating number storage ROM (51), branch road 1 inverse fast fourier transform module is a branch road 1IFFT module (52), branch road 1 mean square root module (53), branch road 2 complex multipliers (60), branch road 2 local pseudo-random code storage ROM (read-only memory) are branch road 2 local PN sign indicating number storage ROM (61), branch road 2 inverse fast fourier transform modules are branch road 2IFFT module (62), branch road 2 mean square root module (63), automatic threshold computing module (70), catch judge module (71), pseudo-random code reference position computing module is a PN sign indicating number reference position computing module (72), carrier frequency adjustment module (73), the local PN code generator (80) of local pseudo-random code maker, correlator (81), code tracking loop mean square root module (82), code tracking loop phase detector (83), code tracking loop loop filter (84), code tracking loop totalizer (85), the code tracking loop digital controlled oscillator is code tracking loop NCO (86), code tracking loop Doppler effect correction module (87), carrier tracking loop frequency discrimination/phase detector (90), carrier tracking loop loop filter (91), carrier tracking loop totalizer (92) and carrier tracking loop digital controlled oscillator are carrier tracking loop NCO (93);

Wherein code tracking loop loop filter (84) is identical with carrier tracking loop loop filter (91) inner structure, have only the parameter difference, comprise straight-through branch amplifier (100), loop filter totalizer (101), integration branch amplifier (110), integration branch road totalizer (111) and integration branch road delay unit (112);

Above-mentioned all constituents, except that front-end A/D (10) used the ready-made product of putting on the shelf, remainder was to realize among the FPGA at programmable gate array all;

Described front-end A/D (10) carries out bandpass sampling with constant sampling rate to the 70M intermediate frequency spread-spectrum signal after nursing one's health, and the simulating signal of importing is transformed to digital signal, and front-end A/D (10) uses ready-made product;

It is that the DDS algorithm is realized that carrier tracking loop NCO (93) uses the direct frequency synthesizing algorithm, be responsible for producing fixedly local carrier of the two-way identical with nominal intermediate frequency behind front-end A/D (10) bandpass sampling, 90 ° of the phase phasic differences of two-way carrier wave, the signal behind the bandpass sampling of the output of carrier tracking loop NCO 93 and front-end A/D (10) output is as the input of in-phase branch multiplier (20) and quadrature branch multiplier (30); In-phase branch multiplier (20) and quadrature branch multiplier (30) use the inner IP kernel of FPGA to realize, use as low-converter, input signal is down-converted to zero intermediate frequency, and in-phase branch multiplier (20) enters identical in-phase branch FIR low-pass filter (21) of structure and quadrature branch FIR low-pass filter (31) respectively with the result of quadrature branch multiplier (30) output; In-phase branch FIR low-pass filter (21) and quadrature branch FIR low-pass filter (31) adopt the FIR Structure Filter, use the inner IP kernel of FPGA to realize, be responsible for the signal after the down coversion is carried out filtering, frequency multiplication component and out-of-band noise after the filtering down coversion drop to the noise power in the baseband signal lower;

Result after the low-pass filtering exports to integration zero clearing device (40) on the one hand, carries out sign indicating number and catches, and exports to correlator (81) on the other hand and is used for code tracking; Integration zero clearing device (40) carries out the integration zero clearing respectively to in-phase branch FIR low-pass filter (21) and the filtered result of quadrature branch FIR low-pass filter (31) under the local PN sign indicating number clock control that code tracking loop NCO (86) produces; The result of integration zero clearing device (40) output enters buffer (41), signal to homophase and quadrature branch carries out buffer memory simultaneously in buffer (41), to adapt to the requirement of follow-up FFT module (42) to input data rate, buffer (41) uses the inner IP kernel of FPGA to realize; The homophase of exporting behind buffer (41) buffer memory and the result of quadrature branch as the real part and the imaginary part input of FFT module (42), carry out Fast Fourier Transform (FFT) respectively in FFT module (42), FFT module (42) uses the inner IP kernel of FPGA to realize; The real part of FFT module (42) and imaginary part output are as one tunnel input of branch road 1 complex multiplier (50) and branch road 2 complex multipliers (60), and branch road 1 complex multiplier (50) and branch road 2 complex multipliers (60) use the inner IP kernel of FPGA to realize; Another road input of branch road 1 complex multiplier (50) and branch road 2 complex multipliers (60) is provided by branch road 1 local PN sign indicating number storage ROM (51) and branch road 2 local PN sign indicating number storage ROM (61) respectively; The output of FFT module (42) successively with local PN sign indicating number storage ROM (51) of branch road 1 and branch road 2 local PN sign indicating numbers storage ROM (61) in result after the local PN sign indicating number process FFT conversion of storage carry out complex multiplication; Local PN sign indicating number storage ROM (51) of branch road 1 and branch road 2 local PN sign indicating numbers storage ROM (61) use the inner IP kernels of FPGA to realize, the data of inside solidification are the result after code phase differs half the two-way this locality PN sign indicating number sequence FFT conversion of FFT length; Result after branch road 1 complex multiplier (50) and branch road 2 complex multipliers (60) calculate sends into branch road 1IFFT module (52) respectively and branch road 2IFFT module (62) is carried out inverse fast fourier transform, and branch road 1IFFT module (52) and branch road 2IFFT module (62) use the inner IP kernel of FPGA to realize; Branch road 1 mean square root module (53) is sent in the output of branch road 1IFFT module (52) and branch road 2IFFT module (62) respectively and branch road 2 mean square root module (63) are calculated corresponding root-mean-square value, and the JPL approximate data is adopted in the calculating of root-mean-square value, promptly utilizes formula $\sqrt{a^2+b^2}\≈\mathrm{Max}(\mathrm{abs}\left(a\right),\mathrm{abs}\left(b\right))+\frac{1}{2}\left(\mathrm{Min}(\mathrm{abs}\left(a\right),\mathrm{abs}\left(b\right))\right)$ Calculate root-mean-square value, calculate after the root-mean-square value, automatic threshold computing module (70) is sent in the output of branch road 1 mean square root module (53) and branch road 2 mean square root module (63) simultaneously, the state computation of relevant peaks goes out suitable threshold value according to this moment, output and branch road 1 mean square root module (53) with automatic threshold computing module (70), the output of branch road 2 mean square root module (63) is sent into simultaneously and is caught judge module (71), catches thresholding and branch road 1 mean square root module (53) of judge module (71) by relatively automatic threshold module (70) output, the correlation peak of the output of branch road 2 mean square root module (63) judges whether band spread receiver catches; Catch the output of judge module (71) and send into PN sign indicating number reference position computing module (72) and carrier frequency adjustment module (73) respectively;

When catching judge module (71) when judging that the spread spectrum answering machine is not caught, band spread receiver is operated in trapped state, carrier frequency adjustment module (73) is being searched for all after dates of a sign indicating number, can adjust the frequency separation of output, thereby adjust the frequency of carrier tracking loop NCO (93) output, until finish catch till; PN sign indicating number reference position computing module this moment (72) is output not; When catching judge module (71) when judging that the spread spectrum answering machine has been caught, will make band spread receiver change tracking mode over to by trapped state; At this moment, carrier frequency adjustment module (73) can stop to adjust, simultaneously code tracking loop Doppler effect correction module (87) is sent in output this moment, code tracking loop Doppler effect correction module (87) is according to the proportionate relationship between spreading rate and the carrier frequency, produce corresponding PN sign indicating number Doppler effect correction component, be used to adjust the sign indicating number clock of code tracking loop NCO (86) output, the compensating for doppler effect is to the influence of spreading code; And PN sign indicating number reference position computing module (72) will calculate the reference position of local PN by the position of when locking relevant peaks, and result calculated is sent into local PN code generator (80), adjust the phase place of the local PN sequence that local PN code generator (80) produces;

Local PN code generator (80) produce leading (PN-), on schedule (PN), (PN+) three tunnel local PN sign indicating numbers lag behind, this three tunnel local PN sign indicating number is the phase difference of half chip phase each other, and three tunnel local PN sign indicating numbers enter correlator (81) back simultaneously and carry out related operation with the output of in-phase branch FIR low-pass filter (21) and quadrature branch FIR low-pass filter (31); Three road correlated results of output are sent into code tracking loop mean square root module (82) simultaneously and are calculated root mean square; Wherein correlated results need be sent into carrier tracking loop frequency discrimination/phase detector (90) on schedule, carries out being used for carrier track behind frequency discrimination, the phase demodulation; The result of code tracking loop mean square root module (82) output enters code tracking loop phase detector (83) phase demodulation, phase-demodulating principle be relatively leading relevant result and lag correlation the result, the phase place of determining code tracking loop NCO (86) still lags behind in advance, and the result of phase demodulation sends into code tracking loop loop filter (84); The main effect of code tracking loop loop filter (84) is the high fdrequency component in the filtering error signal, and provide the memory of a short-term for phase-locked loop, when loop because when instantaneous noise and losing lock, can guarantee loop lock-on signal again rapidly, code tracking loop loop filter (84) uses desirable firstorder filter, by two branch roads: straight-through branch road and integration branch road are formed, straight-through branch road only contains a straight-through branch amplifier (100), the multiple that input signal is amplified appointment gets final product, the integration branch road comprises integration branch amplifier (110), integration branch road unit delay unit (112) and integration branch road totalizer (111) are formed, the signal of input can enter the integration branch road when entering straight-through branch road, input is by the amplifier amplification back of integration branch road with through the results added after the time-delay of integration branch road delay unit, result's one side after the addition is as the input of integration branch road delay unit, on the other hand as the output of integration branch road, pass through loop filter totalizer (101) addition with the output of straight-through branch road, result after two branch road additions is as the output of code tracking loop loop filter (84), code tracking loop loop filter (84) output is sent into code tracking loop totalizer (85) simultaneously with the output of code tracking loop Doppler effect correction module 87 and is carried out sum operation, result after the addition sends into code tracking loop NCO (86), adjust output PN sign indicating number clock frequency, the local PN sign indicating number clock of feasible output and the sign indicating number clock synchronization that receives;

The correlated results on schedule of correlator (81) output is sent into carrier tracking loop frequency discrimination/phase detector (90), carries out frequency discrimination, phase demodulation; Carrier tracking loop frequency discrimination/phase detector (90) uses cross product frequency discrimination/phase demodulation algorithm, calculates the frequency difference between input signal carrier wave and the local carrier and differs; The frequency difference that calculates and differ incoming carrier tracking loop loop filter (91), the structure of carrier tracking loop loop filter (91) and code tracking loop loop filter (84) are identical, but coefficient is different; The output of the output of carrier tracking loop loop filter (91) and carrier frequency adjustment module (73) is incoming carrier tracking loop totalizer (92) together, the tracking loop of incoming carrier as a result NCO (93) after the summation follows the tracks of the carrier wave of input signal, finishes despreading, demodulation to the input spread-spectrum signal.

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