CN115498079A - Light emitting diode and semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 46
- 230000000903 blocking effect Effects 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 257
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000004020 luminiscence type Methods 0.000 description 7
- 230000006798 recombination Effects 0.000 description 7
- 238000005215 recombination Methods 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000010030 laminating Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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Abstract
The invention provides a light emitting diode and a semiconductor device, the light emitting diode includes: the light-emitting diode comprises a substrate, a buffer layer, an N-type gallium nitride layer, a light-emitting zone buffer layer, a first light-emitting layer, a second light-emitting layer, an electronic barrier layer and a P-type gallium nitride layer, wherein the buffer layer, the N-type gallium nitride layer, the light-emitting zone buffer layer, the first light-emitting layer, the second light-emitting layer, the electronic barrier layer and the P-type gallium nitride layer are epitaxially grown on the substrate in sequence; the thickness of the buffer layer of the light emitting area is a preset first multiple of the thickness of the light emitting well-barrier pair sub-layer; the thickness of the first light-emitting layer is a preset second multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the second multiple is smaller than the first multiple; the thickness of the electron blocking layer is a preset third multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the third multiple is smaller than the first multiple. The internal luminous efficiency of the light emitting diode can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a Light-Emitting Diode (LED) and a semiconductor device.
Background
The gallium nitride-based LED emits light by utilizing the characteristic that visible light is radiated when electrons and holes are compounded, has the characteristics of energy conservation, long service life, small volume and the like, is widely applied to the field of illumination, and can be used for displaying, indicating, decorating, illuminating equipment and the like. However, the internal light emitting efficiency of the current LED with the epitaxial structure is generally between 50% and 80%, the light emitting efficiency is not high, especially, the epitaxial structure includes more functional layers, and the unreasonable matching between the functional layers affects each other, especially, the matching between the light emitting layer and the electron blocking layer and the internal structure of the light emitting layer causes a part of carriers to generate non-composite radiation increase, which affects the light emitting efficiency of the LED.
Disclosure of Invention
In view of the above, the present invention provides a light emitting diode and a semiconductor device to improve the internal light emitting efficiency of the light emitting diode.
In a first aspect, an embodiment of the present invention provides a light emitting diode, including:
a substrate, a buffer layer, an N-type gallium nitride layer, a buffer layer of a light-emitting region, a first light-emitting layer, a second light-emitting layer, an electron blocking layer and a P-type gallium nitride layer which are epitaxially grown on the substrate in sequence,
the second light emitting layer includes one or more light emitting well-barrier pair layers;
the thickness of the buffer layer of the light emitting area is a preset first multiple of the thickness of the light emitting well-barrier pair sub-layer;
the thickness of the first light-emitting layer is a preset second multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the second multiple is smaller than the first multiple;
the thickness of the electron blocking layer is a preset third multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the third multiple is smaller than the first multiple.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where,the thickness of the light-emitting trap-barrier pair layer is
The first multiple is 20-40, the second multiple is 2.5-8, and the third multiple is 1-6.
With reference to the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where a thickness of the light-emitting well-barrier pair layer is
The first multiple is 25-40, the second multiple is 3-8, and the third multiple is 2-6.
In combination with the first possible implementation manner of the first aspect, the present invention provides a third possible implementation manner of the first aspect, wherein the light emitting region buffer layer has a thickness of
The first light-emitting layer has a thickness of
The thickness of the electron blocking layer is
With reference to the second possible implementation manner of the first aspect, the present invention provides a fourth possible implementation manner of the first aspect, wherein the light emitting area buffer layer has a thickness of
The first light-emitting layer has a thickness of
The electron blocking layer has a thickness of
With reference to the first aspect, embodiments of the present invention provide a fifth possible implementation manner of the first aspect, where the light emitting region buffer layer, the first light emitting layer, and the second light emitting layer are all n-type doped nitride semiconductors containing Al and In, where an average concentration of Al atoms In the second light emitting layer > an average concentration of Al atoms In the first light emitting layer > an average concentration of Al atoms In the light emitting region buffer layer.
In combination with the fifth possible implementation manner of the first aspect, this embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein the average concentration of In atoms In the second light-emitting layer > the average concentration of In atoms In the first light-emitting layer > the average concentration of In atoms In the light-emitting region buffer layer.
With reference to the sixth possible implementation manner of the first aspect, this embodiment of the present invention provides a seventh possible implementation manner of the first aspect, where the average concentration of n-type impurity atoms in the light emitting region buffer layer > the average concentration of n-type impurity atoms in the second light emitting layer ≧ the average concentration of n-type impurity atoms in the first light emitting layer.
In combination with the sixth possible implementation manner of the first aspect, the embodiment of the present invention provides an eighth possible implementation manner of the first aspect, wherein the light emitting region buffer layer includes one or more pairs of sub-layers epitaxially grown In sequence, and an In content of a previous pair of sub-layers In the light emitting region buffer layer is smaller than an In content of a next pair of sub-layers.
With reference to the first aspect, an embodiment of the present invention provides a ninth possible implementation manner of the first aspect, where the second light emitting layer includes: a first light emitting well-barrier pair layer and a second light emitting well-barrier pair layer, the first light emitting well-barrier pair layer comprising: the second light-emitting trap-barrier pair sub-layer comprises: a second light emitting well sub-layer and a second light emitting barrier sub-layer, wherein,
the first light-emitting well sub-layer is epitaxially grown on the first light-emitting layer, the first light-emitting barrier sub-layer is epitaxially grown on the first light-emitting well sub-layer, the second light-emitting well sub-layer is epitaxially grown on the first light-emitting barrier sub-layer, and the second light-emitting barrier sub-layer is epitaxially grown on the second light-emitting well sub-layer.
The light emitting well-barrier pair layer includes: the second light-emitting layer is of a periodic structure formed by alternately laminating the light-emitting well sub-layers and the barrier sub-layers.
Preferably, the N-type impurity is silicon, and the molar concentration of silicon atoms in the N-type gallium nitride layer is 10 18 /cm 3 ～10 21 /cm 3 The molar concentration of silicon atoms in the buffer layer of the light emitting region is 10 18 /cm 3 ～10 19 /cm 3 The molar concentration of silicon atoms in the second light-emitting layer is 10 17 /cm 3 ～10 18 /cm 3 The molar concentration of silicon atoms in the first light-emitting layer is 10 17 /cm 3 ～10 19 /cm 3 。
Still further, the light emitting well-barrier pair sub-layer includes: the second light-emitting layer is a periodic structure formed by alternately laminating the light-emitting well sub-layer and the barrier sub-layer, and the period number is 3-15.
In a second aspect, the embodiment of the invention also provides a semiconductor device, which includes the light emitting diode as described above.
The embodiment of the invention provides a light-emitting diode and a semiconductor device, wherein the light-emitting diode comprises: the light emitting diode comprises a substrate, a buffer layer, an N-type gallium nitride layer, a light emitting zone buffer layer, a first light emitting layer, a second light emitting layer, an electron blocking layer and a P-type gallium nitride layer which are epitaxially grown on the substrate in sequence, wherein the second light emitting layer comprises one or more light emitting trap-barrier pair layers; the thickness of the buffer layer of the light emitting area is a preset first multiple of the thickness of the light emitting well-barrier pair sub-layer; the thickness of the first light-emitting layer is a preset second multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the second multiple is smaller than the first multiple; the thickness of the electron blocking layer is a preset third multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the third multiple is smaller than the first multiple.
And simultaneously adjusting the concentration relationship among Al atoms, n-type impurities and In atoms In the buffer layer, the first light-emitting layer and the second light-emitting layer In the light-emitting region. Therefore, the thicknesses of the buffer layer, the first light-emitting layer and the electron blocking layer of the light-emitting region are associated with the thickness of the second light-emitting layer by optimizing the optimal matching thickness of each layer from the buffer layer to the P-type GaN layer, so that the matching performance of mutual influence among the layers is optimized, and the internal light-emitting efficiency of the light-emitting diode can be effectively improved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram illustrating a light emitting diode structure provided by an embodiment of the invention;
fig. 2 is a schematic diagram illustrating a relationship between light emitting efficiency and a buffer layer in a light emitting region with different thicknesses, based on the thicknesses of the light emitting well-barrier pair layer in the light emitting diode according to the embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a relationship between light emitting efficiencies of second light emitting layers with different thicknesses in the light emitting diode according to the embodiment of the present invention, based on the thicknesses of the light emitting well-barrier pair layers;
fig. 4 is a schematic diagram illustrating a relationship between light emitting efficiencies of electron blocking layers with different thicknesses based on thicknesses of a light emitting well-barrier pair layer in the light emitting diode according to the embodiment of the present invention;
fig. 5 shows a schematic structural diagram of a semiconductor device provided by an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
In the existing LED, because the epitaxial structure is generally made of gallium nitride, the concentration of n-type electrons is high, and the mobility is high, and in the P-type gallium nitride layer on the light-emitting layer, the concentration of carriers of holes is low, and the mobility is low, electrons often overflow into the P-type gallium nitride layer, and a part of carriers generated by the P-type gallium nitride layer are non-radiatively combined with the electrons, so that the internal light-emitting efficiency is reduced. In addition, because the materials adopted by each layer of the epitaxial structure are different, the corresponding lattice constants are different, stress is generated due to mismatching of the lattice constants, and the polarization field intensity caused by the stress can also reduce the internal luminous efficiency of the LED. In the embodiment of the invention, aiming at the problems that the epitaxial structure contains more layers and the mutual influence among the layers is restricted, under the condition of fully considering the mutual influence among the layers, the thickness of each layer of the epitaxial structure is optimized, the probability of non-radiative recombination of current carriers and electrons is reduced, and the material of each layer is optimized, the influence of stress generated by mismatching of lattice constants of each layer on the internal luminous efficiency is reduced, so that the internal luminous efficiency of the LED is improved.
Embodiments of the present invention provide a light emitting diode and a semiconductor device, which are described below by way of examples.
Fig. 1 shows a schematic structural diagram of a light emitting diode provided in an embodiment of the present invention. As shown in fig. 1, the light emitting diode 100 includes:
a substrate 101, a buffer layer 102 epitaxially grown on the substrate 101, an N-type gallium nitride (GaN) layer 103, a light emitting region buffer layer 104, a first light emitting layer 105, a second light emitting layer 106, an electron blocking layer 107, and a P-type gallium nitride layer 108, wherein,
the second light emitting layer 106 includes one or more light emitting well-barrier pair layers;
the thickness of the light emitting region buffer layer 104 is a preset first multiple of the thickness of the light emitting well-barrier pair sub-layer;
the thickness of the first light-emitting layer 105 is a preset second multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the second multiple is smaller than the first multiple;
the thickness of the electron blocking layer 107 is a preset third multiple of the thickness of the luminescence well-barrier pair sub-layer, and the third multiple is smaller than the first multiple.
In this embodiment of the present invention, as an alternative embodiment, the structure of the first light emitting layer 105 is the same as that of the second light emitting layer 106, and each of the first light emitting layer and the second light emitting layer includes one or more light emitting well-barrier pair sub-layers, except that the light emitting well-barrier pair sub-layers have different contents of some components in materials.
In the embodiment of the present invention, as an optional embodiment, the light-emitting well-barrier pair layer includes: the second light-emitting layer is a periodic structure formed by alternately laminating the light-emitting well sub-layer and the barrier sub-layer. As an alternative embodiment, the number of cycles is 3 to 15.
In this embodiment of the present invention, as an optional embodiment, the number of layers of the light emitting well-barrier pair sub-layers is 2, and the second light emitting layer 106 includes: a first luminescence well-barrier pair sublayer 1061 and a second luminescence well-barrier pair sublayer 1062, the first luminescence well-barrier pair sublayer 1061 comprising: a first luminescence well sublayer 10611 and a first luminescence barrier sublayer 10612, and a second luminescence well-barrier sublayer 1062 includes: a second light emitting well sub-layer 10621, and a second light emitting barrier sub-layer 10622, wherein,
the first light emitting well sublayer 10611 is epitaxially grown on the first light emitting layer 105, the first light emitting barrier sublayer 10612 is epitaxially grown on the first light emitting well sublayer 10611, the second light emitting well sublayer 10621 is epitaxially grown on the first light emitting barrier sublayer 10612, and the second light emitting barrier sublayer 10622 is epitaxially grown on the second light emitting well sublayer 10621.
In the embodiment of the present invention, in the case where the second light emitting layer 106 includes more light emitting well-barrier pair layers, the light emitting well-barrier pair layers are epitaxially grown in sequence.
In an embodiment of the present invention, as an optional embodiment, the N-type GaN layer is made of GaN, the light emitting well sublayer is made of InGaN, the barrier sublayer is made of GaN, the light emitting region buffer layer includes one or more sublayer pairs epitaxially grown in sequence, and each sublayer pair includes: the GaN-based LED comprises a GaN sublayer and an InGaN sublayer, wherein the GaN sublayer is made of GaN, the InGaN sublayer is made of InGaN, and the In content of a light emitting zone buffer layer is smaller than that of a light emitting well sublayer of the first light emitting layer. Therefore, the light emitting zone buffer layer is used as a transition layer between the N-type GaN layer and the light emitting well sublayer of the first light emitting layer, and the In content In the light emitting zone buffer layer is smaller than that of the light emitting well sublayer of the first light emitting layer, so that lattice mutation (stress) caused by different materials (different lattice constants) of the N-type GaN layer and the light emitting well sublayer In the first light emitting layer can be effectively relieved, the stress generated by mismatching of the lattice constants of the N-type GaN layer and the first light emitting layer can be released, and the influence of polarization field intensity caused by the stress on the light emitting efficiency can be reduced.
In the embodiment of the present invention, as an optional embodiment, the thickness of the light emitting well-barrier pair layer is set to be
The first multiple is 20-40, the second multiple is 2.5-8, and the third multiple is 1-6. As another preferred alternative, the thickness of the luminescent trap-barrier pair layer is set to optimize the radiative recombination efficiency
The first multiple is 25-40, the second multiple is 3-8, and the third multiple is 2-6.
In the embodiment of the present invention, as an optional embodiment, the thickness of the light emitting region buffer layer 104 is
Within the thickness range, stress generated by mismatch of lattice constants of the N-type GaN layer and the light emitting well sub-layer in the first light emitting layer can be released to the maximum extent, and defects generated at the interface of the N-type GaN layer and the light emitting region buffer layer can be prevented from growing continuously. If the thickness of the light emitting region buffer layer 104 is smaller than the thickness range, the stress release is insufficient, and if the thickness exceeds the thickness range, the light emitting angle is changed, and the light emitting efficiency of the LED is affected.
In the embodiment of the invention, as an optional embodiment, if the thickness of the light emitting region buffer layer 104 is as follows
The first light-emitting layer 105 is provided with a thickness of
The electron blocking layer 107 has a thickness of
As a preferred alternative, if the thickness of the light emitting region buffer layer 104 is as thick as
The first light-emitting layer 105 is provided with a thickness of
The electron blocking layer 107 has a thickness of
In this embodiment, as an optional embodiment, the light-emitting region buffer layer, the first light-emitting layer, and the second light-emitting layer are all n-type doped nitride semiconductors containing Al and In, where an average concentration of Al atoms In the second light-emitting layer > an average concentration of Al atoms In the first light-emitting layer > an average concentration of Al atoms In the light-emitting region buffer layer.
In this embodiment, as an optional embodiment, an average concentration of In atoms In the second light emitting layer is greater than an average concentration of In atoms In the first light emitting layer, and an average concentration of In atoms In the first light emitting layer is greater than an average concentration of In atoms In the buffer layer In the light emitting layer. In another alternative embodiment, the average concentration of n-type impurity atoms in the light emitting region buffer layer > the average concentration of n-type impurity atoms in the second light emitting layer ≧ the average concentration of n-type impurity atoms in the first light emitting layer.
In the embodiment of the invention, the buffer layer of the light emitting region, the first light emitting layer and the second light emitting layer all contain a certain amount of In, so that the crystal quality is not high, and the defects generated from the bottom layer (the substrate, the buffer layer and the N-type GaN layer) can not be covered but can be continuously amplified and increased, so that as an optional embodiment for improving the performance, the material of the electron blocking layer is GaN containing a dopant, wherein the dopant is one or any combination of Si, mg, in and Al, so that the forbidden bandwidth of the electron blocking layer can be increased, the blocking effect on electrons is improved, the good crystal growth quality of the GaN of the electron blocking layer is utilized, the defect filling effect is improved, and the thicker the thickness of the GaN of the electron blocking layer is, the better the filling effect is; on the other hand, since the electron blocking layer contains dopant components such as Al, the energy barrier is higher, the thicker the thickness is, the more significant the energy barrier effect is, the stronger the blocking of holes is, so that the holes entering the second light emitting layer are fewer, and the radiative recombination efficiency is reduced, therefore, as an optional embodiment, the third multiple is 1 to 6, in this thickness range, the epitaxial wafer can have both an excellent surface and a better energy barrier effect, and if the thickness is less than this thickness range, the coverage of defects derived from the lower layer (layer below the electron blocking layer) is insufficient, and the control of the electron overflow phenomenon is insufficient, so that the radiative recombination efficiency is poor; if the thickness is larger than the above range, absorption of photons and blocking of holes are caused by the generation of a light absorption phenomenon and an excessively strong energy barrier effect, thereby affecting the radiative recombination efficiency.
In the embodiment of the invention, the buffer layer is made of GaN or AlGaN.
In the embodiment of the invention, the N-type impurity is silicon, and as an optional embodiment, in the N-type GaN layer, silicon (Si) doping is carried out in GaN, and the molar concentration of doped Si atoms is 10 18 /cm 3 ～10 21 /cm 3 。
In the embodiment of the present invention, the light emitting region buffer layer may include one or more sub-layer pairs sequentially epitaxially grown, wherein the In content of the InGaN sub-layer In the former sub-layer pair is smaller than that of the InGaN sub-layer In the latter sub-layer pair. As an alternative embodiment, the InGaN used for the light emitting region buffer layer may include a superlattice structure, and the GaN and InGaN may further include a dopant, where the dopant is one or any combination of Al and Si, and the molar concentration of silicon atoms in the light emitting region buffer layer is 10 18 /cm 3 ～10 19 /cm 3 。
In an embodiment of the present invention, as an optional embodiment, the material used in the first light emitting layer may include a superlattice structure, and Al and/or Si may also be doped in the material, where a molar concentration of Si atoms is 10 17 /cm 3 ～10 19 /cm 3 。
In the embodiment of the present invention, as an optional embodiment, in the material adopted by the second light emitting layer, doping Al and/or Si is performed, wherein the molar concentration of silicon atoms in the second light emitting layer is 10 17 /cm 3 ～10 18 /cm 3 。
In embodiments of the present invention, the electron blocking layer may comprise one or more sub-layers.
In the embodiment of the invention, the P-type GaN layer is made of GaN, and Mg and/or Si can be doped in the GaN.
In the embodiment of the invention, the optimal matching thicknesses of all the layers from the buffer layer to the P-type GaN layer are optimized, so that the thicknesses of the buffer layer, the first light-emitting layer and the electronic barrier layer of the light-emitting region are associated with the second light-emitting layer, the matching performance of mutual influence among all the layers is optimized, the stress mismatch generated by thickness mismatch among all the layers of the epitaxial structure is reduced, carrier non-radiation recombination caused by the stress mismatch is reduced, the radiation recombination efficiency is improved, and meanwhile, the influence of the stress generated by lattice constant mismatch of all the layers on the internal light-emitting efficiency is reduced by optimizing the materials of all the layers of the epitaxial structure, so that the internal light-emitting efficiency is improved.
Fig. 2 is a schematic diagram illustrating a relationship between light emitting efficiency and a buffer layer in a light emitting region with different thicknesses, based on the thicknesses of the light emitting well-barrier pair layer in the light emitting diode according to the embodiment of the present invention. As shown in fig. 2, the thickness of the Light-emitting well-barrier pair layer is MQW Thx, and MQW Thx 15 to 20 indicates that the thickness of the Light-emitting region buffer layer is 15 to 20 times the thickness of the Light-emitting well-barrier pair layer, and the Light-emitting region buffer layer thickness is adjusted to MQW Thx 15 to 50, whereby the Light emission efficiency (LOP) can be maintained at 85% or more, and particularly, the LOP approaches 100% when the thickness of the Light-emitting region buffer layer is MQW Thx 25 to 40.
Fig. 3 is a schematic diagram illustrating a relationship between light emitting efficiencies of second light emitting layers with different thicknesses in the light emitting diode according to the embodiment of the present invention, based on the thicknesses of the light emitting well-barrier pair layers. As shown in fig. 3, all the LOPs are higher than 94%, and especially, the LOPs are close to 100% when the second light-emitting layer has a thickness of MQW Thx 2.5 to 8.
Fig. 4 is a schematic diagram illustrating a relationship between light emitting efficiencies of electron blocking layers with different thicknesses in the light emitting diode according to the embodiment of the present invention, based on the thicknesses of the light emitting well-barrier pair layer. As shown in fig. 4, the LOP is higher than 97%, and especially, the LOP is close to 100% when the electron blocking layer has a thickness of MQW Thx 1 to 6.
The present invention further provides a semiconductor device 200 including the light emitting diode 100 formed by the above-mentioned embodiment, and in an embodiment, referring to fig. 5, the semiconductor device 200 is a front-mounted LED structure, which includes a P electrode 201 disposed on and electrically connected to the P-type gallium nitride layer 108, and an N electrode 202 disposed on and electrically connected to the N-type gallium nitride layer.
When the P-electrode 201 and the N-electrode 202 are externally connected to a power supply, electrons generated in the N-type gallium nitride layer 103 diffuse in the positive direction into the light-emitting layers (105, 106), and holes in the P-type gallium nitride layer 108 diffuse in the negative direction into the light-emitting layers (105, 106). Electrons and holes entering the light-emitting layer (105, 106) are confined in the light-emitting layer (105, 106) by the heterojunction barrier layer, and spontaneous emission light is generated when electrons recombine with holes via transition.
Further, in order to increase the amount of light emitted from the front surface of the semiconductor device 200, a reflective layer 203, which is a distributed bragg reflective layer or a metal reflective layer having a high reflectivity, is generally disposed on the back surface of the substrate 101.
In another embodiment, the light emitting diode 100 may further form the semiconductor device 200 having another structure, such as a flip-chip structure LED, a high voltage structure LED, a vertical structure LED, or a lighting device including the light emitting diode 100, through an etching process, an evaporation process, a grinding process, or the like.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present application. Are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A light emitting diode, comprising:
a substrate, a buffer layer, an N-type gallium nitride layer, a buffer layer of a light-emitting region, a first light-emitting layer, a second light-emitting layer, an electron blocking layer and a P-type gallium nitride layer which are epitaxially grown on the substrate in sequence,
the second light emitting layer includes one or more light emitting well-barrier pair layers;
the thickness of the buffer layer of the light emitting area is a preset first multiple of the thickness of the light emitting well-barrier pair sub-layer;
the thickness of the first light-emitting layer is a preset second multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the second multiple is smaller than the first multiple;
the thickness of the electron blocking layer is a preset third multiple of the thickness of the light-emitting well-barrier pair sub-layer, and the third multiple is smaller than the first multiple.
2. The led of claim 1, wherein said light emitting well-barrier pair layer has a thickness of
The first multiple is 20-40, the second multiple is 2.5-8, and the third multiple is 1-6.
3. The led of claim 1, wherein said light emitting well-barrier pair layer has a thickness of
The first multiple is 25-40, the second multiple is 3-8, and the third multiple is 2-6.
4. The led of claim 2, wherein the light emitting region buffer layer has a thickness of
The first light-emitting layer has a thickness of
The thickness of the electron blocking layer is
5. The led of claim 3, wherein the light emitting region buffer layer has a thickness of
The first light-emitting layer has a thickness of
The thickness of the electron blocking layer is
6. The light-emitting diode according to claim 1, wherein the light-emitting region buffer layer, the first light-emitting layer, and the second light-emitting layer are each an n-type doped nitride semiconductor containing Al and In, and wherein an average concentration of Al atoms In the second light-emitting layer > an average concentration of Al atoms In the first light-emitting layer > an average concentration of Al atoms In the light-emitting region buffer layer.
7. The light-emitting diode according to claim 6, wherein an average concentration of In atoms In the second light-emitting layer > an average concentration of In atoms In the first light-emitting layer > an average concentration of In atoms In the light-emitting region buffer layer.
8. The LED of claim 7, wherein the average concentration of n-type impurity atoms in the buffer layer at the light-emitting region > the average concentration of n-type impurity atoms in the second light-emitting layer ≧ the average concentration of n-type impurity atoms in the first light-emitting layer.
9. The light-emitting diode according to claim 7, wherein the light-emitting region buffer layer comprises one or more pairs of sub-layers epitaxially grown In sequence, and wherein an In content of a preceding pair of sub-layers In the light-emitting region buffer layer is smaller than an In content of a succeeding pair of sub-layers.
10. The light-emitting diode according to any one of claims 1, wherein the second light-emitting layer comprises: a first light emitting well-barrier pair layer and a second light emitting well-barrier pair layer, the first light emitting well-barrier pair layer comprising: the second light-emitting trap-barrier pair sub-layer comprises: a second light emitting well sub-layer and a second light emitting barrier sub-layer, wherein,
the first light-emitting well sub-layer is epitaxially grown on the first light-emitting layer, the first light-emitting barrier sub-layer is epitaxially grown on the first light-emitting well sub-layer, the second light-emitting well sub-layer is epitaxially grown on the first light-emitting barrier sub-layer, and the second light-emitting barrier sub-layer is epitaxially grown on the second light-emitting well sub-layer.
11. A semiconductor device comprising the light-emitting diode according to any one of claims 1 to 10.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110680299.XA CN115498079A (en) | 2021-06-18 | 2021-06-18 | Light emitting diode and semiconductor device |
| PCT/CN2021/138505 WO2022262227A1 (en) | 2021-06-18 | 2021-12-15 | Light-emitting diode and semiconductor device |
| EP21945803.1A EP4358163A1 (en) | 2021-06-18 | 2021-12-15 | Light-emitting diode and semiconductor device |
| US18/207,240 US20230335679A1 (en) | 2021-06-18 | 2023-06-08 | Light-emitting diode and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110680299.XA CN115498079A (en) | 2021-06-18 | 2021-06-18 | Light emitting diode and semiconductor device |
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| CN115498079A true CN115498079A (en) | 2022-12-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110680299.XA Pending CN115498079A (en) | 2021-06-18 | 2021-06-18 | Light emitting diode and semiconductor device |
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| CN (1) | CN115498079A (en) |
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