CN115498043A - Semiconductor device and electronic device - Google Patents

Semiconductor device and electronic device Download PDF

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Publication number
CN115498043A
CN115498043A CN202210984757.3A CN202210984757A CN115498043A CN 115498043 A CN115498043 A CN 115498043A CN 202210984757 A CN202210984757 A CN 202210984757A CN 115498043 A CN115498043 A CN 115498043A
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China
Prior art keywords
layer
insulating substrate
semiconductor device
active layer
insulating
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CN202210984757.3A
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Chinese (zh)
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宋继越
艾飞
宋德伟
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN202210984757.3A priority Critical patent/CN115498043A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application provides a semiconductor device and electronic device, this semiconductor device includes the insulating substrate, and set up first insulating layer and active layer on the insulating substrate, first insulating layer is formed with a recess, the active layer sets up in the recess, the active layer is including range upon range of first semiconductor layer that sets up on the insulating substrate, active section and second semiconductor layer, wherein, the orthographic projection of first semiconductor layer on the insulating substrate and the orthographic projection part coincidence of second semiconductor layer on the insulating substrate, thereby form a semiconductor device that has vertical channel type thin film transistor, can improve the aperture opening ratio by a wide margin, the integrated level of semiconductor device has been promoted, be favorable to developing high PII, high refresh rate product and realize partial IC function.

Description

Semiconductor device and electronic device
Technical Field
The present disclosure relates to display technologies, and particularly to a semiconductor device and an electronic device.
Background
Currently, flat panel Display devices such as Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) mobile terminals have the advantages of high image quality, power saving, thin body, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, and the like, and become the mainstream of Display devices.
In the related art, it is known that integrating an IC (integrated circuit) circuit such as a pixel, a driver, a multiplexer, a controller, and a logic circuit on a glass Substrate (SOG) can improve the integration of a semiconductor device and reduce the dependency on an IC chip; in order to realize SOG, it is necessary to improve the integration level, the maximum operating frequency, and the current density of the conventional Thin Film Transistor (TFT), in which, since the electrical property of the thin film transistor when it is turned on is related to the portion of the active layer between the source electrode and the drain electrode, i.e., the channel length of the active layer, it is necessary to make the thin film transistor have a shorter channel length and a smaller volume; however, the conventional thin film transistor is generally planar, and includes an active layer, a gate electrode, a source electrode and a drain electrode which are stacked, and since the metal material can shield light and prevent light from passing through, the thin film transistor inevitably occupies a certain pixel area, which causes a decrease in an effective display area of a pixel, that is, an aperture ratio, and limits a light utilization rate, how to ensure that an area occupied by the thin film transistor in the entire display panel is reduced on the premise that the thin film transistor device normally operates is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
Embodiments of the present application provide a semiconductor device and an electronic device to alleviate the disadvantages of the related art.
In order to realize the above functions, the technical solutions provided in the embodiments of the present application are as follows:
an embodiment of the present application provides a semiconductor device, including
An insulating substrate:
a thin-film transistor layer on the insulating substrate, the thin-film transistor layer comprising:
the first insulating layer is arranged on the insulating substrate, and a groove is formed in the first insulating layer;
the active layer is arranged in the groove and comprises a first semiconductor layer, an active section and a second semiconductor layer which are arranged in a stacked mode, wherein the orthographic projection of the first semiconductor layer on the insulating substrate is overlapped with the orthographic projection of the second semiconductor layer on the insulating substrate.
In the semiconductor device provided by the embodiment of the present application, the first insulating layer includes steps disposed on both sides of the groove, and the active layer includes a first portion located in the groove and a second portion extending from the groove to an upper surface of the step.
In the semiconductor device provided by the embodiment of the application, the semiconductor device comprises a gate electrode positioned on one side of the active layer far away from the insulating substrate, the gate electrode is arranged in an insulating way with the active layer, and the active layer comprises a side surface positioned on the upper surface of the step;
wherein the grid is at least arranged on one side of the side surface, and the orthographic projection of the grid on the side surface covers the active section.
In the semiconductor device provided by the embodiment of the application, the gate electrode is arranged around the active layer.
In the semiconductor device provided by the embodiment of the application, an included angle between the side face and the upper surface of the step is greater than or equal to 30 degrees and less than or equal to 80 degrees.
In the semiconductor device provided by the embodiment of the application, the semiconductor device layer further comprises a source electrode and a drain electrode which are arranged in a stacked mode;
wherein one of the source electrode and the drain electrode is positioned on one side of the active layer close to the insulating substrate, the other one of the source electrode and the drain electrode is positioned on one side of the active layer far away from the insulating substrate, and the orthographic projection of the source electrode on the insulating substrate is at least overlapped with the orthographic projection of part of the drain electrode on the insulating substrate.
In the semiconductor device provided by the embodiment of the application, the source electrode is located on one side of the active layer close to the insulating substrate and connected with the first semiconductor layer, the drain electrode is located on one side of the active layer far away from the insulating substrate and connected with the second semiconductor layer, and an orthographic projection of the source electrode on the insulating substrate covers an orthographic projection of the active layer on the insulating substrate.
In the semiconductor device provided by the embodiment of the application, the semiconductor device further comprises a gate insulating layer positioned between the gate and the active layer, an interlayer insulating layer positioned on one side of the gate away from the insulating substrate, and a first via hole arranged above the active layer;
the first via hole penetrates through the interlayer insulating layer and the gate insulating layer, the drain electrode penetrates through the first via hole to be connected with the second semiconductor layer, and the first semiconductor layer penetrates through the groove to be connected with the source electrode.
In the semiconductor device provided by the embodiment of the present application, the semiconductor device further includes a second insulating layer located on one side of the drain electrode away from the insulating substrate, and an electrode layer located on one side of the second insulating layer away from the drain electrode, the second insulating layer is provided with a second via hole located above the active layer, and the electrode layer passes through the second via hole and is connected to the drain electrode;
the central line of the first via hole is coincident with the central line of the groove, the central line of the second via hole is coincident with the central line of the first via hole, and the aperture of the second via hole is smaller than that of the first via hole
An embodiment of the present application provides an electronic device including any one of the semiconductor devices described above.
The beneficial effects of the embodiment of the application are as follows: the embodiment of the application provides a semiconductor device and an electronic device, the semiconductor device comprises an insulating substrate, a first insulating layer and an active layer, wherein the first insulating layer and the active layer are arranged on the insulating substrate, a groove is formed in the first insulating layer, the active layer is arranged in the groove, the active layer comprises a first semiconductor layer, an active section and a second semiconductor layer which are arranged on the insulating substrate in a stacking mode, the orthographic projection of the first semiconductor layer on the insulating substrate is partially overlapped with the orthographic projection of the second semiconductor layer on the insulating substrate, and therefore the semiconductor device with the vertical channel type thin film transistor is formed, the aperture opening ratio can be greatly improved, the integration level of the semiconductor device is improved, development of products with high PII and high refresh rate is facilitated, and partial IC functions are achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a conventional display panel;
fig. 2 is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present application;
FIG. 3 is an enlarged view at A in FIG. 2;
fig. 4 is a cross-sectional top view of a semiconductor device provided by an embodiment of the present application;
fig. 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application;
fig. 6A to 6H are process flow diagrams of the structure of the semiconductor device in fig. 5.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a semiconductor device and an electronic device. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The embodiment of the application provides a semiconductor device and a mobile terminal. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 2 to 6H, an embodiment of the present invention provides a semiconductor device and an electronic device, where the semiconductor device 2 includes:
insulating substrate 10:
a first insulating layer 30 disposed on the insulating substrate 10, wherein a groove 301 is formed in the first insulating layer 30;
and the active layer 41 is arranged in the groove 301, and the active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C which are arranged in a stacked manner, wherein an orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 is overlapped with an orthographic projection of the second semiconductor layer 41C on the insulating substrate 10.
It can be understood that fig. 1 is a schematic structural diagram of a conventional display panel.
The conventional display panel 1 includes an insulating substrate 10, and a light shielding layer 20, a first insulating layer 30, a thin film transistor layer 40, a planarization layer 51, a common electrode 61, a passivation layer 52, and a pixel electrode 62 stacked on the insulating substrate 10, where the thin film transistor layer 40 includes an active layer 41, a gate insulating layer 42, a gate electrode 43, an interlayer insulating layer 44, a source electrode 45A, and a drain electrode 45B sequentially stacked on the insulating substrate 10; in the prior art, because the thin film transistor 40A is usually opaque and has a shielding effect on light, the thin film transistor 40A inevitably occupies a certain pixel area, which causes a decrease in an effective display area of a pixel, that is, a decrease in an aperture ratio, and limits a light utilization rate.
It can be understood that, in the embodiment of the present application, a groove 301 is formed by disposing the first insulating layer 30, the active layer 41 is disposed in the groove 301, and the active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C which are stacked on the insulating substrate 10, wherein an orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 is overlapped with an orthographic projection of the second semiconductor layer 41C on the insulating substrate 10, so as to form a semiconductor device having a vertical channel type thin film transistor, which can greatly improve an aperture ratio, improve an integration level of the semiconductor device 2, and is beneficial to developing a high-PII and a high-refresh-rate product and realizing a part of IC functions.
The technical solution of the present application will now be described with reference to specific embodiments.
In one embodiment, please refer to fig. 2 and 3; fig. 2 is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present application; fig. 3 is an enlarged view of a portion a in fig. 2.
The present embodiment provides a semiconductor device 2, where the semiconductor device 2 includes an insulating substrate 10, and a first insulating layer 30 and an active layer 41 located on the insulating substrate 10, the insulating substrate 10 may include a rigid substrate or a flexible substrate, and the present embodiment does not specifically limit the material of the insulating substrate 10.
The first insulating layer 30 forms a groove 301, the active layer 41 is disposed in the groove 301, and the active layer 41 includes a first semiconductor layer 41A, an active segment 41B, and a second semiconductor layer 41C, which are stacked, wherein an orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 is partially overlapped with an orthographic projection of the second semiconductor layer 41C on the insulating substrate 10.
Further, the material of the active layer 41 includes, but is not limited to, amorphous silicon, polysilicon, or an oxide semiconductor material, preferably, the first semiconductor layer 41A and the second semiconductor layer 42C are each made of polysilicon doped with n-type impurities at a high concentration by silicide, the doping ion concentration of the second semiconductor layer 42C is smaller than that of the first semiconductor layer 41A, one side of the active segment 41B is connected to the first semiconductor layer 41A, the other side of the active segment 41B is connected to the second semiconductor layer 41C, and the shape of the first semiconductor layer 41A, the shape of the active segment 41B, and the shape of the second semiconductor layer 41C are the same.
It can be understood that, in the present embodiment, a groove 301 is formed by disposing the first insulating layer 30, the active layer 41 is disposed in the groove 301, and the active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C which are stacked on the insulating substrate 10, wherein an orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 is overlapped with an orthographic projection of the second semiconductor layer 41C on the insulating substrate 10, so as to form a semiconductor device having a vertical channel type thin film transistor, which can greatly improve an aperture ratio, improve an integration level of the semiconductor device 2, and is beneficial to developing a high PII and a high refresh rate product and realizing a part of IC functions.
Further, in this embodiment, the first insulating layer 30 includes steps 302 disposed at two sides of the groove 301, and the active layer 41 includes a first portion 411 located in the groove 301 and a second portion 412 extending from the groove 301 to the upper surface 302A of the steps 302; specifically, the first portion 411 is located at the bottom and the side of the groove 301, the second portion 412 is located on the upper surface 302A of the step 302, and the second portion 412 covers the upper surface 302A of the step 302.
In this embodiment, the semiconductor device 2 includes a gate electrode 43 located on a side of the active layer 41 away from the insulating substrate 10, the gate electrode 43 is insulated from the active layer 41, and the active layer 41 includes a side face 413 located on the upper surface 302A of the step 302; wherein, the gate 43 is disposed at least on one side of the side face 413, and an orthographic projection of the gate 43 on the side face 413 covers the active segment 41B.
It is understood that, in the present embodiment, by disposing the gate electrode 43 at least on one side of the side face 413, the orthographic projection of the gate electrode 43 on the side face 413 covers the active segment 41B, so that the gate electrode 43 can adjust the current of the channel P of the active layer 41.
It should be noted that, in this embodiment, the side surface 413 is an inclined side surface, and an included angle α between the side surface 413 and the upper surface 302A of the step 302 is greater than or equal to 30 degrees and less than or equal to 80 degrees; the angle alpha is preferably 30 degrees, 45 degrees, 60 degrees or 80 degrees.
Further, please refer to fig. 4, which is a cross-sectional top view of the semiconductor device according to an embodiment of the present disclosure.
In this embodiment, the gate electrode 43 is disposed around the active layer 41, an orthographic projection of the gate electrode 43 on the insulating substrate 10 is annular, and the orthographic projection of the gate electrode 43 on the insulating substrate 10 overlaps four sides of the orthographic projection of the active segment 41B on the insulating substrate 10, that is, an annular channel P region is formed on the active segment 41B, so as to control the width of the channel P region, and further adjust the channel P current of the active layer 41.
In the present embodiment, the semiconductor device 2 further includes a source electrode 45A and a drain electrode 45B which are stacked; wherein one of the source electrode 45A and the drain electrode 45B is located on a side of the active layer 41 close to the insulating substrate 10, the other of the source electrode 45A and the drain electrode 45B is located on a side of the active layer 41 away from the insulating substrate 10, the gate electrode 43 is located on a side of the active layer 41 away from the insulating substrate 10, and an orthographic projection of the source electrode 45A on the insulating substrate 10 at least coincides with an orthographic projection of a part of the drain electrode 45B on the insulating substrate 10.
Preferably, in this embodiment, the source electrode 45A is located on a side of the active layer 41 close to the insulating substrate 10 and connected to the first semiconductor layer 41A, the drain electrode 45B is located on a side of the active layer 41 away from the insulating substrate 10 and connected to the second semiconductor layer 41C, and an orthographic projection of the source electrode 45A on the insulating substrate 10 covers an orthographic projection of the active layer 41 on the insulating substrate 10.
It is understood that, in the present embodiment, the semiconductor device 2 includes a plurality of thin film transistors 40A arranged in a matrix, the thin film transistors 40A include the source electrode 45A, the active layer 41, the gate electrode 43 and the drain electrode 45B which are stacked, the active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C which are stacked on the insulating substrate 10; in this embodiment, the source electrode 45A is located on one side of the active layer 41 close to the insulating substrate 10 and connected to the first semiconductor layer 41A, and the drain electrode 45B is located on one side of the active layer 41 away from the insulating substrate 10 and connected to the second semiconductor layer 41C, so as to form the semiconductor device 2 with the vertical channel type thin film transistor 40A, which can greatly improve the pixel aperture ratio, improve the integration level of the semiconductor device 2, and facilitate development of high PII and high refresh rate products; meanwhile, the semiconductor device 2 provided by the embodiment has the characteristics of small size and high integration level, so that the functions of data storage, voltage conversion and the like of the IC can be realized.
Furthermore, in the embodiment of the present application, the active layer 41 includes the first semiconductor layer 41A, the active segment 41B, and the second semiconductor layer 41C stacked on the insulating substrate 10, so that the length of the channel P can be controlled by controlling the thickness of the active segment 41B and the included angle α between the side surface 413 and the upper surface 302A of the step 302, that is, the length of the channel P can be controlled independently of the exposure apparatus
In addition, it can be understood that, with reference to fig. 1, in the prior art, a light shielding layer 20 is usually disposed between the insulating substrate 10 and the active layer 41, and the light shielding layer 20 can shield light that is emitted to the active layer 41, so as to reduce an increase in leakage current caused by photo-generated carriers generated by irradiating the active layer 41 with light, and further maintain stability of the active layer 41 during operation, compared with the prior art, in the present embodiment, an orthographic projection of the source electrode 45A on the insulating substrate 10 covers an orthographic projection of the active layer 41 on the insulating substrate 10, so that the source electrode 45A functions as the light shielding layer 20 in the prior art, thereby saving an engineering process and further reducing a manufacturing cost of the semiconductor device 2; and, by setting the orthographic projection of the drain electrode 45B on the insulating substrate 10 to be at least overlapped with the orthographic projection of a part of the source electrode 45A on the insulating substrate 10, the wiring space is saved.
In this embodiment, the semiconductor device 2 further includes a gate insulating layer 42 between the gate electrode 43 and the active layer 41, an interlayer insulating layer 44 on a side of the gate electrode 43 away from the insulating substrate 10, and a first via 400A disposed above the active layer 41; the first via hole 400A passes through the interlayer insulating layer 44 and the gate insulating layer 43, the drain electrode 45B passes through the first via hole 400A and is connected to the second semiconductor layer 41C, and the first semiconductor layer 41A passes through the groove 301 and is connected to the source electrode 45A
Specifically, the material of the first insulating layer 30 includes, but is not limited to, a single layer of silicon nitride (Si) 3 N 4 ) Single layer silicon dioxide (SiO) 2 ) Single layer silicon oxynitride (SiON) x ) Or a double-layer structure of the above layers, the groove 301 is formed in the first insulating layer 30 to extend to the source electrode 45A; it is understood that the first insulating layer 30 is disposed around the source electrode 45A, thereby acting as a barrier to water and oxygen for the source electrode 45A.
The gate insulating layer 42 and the interlayer insulating layer 44 have strong water-oxygen barrier capability and insulating capability, and the material of the gate insulating layer 42 and the material of the interlayer insulating layer 44 include, but are not limited to, silicon oxide (SiO) X ) Silicon nitride (SiN) X ) Silicon oxynitride (SiNO), or the like, or a stack thereof, the first via hole 400A being formed in the gate insulating layer 42 and the interlayer insulating layer 44 to extend onto the active layer 41; it will be appreciated that the gate insulating layer 42 surrounds the gateThe active layer 41 is disposed to block water and oxygen and insulate the active layer 41, and the interlayer insulating layer 44 is disposed around the gate electrode 43 to block water and oxygen and insulate the gate electrode 43.
In this embodiment, the semiconductor device 2 further includes a second insulating layer 50 located on a side of the drain electrode 45B away from the insulating substrate 10, and an electrode layer 70 located on a side of the second insulating layer 50 away from the drain electrode 45B, wherein the second insulating layer 50 defines a second via 40B located above the active layer 41, and the electrode layer 70 passes through the second via 40B and is connected to the drain electrode 45B; the central line W1 of the first via hole 400A coincides with the central line W2 of the groove 301, the central line W3 of the second via hole 40B coincides with the central line W1 of the first via hole 400A, the aperture of the second via hole 40B is smaller than that of the first via hole 400A, and in the first via hole 400A, the second insulating layer 50 covers the inner wall of the drain electrode 45B, so that the drain electrode 45B is blocked from water and oxygen and is insulated.
Specifically, in this embodiment, the second insulating layer 50 includes a flat layer 51 located on the drain electrode 45B, and a passivation layer 52 located on the flat layer 51 and away from the drain electrode 45B, the electrode layer 60 includes a first electrode 61 and a second electrode 62, the first electrode 61 is located between the flat layer 51 and the passivation layer 52, and the second electrode 62 is located on a side of the passivation layer 52 away from the flat layer 51, where the material of the electrode layer 60 includes a metal Oxide material, the metal Oxide material includes but is not limited to Indium Gallium Zinc Oxide (IGZO), the first electrode 61 is a common electrode 61, and the second electrode 62 is a pixel electrode 62.
Specifically, the planarization layer 51 defines a first sub-hole 51A exposing a portion of the drain electrode 45B, the passivation layer 52 defines a second sub-hole 52A exposing a portion of the drain electrode 45B, and the pixel electrode 62 is connected to the drain electrode 45B through the first sub-hole 51A and the second sub-hole 52A, wherein the second sub-hole 52A has a smaller aperture than the first sub-hole 51A in a direction perpendicular to the insulating substrate 10, and the passivation layer 52 covers an inner wall of the planarization layer 51 in the first sub-hole 51A, thereby blocking water and oxygen and insulating the planarization layer 51.
A center line W5 of the second sub-hole 52A, a center line W4 of the first sub-hole 51A, and a center line W1 of the first via hole 400A coincide with each other, a hole diameter of the first sub-hole 51A is smaller than a hole diameter of the first via hole 400A, and the planarization layer 51 covers an inner wall of the drain electrode 45B in the first via hole 400A, thereby blocking water and oxygen and insulating the drain electrode 45B.
It should be noted that the first electrode 61 is a common electrode 61, and the second electrode 62 is a pixel electrode 62 for illustration only. In another embodiment, the semiconductor device 2 further includes a flat layer, a bridge layer, a passivation layer, a light emitting device layer and an encapsulation layer on the side of the drain electrode 45B away from the insulating substrate 10, the light emitting device layer includes an electrode layer, a light emitting layer and a cathode layer stacked on the passivation layer, wherein the electrode layer 60 includes an anode.
The present embodiment further provides a method for manufacturing a semiconductor device, please refer to fig. 5 and fig. 6A to 6H; fig. 5 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; fig. 6A to 6H are process flow diagrams of structures of the semiconductor device of fig. 5.
In this embodiment, the manufacturing method includes the following steps:
step S100: an insulating substrate 10 is provided.
Wherein, when the insulating base 10 is a rigid substrate, the material may be metal or glass, and when the insulating base 10 is a flexible substrate, the material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin.
Step S200: a first insulating layer 30 and an active layer 41 are sequentially formed on the insulating substrate 10, the first insulating layer 30 forms a groove 301, the active layer 41 is disposed in the groove 301, the active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C, which are stacked, wherein an orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 is overlapped with an orthographic projection of the second semiconductor layer 41C on the insulating substrate 10.
Specifically, in this embodiment, before the step S200, the method for manufacturing a semiconductor device further includes the steps of:
step S110: a source electrode 45A is formed on the insulating substrate 10 as shown in fig. 6A.
In this embodiment, the material of the source electrode 45A is preferably a metal material, and the metal material includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); specifically, in the present embodiment, a metal material layer is deposited on the insulating substrate 10, and the metal material layer is patterned by Wet etching (Wet) using a yellow light process, so as to form a source electrode 45A pattern with trace and light shielding functions.
In step S200, the method for manufacturing a semiconductor device further includes the steps of:
step S201 is to form a first insulating layer 30 on the source electrode 45A, and to open a groove 301 exposing a portion of the source electrode 45A on the first insulating layer 30 through a photo-masking process, as shown in fig. 6B.
Wherein the material of the first insulating layer 30 includes, but is not limited to, a single layer of silicon nitride (Si) 3 N 4 ) Single layer silicon dioxide (SiO) 2 ) Single layer of silicon oxynitride (SiON) x ) Or a double-layer structure of the above layers, the first insulating layer 30 is formed by a method including, but not limited to, plasma Enhanced Chemical Vapor Deposition (PECVD), preferably yellow light and dry etching, and patterning the first insulating layer 30 to form the groove 301.
Step S202: an active layer 41 is formed on a side of the first insulating layer 30 away from the insulating substrate 10, and the active layer 41 is connected to the source electrode 45A through the groove 301.
Specifically, the step S202 includes: forming a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C in sequence on the side of the active layer 41 away from the first insulating layer 30, as shown in fig. 6C; wherein the first semiconductor layer 41A and the second semiconductor layer 42C are each made of polysilicon doped with an n-type impurity at a high concentration, the second semiconductor layer 42C has a doping ion concentration smaller than that of the first semiconductor layer 41A, one side of the active segment 41B is connected to the first semiconductor layer 41A, the other side of the active segment 41B is connected to the second semiconductor layer 41C, and the shape of the first semiconductor layer 41A, the shape of the active segment 41B, and the shape of the second semiconductor layer 41C are the same.
The first insulating layer 30 includes steps 302 disposed on two sides of the recess 301, and the active layer 41 includes a first portion 411 located in the recess 301 and a second portion 412 extending from the recess 301 to an upper surface 302A of the steps 302; specifically, the first portion 411 is located at the bottom and the side of the groove 301, the second portion 412 is located on the upper surface 302A of the step 302, and the second portion 412 covers the upper surface 302A of the step 302.
It should be noted that, in this embodiment, the side surface 413 is an inclined side surface, and an included angle α between the side surface 413 and the upper surface 302A of the step 302 is greater than or equal to 30 degrees and less than or equal to 80 degrees; the angle α is preferably 30 degrees, 45 degrees, 60 degrees or 80 degrees.
It can be understood that, in the present embodiment, a groove 301 is formed by disposing the first insulating layer 30, the active layer 41 is disposed in the groove 301, and the active layer 41 includes a first semiconductor layer 41A, an active segment 41B and a second semiconductor layer 41C which are stacked on the insulating substrate 10, wherein an orthographic projection of the first semiconductor layer 41A on the insulating substrate 10 is overlapped with an orthographic projection of the second semiconductor layer 41C on the insulating substrate 10, so as to form a semiconductor device having a vertical channel type thin film transistor, which can greatly improve an aperture ratio, improve an integration level of the semiconductor device 2, and is beneficial to developing a high PII and a high refresh rate product and realizing a part of IC functions.
In this embodiment, the method for manufacturing a semiconductor device further includes:
step S300: sequentially forming a gate insulating layer 42 and a gate electrode 43 on the side of the active layer 41 away from the first insulating layer 30, wherein an orthographic projection of the gate insulating layer 42 on the insulating substrate 10 covers an orthographic projection of the active layer 41 on the insulating substrate 10, and the active layer 41 comprises a side face 413 on the upper surface 302A of the step 302; wherein the gate 43 is disposed at least on one side of the side face 413, and an orthographic projection of the gate 43 on the side face 413 covers the active segment 41B, as shown in fig. 6D.
Wherein the material of the gate insulating layer 42 includes, but is not limited to, silicon oxide (SiO) X ) Silicon nitride (SiN) X ) Silicon oxynitride (SiNO), etc. or a stack thereof, and a material of the gate electrode 43 includes, but is not limited to, at least one metal of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W), which are not particularly limited in this embodiment.
Specifically, the gate electrode 43 is disposed around the active layer 41, an orthographic projection of the gate electrode 43 on the insulating substrate 10 is annular, and the orthographic projection of the gate electrode 43 on the insulating substrate 10 overlaps with four sides of an orthographic projection of the active segment 41B on the insulating substrate 10, that is, an annular channel P region is formed on the active segment 41B, so that the width of the channel P region is controlled, and the channel P current of the active layer 41 is further adjusted.
Step 400: an interlayer insulating layer 44 is formed on a side of the gate electrode 43 away from the gate insulating layer 42, and a first via 400A exposing a portion of the active layer 41 is opened on the interlayer insulating layer 44 and the gate insulating layer 42 by a photo-masking process, as shown in fig. 6E.
Wherein the material of the interlayer insulating layer 44 includes, but is not limited to, silicon oxide (SiO) X ) Silicon nitride (SiN) X ) Silicon oxynitride (SiNO), or the like, or a stack thereof, which is not particularly limited in this embodiment; preferably, yellow light and dry etching are performed to pattern the interlayer insulating layer 44 and the gate insulating layer 42, thereby forming the first via hole 400A, and a center line W1 of the first via hole 400A coincides with a center line W2 of the groove 301.
Step S500: a drain electrode 45B is formed on a side of the interlayer insulating layer 44 away from the gate electrode 43, and the drain electrode 45B is connected to the active layer 41 through the first via 400A, as shown in fig. 6F.
The material of the drain electrode 45B includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); specifically, in the present embodiment, a metal material layer is deposited on a side of the interlayer insulating layer 44 away from the gate electrode 43, and a yellow light process is used to pattern the metal material layer by Wet etching (Wet), so as to form a drain electrode 45B pattern with routing and light shielding functions, wherein the source electrode 45A is connected to the second semiconductor layer 41C through the first via hole 400A.
Step S600: a planarization layer 51 and a first electrode 61 are formed in this order on the side of the drain electrode 45B remote from the interlayer insulating layer 44.
Step S600 further includes forming a first sub-hole 51A exposing a portion of the drain electrode 45B on the planarization layer 51 through a photo-masking process, where a center line W4 of the first sub-hole 51A and a center line W1 of the first via hole 400A coincide with each other, an aperture of the first sub-hole 51A is smaller than an aperture of the first via hole 400A, and in the first via hole 400A, the planarization layer 51 covers an inner wall of the drain electrode 45B, thereby blocking water and oxygen and insulating the drain electrode 45B, as shown in fig. 6G.
Step S700: a passivation layer 52 and a second electrode 62 are sequentially formed on the side of the planarization layer 51 away from the drain electrode 45B.
The step S700 further includes forming a second sub-hole 52A exposing a portion of the drain electrode 45B on the passivation layer 70 through a photo-masking process, where the second electrode 62 is connected to the drain electrode 45B through the second sub-hole 52A and the first sub-hole 51A, a center line W5 of the second sub-hole 52A, a center line W4 of the first sub-hole 51A, and a center line W1 of the first via hole 400A coincide with each other, an aperture of the second sub-hole 52A is smaller than an aperture of the first sub-hole 51A, and in the first sub-hole 51A, the passivation layer 52 covers an inner wall of the planarization layer 51, so as to block water, oxygen, and insulate the planarization layer 51, as shown in fig. 6H.
Further, the material of the first electrode 61 and the material of the second electrode 62 both include a metal Oxide material, the metal Oxide material includes, but is not limited to, indium Gallium Zinc Oxide (IGZO), the first electrode 61 is a common electrode 61, and the second electrode 62 is a pixel electrode 62.
It can be understood that, in the present embodiment, by disposing the source electrode 45A on the side of the active layer 41 close to the insulating substrate 10, the drain electrode 45B on the side of the active layer 41 away from the insulating substrate 10, the gate electrode 43 between the drain electrode 45B and the active layer 41, and the orthographic projection of the gate electrode 43 on the insulating substrate 10 at least overlaps with the orthographic projection of a part of the active layer 41 on the insulating substrate 10, so as to form the semiconductor device 2 with the vertical channel type thin film transistor 40A, the pixel aperture ratio can be greatly improved, the integration level of the semiconductor device 2 is improved, and the development of high-pii, high-refresh-rate products is facilitated; meanwhile, since the semiconductor device 2 provided by the embodiment has the characteristics of small size and high integration level, the functions of data storage, voltage conversion and the like of the IC can be realized,
meanwhile, compared with the prior art, in the embodiment, the source electrode 45A is arranged on one side of the active layer 41 close to the insulating substrate 10, and the orthographic projection of the source electrode 45A on the insulating substrate 10 covers the orthographic projection of the active layer 41 on the insulating substrate 10, so that the source electrode 45A plays a role of the light shielding layer 20 in the prior art, and the embodiment not only saves a light shield, but also reduces an etching process, thereby achieving the purposes of simplifying the process flow and saving the production cost.
This embodiment provides an electronic device including a terminal body and the semiconductor device described in any of the above embodiments.
It is to be understood that the semiconductor device has been described in detail in the above embodiments, and the description is not repeated here.
In specific application, the electronic device can be a display screen of a smart phone, a tablet computer, a notebook computer, an intelligent bracelet, an intelligent watch, intelligent glasses, an intelligent helmet, a desktop computer, an intelligent television or a digital camera, and even can be applied to an electronic device with a flexible display screen.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing detailed description is directed to a semiconductor device and an electronic device provided in the embodiments of the present application, and specific examples are applied herein to explain the principles and implementations of the present application, and the description of the foregoing embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A semiconductor device, comprising:
an insulating substrate:
a thin-film transistor layer on the insulating substrate, the thin-film transistor layer including:
the first insulating layer is arranged on the insulating substrate and is provided with a groove;
the active layer is arranged in the groove and comprises a first semiconductor layer, an active section and a second semiconductor layer which are arranged in a stacked mode, wherein the orthographic projection of the first semiconductor layer on the insulating substrate is overlapped with the orthographic projection of the second semiconductor layer on the insulating substrate.
2. The semiconductor device according to claim 1, wherein the first insulating layer comprises steps provided on both sides of the groove, and wherein the active layer comprises a first portion located in the groove and a second portion extending from the groove to an upper surface of the steps.
3. The semiconductor device according to claim 2, wherein the semiconductor device comprises a gate electrode on a side of the active layer away from the insulating substrate, the gate electrode being provided insulated from the active layer, the active layer comprising a side surface on an upper surface of the step;
wherein the grid is at least arranged on one side of the side surface, and the orthographic projection of the grid on the side surface covers the active section.
4. The semiconductor device according to claim 3, wherein the gate electrode is provided around the active layer.
5. The semiconductor device according to claim 3, wherein an angle between the side face and the step upper surface is greater than or equal to 30 degrees and less than or equal to 80 degrees.
6. The semiconductor device according to claim 3, wherein the semiconductor device layer further comprises a source electrode and a drain electrode which are arranged in a stack;
wherein one of the source electrode and the drain electrode is positioned on one side of the active layer close to the insulating substrate, the other one of the source electrode and the drain electrode is positioned on one side of the active layer far away from the insulating substrate, and the orthographic projection of the source electrode on the insulating substrate is at least overlapped with the orthographic projection of part of the drain electrode on the insulating substrate.
7. The semiconductor device according to claim 6, wherein the source electrode is located on a side of the active layer close to the insulating substrate and connected to the first semiconductor layer, the drain electrode is located on a side of the active layer away from the insulating substrate and connected to the second semiconductor layer, and an orthographic projection of the source electrode on the insulating substrate covers an orthographic projection of the active layer on the insulating substrate.
8. The semiconductor device according to claim 7, further comprising a gate insulating layer between the gate electrode and the active layer, an interlayer insulating layer on a side of the gate electrode away from the insulating substrate, and a first via provided above the active layer;
the first via hole penetrates through the interlayer insulating layer and the gate insulating layer, the drain electrode penetrates through the first via hole to be connected with the second semiconductor layer, and the first semiconductor layer penetrates through the groove to be connected with the source electrode.
9. The semiconductor device according to claim 8, further comprising a second insulating layer on a side of the drain away from the insulating substrate, and an electrode layer on a side of the second insulating layer away from the drain, wherein the second insulating layer defines a second via hole over the active layer, and the electrode layer passes through the second via hole and is connected to the drain;
the central line of the first via hole is coincided with the central line of the groove, the central line of the second via hole is coincided with the central line of the first via hole, and the aperture of the second via hole is smaller than that of the first via hole.
10. An electronic device characterized in that it comprises a semiconductor device according to any one of claims 1-9.
CN202210984757.3A 2022-08-17 2022-08-17 Semiconductor device and electronic device Pending CN115498043A (en)

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CN202210984757.3A CN115498043A (en) 2022-08-17 2022-08-17 Semiconductor device and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210984757.3A CN115498043A (en) 2022-08-17 2022-08-17 Semiconductor device and electronic device

Publications (1)

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