CN115498010A - 半导体结构以及其形成方法 - Google Patents

半导体结构以及其形成方法 Download PDF

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CN115498010A
CN115498010A CN202111091309.2A CN202111091309A CN115498010A CN 115498010 A CN115498010 A CN 115498010A CN 202111091309 A CN202111091309 A CN 202111091309A CN 115498010 A CN115498010 A CN 115498010A
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region
well region
well
deep drain
doped region
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藤卷浩和
蔡博安
李世平
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Powerchip Technology Corp
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Powerchip Technology Corp
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Abstract

本发明公开一种半导体结构以及其形成方法，其中该半导体结构包含一基底，该基底具有一第一导电型态，一LDMOS元件位于该基底上，其中该LDMOS元件包含一第一阱区，位于该基底上，该第一阱区有一第一导电型态，一第二阱区，位于该第一阱区之内，且其中一部分的该第二阱区的上下两面被该第一阱区所包围，其中该第二阱区具有一第二导电型态，其中该第二导电型态与该第一导电型态互补，一源极掺杂区，位于该第二阱区之内，该源极掺杂区具有该第一导电型态，以及一深漏极掺杂区，位于第一阱区之内，深漏极掺杂区具有第一导电型态。

Description

半导体结构以及其形成方法
技术领域
本发明涉及半导体结构，尤其是涉及一种横向扩散金属氧化物半导体(lateraldiffused metal oxide semiconductor，LDMOS)晶体管元件及其制作方法。
背景技术
横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件是一种常见的功率半导体元件。由于横向扩散金属氧化物半导体元件具有水准式的结构，容易制造且易于和现行的半导体技术整合，进而减少制作成本。同时，其可以耐较高的击穿电压而具有高的输出功率，因此被广泛应用于功率转换器(power converter)、功率放大器(power amplifier)、切换开关(switch)、整流器(rectifier)等元件。
然而由于LDMOS等元件通常面积较大，因此也占用整个半导体结构将近约一半的面积。因此如何改进元件结构，使得LDMOS的面积缩减，将是业界的研究方向之一。
发明内容
本发明提供一种半导体结构，包含一基底，该基底具有一第一导电型态，一横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件位于该基底上，其中该LDMOS元件包含一第一阱区，位于该基底上，该第一阱区有一第一导电型态，一第二阱区，位于该第一阱区之内，且其中一部分的该第二阱区的上下两面被该第一阱区所包围，其中该第二阱区具有一第二导电型态，其中该第二导电型态与该第一导电型态互补，一源极掺杂区，位于该第二阱区之内，该源极掺杂区具有该第一导电型态，以及一深漏极掺杂区，位于第一阱区之内，深漏极掺杂区具有第一导电型态。
本发明另提供一种半导体结构的形成方法，包含提供一基底，该基底具有一第一导电型态，形成一横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件于该基底上，其中该LDMOS元件包含形成一第一阱区于该基底上，该第一阱区有一第一导电型态，形成一第二阱区于该第一阱区之内，且其中一部分的该第二阱区的上下两面被该第一阱区所包围，其中该第二阱区具有一第二导电型态，其中该第二导电型态与该第一导电型态互补，形成一源极掺杂区，位于该第二阱区之内，该源极掺杂区具有该第一导电型态，以及在该第一阱区中形成一凹槽，并且在凹槽中形成一深漏极掺杂区于第一阱区之内，深漏极掺杂区具有第一导电型态。
本发明的特征在于，提供一种降低表面场的横向扩散金属氧化物半导体场效应晶体管(Reduced Surface Field Laterally Diffused MOSFET，简称为RESURF LDMOS)。该RESURF LDMOS的形成过程中，在一第一阱区中形成一凹槽，接着在该凹槽中填入高掺杂浓度的多晶硅材质，或是以掺杂方式形成U型剖面的离子掺杂区，以在第一阱区中形成一深漏极掺杂区。有别于现有方式在第一阱区中以离子注入与加热扩散的方式形成深漏极掺杂区，本案的深漏极掺杂区所需面积大幅减少，因此也可减少元件的总面积，达到微型化的效果。此外深漏极掺杂区具有高掺杂浓度，较不容易产生电压降，也因此可以提高产品的品质。
附图说明
图1至图7为本发明形成一降低表面场的横向扩散金属氧化物半导体场效应晶体管(Reduced Surface Field Laterally Diffused MOSFET，简称为RESURF LDMOS)的流程示意图；
图8为一以离子注入与加热步骤形成深漏极掺杂区的RESURF LDMOS的结构示意图；
图9为一P型RESURF LDMOS的结构示意图；
图10～图11分别为本发明另两个实施例的RESURF LDMOS的结构示意图；
图12～图14为本发明另一个实施例的RESURF LDMOS的结构示意图。
符号说明
1:降低表面场的横向扩散金属氧化物半导体场效应晶体管(RESURF LDMOS)结构
10:基底
12:第一阱区
14:阻障层
16:漂移区
20:第二阱区
22:绝缘层
24:凹槽
25:光致抗蚀剂层
26:多晶硅层
27:深漏极掺杂区
27A:深漏极掺杂区
28:栅极结构
29:栅极介电层
30:栅极导电层
32:源极掺杂区
34:浅漏极掺杂区
34A:离子掺杂区
36:基体区
40:金属硅化物层
42:介电层
44:接触结构
44A:接触结构
45:衬垫层
46:导电层
50:绝缘层
60:绝缘层
A:区域
B:区域
C:区域
G:间距
P1:掺杂步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围，在此容先叙明。
请参考图1至图7，图1至图7绘示本发明形成一降低表面场的横向扩散金属氧化物半导体场效应晶体管(Reduced Surface Field Laterally Diffused MOSFET，简称为RESURF LDMOS)的流程示意图。如图1所示，提供一基底10，在基底10内以例如掺杂等方式形成一第一阱区12以及一第二阱区20。值得注意的是，基底10例如为硅基底(单晶硅)，第一阱区12位于基底10上，包含有一第一导电型态(例如N型，第一阱区12可以包含有一阻障层14以及一漂移区16，两者相互连接且具有同样导电型态(例如N型)。第二阱区20则包含有与第一导电型态互补的第二导电型态(例如P型)。本实施例中，基底10例如为P型基底。
值得注意的是，如图1所示，有一部分的第二阱区20横向深入第一阱区12之内，且部分第二阱区20的上下两面被第一阱区12所包围，形成第一阱区12与第二阱区20相互交错的结构。换句话说，一部分第二阱区20的延伸部，位于第一阱区12的阻障层14以及漂移区16之间。在实际制作过程中，可以先在基底10上形成阻障层14，然后形成第二阱区20之后，再于一部分的第二阱区20中掺杂离子而形成漂移区16。
后续步骤中，将这种阱区的分布结构制成LDMOS元件时，有利于在N-P介面处形成空乏区阻挡电流通过，让LDMOS在关闭状态时可承受较大的电压差，此种结构比起一般的LDMOS所需要的面积更小，因此上述LDMOS也可简称为降低表面场的横向扩散金属氧化物半导体场效应晶体管(Reduced Surface Field Laterally Diffused MOSFET，简称为RESURFLDMOS)。关于RESURF LDMOS的其他介绍，已经揭露于部分现有技术中(例如美国专利证书号US 9484454)，因此在此不多加赘述。
本发明在RESURF LDMOS的架构下进行改进，以达到减少元件面积以及增加元件品质的效果。如图1所示，形成一图案化的绝缘层22位于第一阱区12以及第二阱区20的表面，绝缘层22例如为氧化硅或是氮化硅，但不限于此。然后以绝缘层22为掩模，在第一阱区12中形成一凹槽24，凹槽24例如可以用图案化与蚀刻等方式形成，但不限于此。另外本实施例中，凹槽24的宽度较佳小于0.5微米，深度大于8微米，但不限于此。本实施例中，凹槽24的宽度约为0.3微米，而深度较佳大于阻障层14与第二阱区20的交界面。
接着如图3所示，形成一多晶硅层26填满凹槽24，其中多晶硅层26例如为具有高掺杂浓度的多晶硅层，可以通过原位(in-situ)掺杂制作工艺形成，其具有第一导电型态(例如N型)。本实施例中，多晶硅层26的浓度较佳大于1E18cm3上述浓度较现有步骤中，以离子注入与加热步骤等方式所形成的掺杂区浓度更高。
接着如图4所示，以回蚀刻或是化学机械研磨等方式，移除多余的多晶硅层26与绝缘层22，以曝露出第一阱区12与第二阱区20的表面。此处剩余在凹槽24内的多晶硅层26，又可以被定义为深漏极掺杂区27，其作用将会在下面段落继续描述。
如图5所示，形成一栅极结构28于第一阱区12以及第二阱区20上，其中栅极结构28包含有栅极介电层29以及栅极导电层30，其中栅极介电层29在漂移区16上方的厚度较厚，而在第一阱区12以及第二阱区20在表面的交界处附近则具有较薄的厚度。上述栅极结构28属于RESURF LDMOS的现有技术，其余特征不多加赘述。
继续参考图6，在栅极结构28完成后，以离子掺杂与加热步骤等方式分别在第一阱区12以及第二阱区14内至少形成源极(source)掺杂区32以及浅漏极(drain)掺杂区34。其中源极掺杂区32与浅漏极掺杂区34都包含有第一导电型态(例如N型)，且浅漏极掺杂区34与上述深漏极掺杂区27连接。值得注意的是，由于源极掺杂区32与浅漏极掺杂区34都是以离子掺杂以及加热的步骤形成于单晶硅成分的阱区之中，因此其材质也是单晶硅，且材质不同于深漏极掺杂区27。另外，本实施例中，源极掺杂区32以及浅漏极掺杂区34的离子掺杂浓度例如为大于1E20cm3。除此之外，在一些实施例中，可以在源极掺杂区32旁另外形成有基体区(body)36，其中基体区36例如为包含有第二导电型态(例如P型)的掺杂区。
如图7所示，可以选择性地在栅极结构28、第一阱区12与第二阱区20的表面形成金属硅化物层40。接着形成一介电层42覆盖于上述元件后，在介电层42中形成接触结构44，接触结构连接到源极掺杂区32与浅漏极掺杂区34。其中在一些实施例中，金属硅化物层40可以省略不形成，或是在介电层42完成后，将金属硅化物层40形成于接触结构44底下。介电层42例如为氧化硅或氮化硅，而接触结构44可能包含有衬垫层45，其材质例如为钛/氮化钛，以及导电层46，其材质例如为钨(W)。上述元件的其他细节与制作方法，属于本领域的现有技术，在此不多赘述。至此已完成本发明所述的RESURF LDMOS结构1。由于本实施例中RESURF LDMOS结构1的第一阱区12为N型，因此本实施例的RESURF LDMOS结构1又可定义为N型RESURF LDMOS结构。
本发明的RESURF LDMOS结构1，在栅极结构28关闭时，源极端与漏极端仍具有电位差，例如在漏极端上方的接触结构44导入高电压(例如100V)，而源极端维持0电位，此时由于深漏极掺杂区27的掺杂浓度高且导电性佳，因此传导至下方的电压仅有少量降低。电压会使得第一阱区12维持高电位，而第二阱区20保持低电位，使得位于RESURF LDMOS结构1中央部分的N-P交界面产生空乏区。例如图7中的区域A、B、C，都是可能产生空乏区的区域。也就是说，当RESURF LDMOS结构1的栅极结构28关闭时，除了通道区关闭可以造成隔绝之外，中央产生的空乏区也能进一步隔绝电流，让RESURF LDMOS结构1可以承受高电压的运作模式。
为了让上述空乏区可以顺利形成，现有技术中较佳将深漏极掺杂区的深度制作得更深，以让电压可以顺利传导至下方靠近阻障层14的部分，并且顺利产生空乏区。图8绘示一以离子注入与加热步骤形成深漏极掺杂区的RESURF LDMOS的结构示意图。现有技术中，以离子注入与加热步骤来增加深漏极掺杂区的深度，然而，离子在加热的同时也会朝向横向扩散，因此现有技术中深漏极掺杂区的宽度较大(如图8中的离子掺杂区34A)，如此一来将会导致元件的面积过大，不利于元件的微小化。举例来说，现有技术中离子掺杂区34A的深度若要达到8微米，则其宽度约会扩散到12微米左右。此外，离子掺杂区34A的掺杂浓度不如本发明的深漏极掺杂区27，故导电性也不如深漏极掺杂区27。当从离子掺杂区34A上方导入高电压(例如100V)时，传导至离子掺杂区34A下方的电压将会下降得更多，如此不利于空乏区的形成。
本发明的RESURF LDMOS结构1与现有技术中的RESURF LDMOS结构的主要不同处在于形成深漏极掺杂区27取代部分的离子掺杂区，上述深漏极掺杂区27以蚀刻凹槽24与回填多晶硅层26的方式所形成。其中，凹槽24的宽度可以远小于上述现有技术中离子掺杂区34A的宽度，另一个特征是在凹槽24中填入更高掺杂浓度且导电性更好的多晶硅层26，不但可以大幅度减少元件面积(因为深漏极掺杂区27的宽度较小)，且深漏极掺杂区27的导电效果更佳，使得来自上方接触结构44的高电压，可以顺利地传导至深漏极掺杂区27的下方，进一步再传导到第一阱区12内，让空乏区可以顺利形成。总之，本发明具有减少元件面积、提高元件品质以及与现有制作工艺相容等优点。
在上述实施例中(图1到图7)，以制作N型RESURF LDMOS结构为例，也就是第一阱区12以及深漏极掺杂区27为N型、第二阱区20为P型。但在本发明的其他实施例中，也可以制作P型RESURF LDMOS结构。如图9所示，图9绘示一P型RESURF LDMOS的结构示意图。其中，多数元件的结构、材质与制作方法与上述第一优选实施例相同而不多赘述，与上述实施例不同之处在于，本实施例中基底10、第一阱区12、深漏极掺杂区27、源极掺杂区32与浅漏极掺杂区34为P型，而第二阱区20与基体区36则是N型。值得注意的是，本实施例中深漏极掺杂区27并不接触第二阱区20，且深漏极掺杂区27以及第二阱区20之间维持有一间距G，以避免在漏极端导入高电位时，具有较高掺杂浓度的深漏极掺杂区27与具有较低掺杂浓度的第二阱区20之间产生电流击穿(punch through)而引起元件击穿(breakdown)。
同样地，在本发明的其他实施例中，为了避免横向的电流击穿，可以在深漏极掺杂区27旁边或是下方设置绝缘层。请参考图10～图11，图10～图11分别绘示根据本发明另两个实施例的RESURF LDMOS的结构示意图。如图10所示，本实施例中额外形成一绝缘层50在深漏极掺杂区27旁边，绝缘层50例如为氧化硅、或是外围被氧化硅所包围的多晶硅层。绝缘层50的深度可以比深漏极掺杂区27的深度更深，且绝缘层50设置在第一阱区12旁的基底10内，在一些实施例中，深沟槽隔离(deep trench isolation，DTI)可以当作此处的绝缘层50。绝缘层50具有防止深漏极掺杂区27击穿第一阱区12而影响其他相邻元件的功能。
在另一实施例中，如图11所示，除了设置上述的绝缘层50以外，本实施例中将部分的阻障层14以另一绝缘层60取代。绝缘层60例如为氧化硅。在一些实施例中，可以用硅覆绝缘层(silicon on substrate，SOI)基底来代替原本的硅基底，以达到如图11所示的结构。在本实施例中，绝缘层60同样可以防止纵向方向的电流击穿。
在本发明的其他实施例中，也可以在同一基底上形成不同的LDMOS。举例来说，可以将N型RESURF LDMOS(图7所示的结构)与P型RESURF LDMOS(图9所示的结构)一起形成在同一基底的不同区域上。此结构也属于本发明的涵盖范围内。
在以上的实施例中，在凹槽24中填入高掺杂浓度的多晶硅层26，用于形成宽度较窄的多晶硅深漏极掺杂区27。另外在本发明的其他实施例中，也可以通过在凹槽24内以掺杂或是等离子体注入等其他方式，在第一阱区12内形成宽度较窄且深度足够的深漏极掺杂区，详细如下图12至图14所示。
如图12所示，在本实施例中，形成凹槽24之后(接续第一实施例的图1与图1的步骤)，先形成一光致抗蚀剂层25覆盖部分的第一阱区12与第二阱区20，并且同时曝露出部分的第一阱区12与第二阱区20，其中被曝露的区域包含有凹槽24、以及第二阱区20中预定要形成源极掺杂区32的位置。接下来，进行一掺杂步骤P1，对未被光致抗蚀剂层25覆盖的区域进行掺杂，在本实施例中，以掺杂高浓度的N型离子为例，但本发明的其他实施例中，也可能掺杂高浓度的P型离子，本发明不以此为限制。此外，凹槽24、源极掺杂区32、栅极结构28也可以分别用不同光掩模进行个别独立的掺杂，本发明不以此为限制。
值得注意的是，本实施例中离子掺杂步骤P1过程中可以调整其掺杂角度，例如以斜向方向进行掺杂，因此所掺杂的离子，可以深入至凹槽24的底面以及侧壁，在凹槽24的底面与侧壁形成深漏极掺杂区27A。与前述实施例所提及的深漏极掺杂区27不同的是，本实施例中的深漏极掺杂区27A因为以离子掺杂的方式形成在第一阱区12的凹槽24外围，因此具有U型的剖面轮廓，且深漏极掺杂区27A的材质与第一阱区12相同，两者均为单晶硅。此外，本实施例中在形成深漏极掺杂区27A的同时，也同时可在第二阱区20内形成源极掺杂区32，因此可以达到节省步骤的功效。此外凹槽24亦可以使用等离子体掺杂(plasma doping)方式进行掺杂，本发明不以此为限制。
接着，如图13所示，移除光致抗蚀剂层25，之后在源极掺杂区32旁边形成基体区36，此处的基体区36例如是以掺杂的方式形成的一P型掺杂区。然后再形成金属硅化物层40，其中金属硅化物层40覆盖在栅极结构28、第一阱区12、第二阱区20与凹槽24(即深漏极掺杂区27A)的表面。此外本发明也可以不用形成金属硅化物层、或选择性的形成金属硅化物层于基底，或栅极结构，或凹槽内表面，本发明不以此为限制。
然后如图14所示，形成介电层42以及接触结构44以及接触结构44A。其中介电层42例如为氧化硅或氮化硅，而接触结构44与接触结构44A可能包含有衬垫层45，其材质例如为钛/氮化钛，以及导电层46，其材质例如为钨(W)。此处关于形成基体区36、金属硅化物层40与接触结构44、44A的步骤与上述实施例相似(可参考图6与图7的描述)相似，在此不多加赘述。值得注意的是，本实施例中的接触结构44A形成在凹槽24内，也就是形成在深漏极掺杂区27A上。接触结构44A深入第一阱区12内，也就是接触结构44A的底面低于第一阱区12的顶面，因此可以有效地将来自上方其他元件的电流传导至下方。
综合以上图12至图14，本实施例以另一种方式形成深漏极掺杂区27A，其在凹槽中通过掺杂或是离子注入等方式形成深漏极掺杂区。其中深漏极掺杂区的深度足够将来自上方的电流传导至下方。在另一实施例中，深漏极掺杂区的宽度也小于0.5微米，同样具有节省空间的功效。此外本实施例也与现有的制作工艺相容。此外，本实施例中以制作N型RESURF LDMOS结构为例，但可以调整掺杂离子的种类，而制作P型的RESURF LDMOS结构。也就是将本实施例中在凹槽内掺杂离子的方法，应用于图9的实施例中，也属于本发明的涵盖范围。
综合以上说明书与附图，本发明提供一种半导体结构，包含一基底10，一横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件位于该基底10上，其中该LDMOS元件包含:一第一阱区12，位于该基底10上，该第一阱区12有一第一导电型态，一第二阱区20，位于该第一阱区12之内，且其中一部分的该第二阱区20的上下两面被该第一阱区12所包围，其中该第二阱区20具有一第二导电型态，其中该第二导电型态与该第一导电型态互补，一源极掺杂区32，位于该第二阱区20之内，该源极掺杂区32具有该第一导电型态，以及一深漏极掺杂区(27或27A)，位于第一阱区12之内，深漏极掺杂区(27或27A)具有第一导电型态。在另一实施例中，其深漏极掺杂区(27或27A)的一宽度小于0.5微米。
本发明另提供一种半导体结构的形成方法，包含提供一基底10，形成一横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件位于基底上，其中形成LDMOS元件的步骤包含:形成一第一阱区12于基底10上，第一阱区12有一第一导电型态，形成一第二阱区20于第一阱区12之内，且其中一部分的第二阱区20的上下两面被第一阱区12所包围，其中第二阱区20具有一第二导电型态，其中第二导电型态与第一导电型态互补，形成一源极掺杂区32，位于第二阱区20之内，源极掺杂区32具有第一导电型态，以及在第一阱区12中形成一凹槽24，并且在凹槽24中形成一深漏极掺杂区(27或27A)于第一阱区12之内，深漏极掺杂区(27或27A)具有第一导电型态。在另一实施例中，其深漏极掺杂区(27或27A)的一宽度小于0.5微米。
在一些实施例中，其中第一阱区12与第二阱区20的材质均包含单晶硅，而深漏极掺杂区27的材质包含多晶硅，且深漏极掺杂区27的形状包含一柱状体。
在一些实施例中，其中第一阱区12、第二阱区20与深漏极掺杂区27A的材质均包含单晶硅，深漏极掺杂区27A具有一U型剖面轮廓。
在一些实施例中，其中还包含有一接触结构44A，位于第一阱区12上，并且与深漏极掺杂区27A电连接，其中接触结构44A的一底面低于该第一阱区12的一顶面。
在一些实施例中，其中深漏极掺杂区27的一掺杂浓度高于1E18cm3。
在一些实施例中，还包含有一浅漏极掺杂区34，位于第一阱区12之内，并且连接深漏极掺杂区27。
在一些实施例中，其中第一阱区12包含有一阻障层14以及一漂移区16相互连接，且部分第二阱区20位于阻障层14与漂移区16之间。
在一些实施例中，还包含有至少一绝缘结构50，位于深漏极掺杂区27旁边。
在一些实施例中，其中第一导电型态包含N型，第二导电型态包含P型。
在一些实施例中，其中第一导电型态包含P型，第二导电型态包含N型。
本发明的特征在于，提供一种降低表面场的横向扩散金属氧化物半导体场效应晶体管(Reduced Surface Field Laterally Diffused MOSFET，简称为RESURF LDMOS)。该RESURF LDMOS的形成过程中，在一第一阱区中形成一凹槽，接着在该凹槽中填入高掺杂浓度的多晶硅材质，或是以掺杂方式形成U型剖面的离子掺杂区，以在第一阱区中形成一深漏极掺杂区。有别于现有方式在第一阱区中以离子注入与加热扩散的方式形成深漏极掺杂区，本案的深漏极掺杂区所需面积大幅减少，因此也可减少元件的总面积，达到微型化的效果。此外深漏极掺杂区具有高掺杂浓度，较不容易产生压降，也因此可以提高产品的品质。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体结构，包含:
基底；
横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件位于该基底上，其中该横向扩散金属氧化物半导体元件包含:
第一阱区，位于该基底上，该第一阱区有第一导电型态；
第二阱区，位于该第一阱区之内，且其中一部分的该第二阱区的上下两面被该第一阱区所包围，其中该第二阱区具有第二导电型态，其中该第二导电型态与该第一导电型态互补；
源极掺杂区，位于该第二阱区之内，该源极掺杂区具有该第一导电型态；以及
深漏极掺杂区，位于该第一阱区之内，该深漏极掺杂区具有该第一导电型态。
2.如权利要求1所述的半导体结构，其中该第一阱区与该第二阱区的材质均包含单晶硅，而该深漏极掺杂区的材质包含多晶硅，且该深漏极掺杂区的形状包含柱状体。
3.如权利要求1所述的半导体结构，其中该第一阱区、该第二阱区与该深漏极掺杂区的材质均包含单晶硅，该深漏极掺杂区具有U型剖面轮廓。
4.如权利要求3所述的半导体结构，还包含有接触结构，位于该第一阱区上，并且与该深漏极掺杂区电连接，其中该接触结构的底面低于该第一阱区的顶面。
5.如权利要求1所述的半导体结构，其中该深漏极掺杂区的掺杂浓度高于1E18cm3。
6.如权利要求1所述的半导体结构，还包含有浅漏极掺杂区，位于该第一阱区之内，并且连接该深漏极掺杂区。
7.如权利要求1所述的半导体结构，其中该第一阱区包含有阻障层以及漂移区相互连接，且部分该第二阱区位于该阻障层与该漂移区之间。
8.如权利要求1所述的半导体结构，还包含有至少一绝缘结构，位于该深漏极掺杂区旁边。
9.如权利要求1所述的半导体结构，其中该第一导电型态包含N型，该第二导电型态包含P型，或是该第一导电型态包含P型，该第二导电型态包含N型。
10.如权利要求1所述的半导体结构，其中该深漏极掺杂区的宽度小于0.5微米。
11.一种半导体结构的形成方法，包含:
提供基底；
形成横向扩散金属氧化物半导体(laterally diffused metal-oxide-semiconductor，LDMOS)元件位于该基底上，其中形成该横向扩散金属氧化物半导体元件的步骤包含:
形成第一阱区于该基底上，该第一阱区有第一导电型态；
形成第二阱区于该第一阱区之内，且其中一部分的该第二阱区的上下两面被该第一阱区所包围，其中该第二阱区具有第二导电型态，其中该第二导电型态与该第一导电型态互补；
形成源极掺杂区，位于该第二阱区之内，该源极掺杂区具有该第一导电型态；
在该第一阱区中形成凹槽；以及
在该凹槽中形成深漏极掺杂区于该第一阱区之内，该深漏极掺杂区具有该第一导电型态。
12.如权利要求11所述的形成方法，其中该深漏极掺杂区由在该凹槽内填入掺杂的多晶硅层所形成，其中该第一阱区与该第二阱区的材质均包含单晶硅，而该深漏极掺杂区的材质包含多晶硅，并且该深漏极掺杂区的形状包含柱状体。
13.如权利要求11所述的形成方法，其中该深漏极掺杂区由在该凹槽内进行掺杂步骤所形成，其中该第一阱区、该第二阱区与该深漏极掺杂区的材质均包含单晶硅，该深漏极掺杂区具有U型剖面轮廓。
14.如权利要求13所述的形成方法，还包含形成接触结构，位于该第一阱区上，并且与该深漏极掺杂区电连接，其中该接触结构的底面低于该第一阱区的顶面。
15.如权利要求11所述的形成方法，其中该深漏极掺杂区的掺杂浓度高于1E18cm3。
16.如权利要求11所述的形成方法，还包含形成有浅漏极掺杂区，位于该第一阱区之内，并且连接该深漏极掺杂区。
17.如权利要求11所述的形成方法，其中该第一阱区包含有阻障层以及漂移区相互连接，且部分该第二阱区位于该阻障层与该漂移区之间。
18.如权利要求11所述的形成方法，还包含形成有至少一绝缘结构，位于该深漏极掺杂区旁边。
19.如权利要求11所述的形成方法，其中该第一导电型态包含N型，该第二导电型态包含P型，或是该第一导电型态包含P型，该第二导电型态包含N型。
20.如权利要求11所述的形成方法，其中该深漏极掺杂区的宽度小于0.5微米。
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