CN115497879A - Method for manufacturing semiconductor structure - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor structure, which comprises the steps of forming a material laminated layer on a substrate and covering an array area and a peripheral area of the material laminated layer; forming a first patterned mask layer over the material stack; transferring the pattern of the first patterned mask layer to the material stack to form a first array pattern and a first peripheral pattern in the array region and the peripheral region; providing a second patterned mask layer over the first array pattern and the first peripheral pattern, the second and first patterned mask layers being staggered in pattern; transferring the pattern of the second patterned mask layer downward to form first and second sacrificial patterns in the array region and the peripheral region; and simultaneously carrying out pattern transfer on the first array pattern, the first sacrificial pattern, the first peripheral pattern and the second sacrificial pattern so as to form a second array pattern and a second peripheral pattern in the array area and the peripheral area respectively. The manufacturing method of the semiconductor structure provided by the invention can simplify the process steps and reduce the cost.

Description

Method for manufacturing semiconductor structure

Technical Field

Embodiments of the present invention relate to a method for fabricating a semiconductor structure, and more particularly, to a method for fabricating a material layer in an array region and a peripheral region of a patterned semiconductor structure.

Background

In recent years, as the manufacturing technology of Dynamic Random Access Memory (DRAM) devices continues to advance toward the miniaturization of device sizes, many challenges have been raised. For example, conventionally, the patterning steps are performed separately for the material layers in the array region and the peripheral region of the semiconductor structure, and multiple precise steps are required for patterning in response to the reduced device size, which is time consuming and expensive. Accordingly, there is a need for improved methods of fabricating dram devices, and in particular, for overcoming the problems associated with the reduced device size and patterning process.

Disclosure of Invention

The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps: forming a first material lamination above a substrate, the substrate comprising an array region and a peripheral region, wherein the first material lamination covers the array region and the peripheral region, and the first material lamination comprises a first pattern transfer layer and a second pattern transfer layer; forming a first patterned mask layer on the first material stack layer in the array region and the peripheral region, the first patterned mask layer exposing a portion of a top surface of the first material stack layer; removing a portion of the first material stack using the first patterned mask layer as a mask to transfer the pattern of the first patterned mask layer to the second pattern transfer layer, thereby forming a first array pattern and a first periphery pattern in the array region and the periphery region, respectively; providing a second patterned mask layer over the first array pattern and the first peripheral pattern, corresponding to the array region and the peripheral region, wherein the pattern of the second patterned mask layer is offset (e.g., in a first direction) from the pattern of the first patterned mask layer; using the second patterned mask layer as a mask to transfer the pattern of the second patterned mask layer downward, thereby forming a first sacrificial pattern and a second sacrificial pattern in the array region and the peripheral region, respectively; and performing pattern transfer on the first array pattern and the first sacrificial pattern to form a second array pattern in the array region, and performing pattern transfer on the first peripheral pattern and the second sacrificial pattern to form a second peripheral pattern in the peripheral region.

In addition, in an embodiment, after forming the second array pattern and the second peripheral pattern, the method for fabricating the semiconductor structure further includes: forming a second material lamination layer on the second array pattern and the second peripheral pattern; forming a third patterned mask layer on the second material layer in the array region and the peripheral region; and performing a self-aligned double patterning process according to the pattern of the third patterned mask layer to form a patterned stack of materials, wherein the patterned stack of materials includes a third array pattern formed in the array region.

In addition, in an embodiment, after the forming the third array pattern, the method for manufacturing the semiconductor structure further includes: forming a fourth patterned mask layer to cover the peripheral region and expose the third array pattern of the array region; and removing the exposed part of the lower material layer and the corresponding part of the second array pattern by using the fourth patterned mask layer and the third array pattern as masks to convert the second array pattern into a final array pattern.

The embodiment of the invention defines the pattern of the peripheral area and defines the pattern of the array area along the first direction at the same time, compared with the traditional process of separately manufacturing the array pattern and the peripheral pattern, the manufacturing method of the semiconductor structure provided by the invention can simplify the process steps and reduce the cost. In addition, since the present invention can manufacture the array pattern with high density only by one SADP process, only one high-level immersion lithography is required, and the manufacturing cost can be greatly reduced compared with the conventional method that the same density array pattern can be manufactured by multiple (e.g. more than four) complicated and expensive SADP processes.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts. In the drawings:

FIGS. 1A, 1B, 2-5, 6A, 6B, 7A, 7B, 8-15, 16A, 16B, 17 are schematic illustrations of a semiconductor structure at various stages of manufacture, according to an embodiment of the present invention, wherein FIG. 1B is a schematic cross-sectional view taken along line B-B of the top view schematic illustration of FIG. 1A;

FIG. 6B is a schematic cross-sectional view taken along line B-B of the top view of FIG. 6A, respectively;

FIG. 7B is a schematic cross-sectional view taken along line B-B of the top view of FIG. 7A, respectively;

fig. 16B is a schematic cross-sectional view taken along line B-B of the top view of fig. 16A, respectively.

Reference numerals

10 substrate

11: cover layer (cap layer)

Layer of target material

12-1: tungsten nitride layer

12-2 tungsten layer

120a target array Pattern

120b target perimeter pattern

Carbide layer 13

14,18 dielectric layer

15,150 nitrogen-containing layer

16,160,21,210,34,340 polysilicon layer

17,22,220,25,250,31,310,35,350 carbon-containing layer

21a first array pattern

21b first peripheral pattern

211,212,241,242,271,272,291,292,371,372 opening

23,230,26,260,36 antireflection layer

24,27,37,46 patterning masking layer

24a,24b,27a,27b,37a,37b mask pattern

25S sacrificial pattern layer

25S-a first sacrificial pattern

25S-b second sacrificial pattern

29,290 polysilicon pattern layer

29a second array pattern

29b second peripheral pattern (final peripheral pattern)

290a final array Pattern

32,320 nitride layer

32a first nitride pattern

32b second nitride Pattern

33,330 silicon oxide layer

38 core pattern layer

38a first core Pattern

38b second core Pattern

41,410 spacer Material layer

42,420,42R planarization layer

43 patterning the stack layer

43a first Stack

43b second Stacking

43' patterning a stack of materials

43a' first Material Stack (third array Pattern)

43b' of a second material stack

A1 array region

A2 peripheral area

B-B: line

D1, D2, D3, dc Direction

ML-1 first Material Stack

ML-2 second Material Stack

L1, L2, L3 Pattern transfer layer

Detailed Description

Referring to fig. 1A and 1B, a substrate 10 and a first material layer ML-1 are provided, and the substrate 10 includes an array region A1 and a peripheral region A2. In an embodiment, the material of the substrate 10 may comprise a semiconductor material. In one embodiment, the substrate 10 is a material including silicon, gallium arsenide, gallium nitride, germanium silicide, other suitable materials, or combinations of the foregoing. In one embodiment, the substrate 10 is a silicon on insulator (soi) substrate. Various features, such as buried word lines, isolation structures, bit lines, etc., may be formed in the substrate 10 and above the substrate 10, and are omitted for simplicity and clarity.

The first material layer ML-1 is formed on the substrate 10 and covers the array region A1 and the peripheral region A2. The first material layer ML-1 comprises a plurality of materials, which may include, for example, a dielectric layer 14, a pattern transfer layer L1, a dielectric layer 18, and a pattern transfer layer L2 sequentially formed on the substrate 10. In an embodiment, the plurality of material layers included in the first material layer stack ML-1 may be formed by a method including Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), spin-on coating, other suitable processes, or a combination thereof. In one embodiment, dielectric layers 14 and 18 are comprised of an insulating material, such as silicon nitride (SiN). In one example, the thickness of dielectric layer 18 is about (but not limited to) 30nm and the thickness of dielectric layer 14 is about (but not limited to) 70nm.

In one embodiment, the pattern transfer layer L1 includes a nitrogen-containing layer 15, a polysilicon layer 16, and a carbon-containing layer 17 sequentially formed over the dielectric layer 14. The nitrogen-containing layer 15 is, for example, comprised of a different material than the dielectric layer 14. In this example, the nitrogen-containing layer 15 is an oxygen-rich silicon oxynitride (O-rich SiON). The carbon-containing layer 17 comprises a carbide, such as diamond-like carbon, amorphous carbon film, high selectivity transparent carbon-containing layer, and may be, but is not limited to, about 70nm to about 100nm in thickness. In this example, carbon-containing layer 17 is a high selectivity transparent carbon-containing layer. Here, the pattern transfer layer L1 is described as including the nitrogen-containing layer 15, the polysilicon layer 16, and the carbon-containing layer 17, but the invention is not limited thereto, and the pattern transfer layer L1 may be a combination of other material layers suitable for pattern transfer in other embodiments.

In one embodiment, the pattern transfer layer L2 includes a polysilicon layer 21, a carbon-containing layer 22, and an anti-reflection layer 23 sequentially formed over the dielectric layer 18. The carbon-containing layer 22 includes, for example, carbides such as diamond-like carbon, amorphous carbon film, high-selectivity transparent carbon-containing layers. In this example, the carbon-containing layer 22 is a spun-on carbon layer. The material of the antireflection layer 23 includes, for example, an organic polymer, carbon, silicon oxynitride, or the like. Here, the pattern transfer layer L2 is described as including the nitrogen-containing layer 15, the polysilicon layer 16, and the carbon-containing layer 17, but the present invention is not limited thereto, and in other embodiments, the pattern transfer layer L2 may be a combination of other material layers suitable for pattern transfer.

In one embodiment, the target material layer 12 and other material layers are disposed between the substrate 10 and the first material layer ML-1 to cover the array region A1 and the peripheral region A2. For example, between the substrate 10 and the first material layer ML-1, a cap layer (cap layer) 11, a target material layer 12, and a carbide layer 13 are sequentially formed on the substrate 10. The cap layer 11, the target material layer 12, and the carbide layer 13 may be formed by, for example, PVD, CVD, ALD, spin coating, other suitable processes, or combinations of the foregoing.

The cap layer 11 is, for example, a silicon nitride layer or other suitable insulating material. The target material layer 12 is, for example, a single layer or a plurality of layers of conductive material. In one embodiment, the target material layer 12 may comprise tungsten, tungsten nitride, copper, aluminum copper alloy, polysilicon, silicon germanium, other suitable conductive materials, or combinations of the foregoing. In this example, the target material layer 12 may include, for example, a tungsten nitride layer 12-1 and a tungsten layer 12-2. The carbide layer 13 includes, for example, diamond-like carbon, amorphous carbon film, and high-selectivity transparent carbon-containing layer (high-selectivity transparent carbon-containing layer). In this example, the carbide layer 13 is a highly selective transparent carbon-containing layer.

Referring to fig. 1A and 1B, a patterned mask layer 24 (e.g., a patterned photoresist) is provided over the first material layer ML-1, wherein the patterned mask layer 24 exposes a portion of the top surface of the first material layer ML-1. The patterned mask layer 24 includes a mask pattern 24a and a mask pattern 24b, which are formed on the anti-reflective layer 23 in the array region A1 and the peripheral region A2, respectively, and expose a portion of the top surface of the anti-reflective layer 23. In addition, the mask pattern 24a includes an opening 241, and the mask pattern 24b includes an opening 242.

Next, referring to fig. 1A-1B, 2-5, 6A and 6B, the present invention first defines a final peripheral pattern (e.g., the second peripheral pattern 29B shown in fig. 6A and 6B) in the peripheral region A2 and defines a line pattern (e.g., the second array pattern 29a shown in fig. 6A and 6B) along a specific direction in the array region A1 by a two-stage photolithography and etching process. In summary, the first array pattern 21A and the first peripheral pattern 21B (fig. 3) with larger line widths are formed by the photolithography process of the first stage (as illustrated in fig. 1A-1B and fig. 2-3), and then the photolithography process of the second stage (as illustrated in fig. 4-5 and fig. 6A-6B) is performed to further increase the pattern density of the first array pattern 21A and the first peripheral pattern 21B to form the second array pattern 29a and the second peripheral pattern 29B (fig. 6A-6B).

Referring to fig. 1A-1B and fig. 2, the patterned mask layer 24 is used as a mask to remove the pattern transfer layer L2 not covered by the patterned mask layer 24. In one embodiment, for example, a dry etching process is performed to remove the portions of the anti-reflection layer 23 exposed by the openings 241 and 242 and the portions of the underlying carbon-containing layer 22 and the underlying polysilicon layer 21. After etching, the pattern of the patterned mask layer 24 is transferred to the underlying pattern transfer layer L2 to form an anti-reflective layer 230, a carbon-containing layer 220, and a polysilicon layer 210, as shown in FIG. 2. In this exemplary step, dielectric layer 18 may act as an etch stop layer.

Thereafter, as shown in FIG. 3, the patterned masking layer 24, the carbon-containing layer 220, and the anti-reflective layer 230 are removed, leaving the polysilicon layer 210. The polysilicon layer 210 includes a first array pattern 21a in the array region A1 and a first peripheral pattern 21b in the peripheral region A2. In addition, the first array pattern 21a includes openings 211, and the first peripheral pattern 21b includes openings 212. Openings 211 and 212 are portions of the top surface of dielectric layer 18 that are exposed. In one embodiment, the first array pattern 21a extends along the direction D2, for example. Further, the first array pattern 21a and the first peripheral pattern 21b are separated in the direction D1, for example.

Next, as shown in fig. 4, a carbon-containing layer 25 and an anti-reflective layer 26 are sequentially formed on the polysilicon layer 210. Methods of forming carbon-containing layer 25 and anti-reflective layer 26 may include PVD, CVD, ALD, spin coating, other suitable processes, or combinations of the foregoing. The carbon-containing layer 25 completely covers the first array pattern 21a and the first peripheral pattern 21b, and fills the openings 211 and 212. The carbon-containing layer 25 includes, for example, carbides such as diamond-like carbon, amorphous carbon films, high-selectivity transparent carbon-containing layers. In this example, the carbon-containing layer 25 is a spun-on carbon layer. The anti-reflective layer 26 is, for example, comprised of an organic polymer, carbon, silicon oxynitride, or the like.

Referring to fig. 4, a patterned mask layer 27 (e.g., a patterned photoresist layer) is formed on the anti-reflective layer 26, wherein the patterned mask layer 27 includes a mask pattern 27a and a mask pattern 27b, which are formed on the anti-reflective layer 26 in the array region A1 and the peripheral region A2, respectively, and expose a portion of the top surface of the anti-reflective layer 26. In addition, the mask pattern 27a includes an opening 271, and the mask pattern 27b includes an opening 272. Further, the patterned mask layer 27 is offset from the pattern of the polysilicon layer 210 (i.e., the pattern of the patterned mask layer 24), for example, in the direction D1. For example, as shown in fig. 4, the opening 271 of the mask pattern 27a corresponds to the first array pattern 21a of the underlying polysilicon layer 210, and the opening 272 of the mask pattern 27b corresponds to the first peripheral pattern 21b of the underlying polysilicon layer 210. In one embodiment, the extending direction of the mask pattern 24a is substantially the same as the extending direction of the mask pattern 27 a.

It should be noted that the mask pattern 27b in the peripheral area A2 in fig. 4 only shows one exemplary pattern adjacent to the array area A1, and the density of the peripheral pattern in other areas of the peripheral area A2 not shown may also be increased by staggering the patterns in the array area A1, so that the actual pattern of the mask pattern 27b depends on the application design.

Next, as shown in FIG. 5, the anti-reflection layer 26 and the carbon-containing layer 25, which are not covered with the patterned mask layer 27, are removed using the patterned mask layer 27 as a mask. In one embodiment, the anti-reflective layer 26 exposed by the openings 271 and 272 and the corresponding portion of the carbon-containing layer 25 therebelow are removed, for example, by a dry etching process. After etching, the pattern of the patterned masking layer 27 is transferred to the underlying layer to form a carbon-containing layer 250 and an anti-reflective layer 260, as shown in FIG. 5. In this exemplary step, dielectric layer 18 may act as an etch stop layer. Thereafter, the patterned mask layer 27 is removed, for example, by an ashing process.

As shown in fig. 5, the stacked carbon-containing layer 250 and the anti-reflection layer 260 constitute a sacrificial pattern layer 25S. And the sacrificial pattern layer 25S includes first sacrificial patterns 25S-a in the array region A1 and second sacrificial patterns 25S-b in the peripheral region A2. In one embodiment, the first sacrificial patterns 25S-a extend along the direction D2, for example. Further, the first sacrificial pattern 25S-a and the second sacrificial pattern 25S-b are separated in the direction D1, for example. Further, in this example, the first sacrificial patterns 25S-a and the first array patterns 21a in the array region A1 are alternately disposed on the dielectric layer 18. The second sacrificial patterns 25S-b in the peripheral area A2 cover a portion of the first peripheral patterns 21b or are staggered with a portion of the first peripheral patterns 21b according to the peripheral pattern to be formed.

Next, as shown in fig. 6A and 6B, the dielectric layer 18 and the pattern transfer layer L1 which are not covered by the sacrificial pattern layer 25S and the polysilicon layer 210 are removed by using the sacrificial pattern layer 25S and the polysilicon layer 210 as masks. In one embodiment, the dielectric layer 18 exposed by the openings of the sacrificial pattern layer 25S and the polysilicon layer 210 and the corresponding portions of the underlying carbon-containing layer 17, the polysilicon layer 16 and the nitrogen-containing layer 15 are removed, for example, by a dry etching process. After etching, the pattern of the sacrificial pattern layer 25S and the polysilicon layer 210 is transferred to the underlying dielectric layer 18 and the pattern transfer layer L1 to form a remaining dielectric layer (not shown), a remaining carbon-containing layer (not shown), the polysilicon layer 160, and the nitrogen-containing layer 150. In this exemplary step, the dielectric layer 14 serves as an etch stop layer.

Thereafter, the sacrificial pattern layer 25S, the polysilicon layer 210, the remaining dielectric layer 18, and the remaining carbon-containing layer 17 may be removed by one or more steps including an ashing process, an etching process, and the like. As shown in fig. 6B, the polysilicon layer 160 and the nitrogen-containing layer 150 constitute a polysilicon pattern layer 29. The polysilicon pattern layer 29 includes a second array pattern 29a in the array region A1 and a second peripheral pattern 29b in the peripheral region A2. In addition, the second array pattern 29a includes an opening 291 therein, and the second peripheral pattern 29b includes an opening 292 therein. The openings 291 and 292 are portions of the top surface of the dielectric layer 14 that are exposed.

To this end, the final peripheral pattern in the peripheral region A2 (i.e., the second peripheral pattern 29 b) is defined by the two-stage photolithography process, and the pattern extending along a specific direction in the array region A1 (i.e., the second array pattern 29 a) is defined while the final peripheral pattern 29b in the peripheral region A2 is defined. Next, referring to fig. 7A, 7B, and 8-13, the present invention uses a self-aligned double patterning (SADP) process to define a pattern (e.g., the third array pattern 43a' of fig. 13) extending along another direction in the array region A1.

Referring to fig. 7A and 7B, a second material layer ML-2 is formed over the polysilicon pattern layer 29. The second material layer ML-2 comprises a plurality of materials, for example, a carbon-containing layer 31, a nitride layer 32, a silicon oxide layer 33, and a pattern transfer layer L3 sequentially formed on the polysilicon pattern layer 29. The formation method of the multiple material layers included in the second material layer ML-2 may include, for example, PVD, CVD, ALD, spin coating, other suitable processes, or a combination thereof. The carbon-containing layer 31 completely covers the second array pattern 29a and the second peripheral pattern 29b and fills the openings 291 and 292. The carbon-containing layer 31 includes, for example, diamond-like carbon, amorphous carbon film, and high-selectivity transparent carbon-containing layer. In this example, the carbon-containing layer 31 is a spin-on carbon layer. The nitride layer 32 is, for example, comprised of a different material than the dielectric layer 14. In this example, the nitride layer 32 may comprise nitrogen-rich silicon oxynitride (N-rich SiON), for example. The silicon oxide layer 33 may include, for example, a Tetraethyl orthosilicate (TEOS) layer.

In one embodiment, the pattern transfer layer L3 includes a polysilicon layer 34, a carbon-containing layer 35, and an anti-reflective layer 36 sequentially formed over the silicon oxide layer 33. The carbon-containing layer 35 includes, for example, carbides such as diamond-like carbon, amorphous carbon film, high-selectivity transparent carbon-containing layers. In this example, the carbon-containing layer 35 is a spun-on carbon layer. The material of anti-reflective layer 36 includes, for example, an organic polymer, carbon, silicon oxynitride, or the like. Here, the pattern transfer layer L3 is illustrated as including the polysilicon layer 34, the carbon-containing layer 35, and the anti-reflection layer 36, but the invention is not limited thereto, and in other embodiments, the pattern transfer layer L3 may be a combination of other material layers suitable for pattern transfer.

Referring to fig. 7A and 7B, a patterned mask layer 37 (e.g., a patterned photoresist) is formed on the second material layer ML-2, wherein the patterned mask layer 37 exposes a portion of the top surface of the second material layer ML-2. The patterned mask layer 37 includes a mask pattern 37a and a mask pattern 37b, which are formed on the anti-reflection layer 36 in the array region A1 and the peripheral region A2, respectively, and expose a portion of the top surface of the anti-reflection layer 36. In addition, the mask pattern 37a includes an opening 371, and the mask pattern 37b includes an opening 372.

As shown in fig. 7A and 7B, the mask pattern 37A includes line-shaped patterns spaced apart in the direction D1 and extending along the direction Dc. The direction Dc has an angle greater than 0 degree and less than 90 degrees with the direction D1, but the invention is not limited thereto, and in other embodiments, the mask pattern 37a may also include line-shaped patterns separated in the direction D2 and extending substantially along the direction D1.

Next, referring to fig. 8, the patterned mask layer 37 is used as an etching mask to remove the pattern transfer layer L3 not covered by the patterned mask layer 37. In one embodiment, the anti-reflective layer 36 exposed by the openings 371 and 372 and the portions of the underlying carbon-containing layer 35 and the polysilicon layer 34 are removed, for example, by a dry etching process. After etching, the pattern of the patterned mask layer 37 is transferred to the underlying pattern transfer layer L3 to form the remaining anti-reflection layer 36 (not shown), the carbon-containing layer 350 and the polysilicon layer 340. In this exemplary step, the silicon oxide layer 33 acts as an etch stop.

Thereafter, the patterned mask layer 37 and the remaining anti-reflection layer 36 may be removed by processes including an ashing process, an etching process, and the like. As shown in fig. 8, the carbon-containing layer 350 and the polysilicon layer 340 form the core pattern layer 38. The core pattern layer 38 includes a first core pattern 38a in the array region A1 and a second core pattern 38b in the peripheral region A2.

Next, as shown in fig. 9, a spacer material layer 41 is deposited over the silicon oxide layer 33 and the core pattern layer 38. The spacer material layer 41 conformably covers the core patterning layer 38. For example, the spacer material layer 41 covers the top surfaces and sidewalls of the first and second core patterns 38a and 38b, and covers the exposed portion of the silicon oxide layer 330. The spacer material layer 41 may comprise an oxide, for example, and the formation method thereof may include PVD, CVD, ALD, spin coating, other suitable processes, or a combination thereof. The spacer material layer 41 may comprise the same or different material as the silicon oxide layer 33. In this example, the spacer material layer 41 is a Tetraethylorthosilicate (TEOS) layer.

Thereafter, as shown in fig. 10, a planarization layer 42 is formed over the spacer material layer 41. The planarization layer 42 completely covers the spacer material layers 41 and fills the gaps between the spacer material layers 41. Planarization layer 42 may comprise, for example, an organic dielectric layer, such as diamond-like carbon, amorphous carbon film, highly selective transparent carbon-containing layer, or other suitable material, and may be formed by PVD, CVD, ALD, spin-on coating, other suitable process, or combinations thereof. In this example, planarization layer 42 is a spun-on carbon layer.

Next, as shown in fig. 11, a portion of the planarization layer 42 and a portion of the spacer material layer 41 are removed until the top surface of the core pattern layer 38 is exposed. The method of removing part of the planarization layer 42 and part of the spacer material layer 41 may include, for example, an etch-back process or a chemical mechanical polishing process. After the removal step, the remaining planarization layer 42R is filled between the remaining spacer material layers 41, and the top surface of the planarization layer 42R is substantially flush with the top surface of the spacer material layers 41.

Then, referring to fig. 12, the planarization layer 42R and the core pattern layer 38 are used as a mask to remove the spacer material layer 41 and the silicon oxide layer 33 that are not covered by the planarization layer 42R and the core pattern layer 38, so as to form a patterned stacked layer 43. In one embodiment, the spacer material layer 41 and the silicon oxide layer 33 not covered by the planarization layer 42R and the core pattern layer 38 are removed by, for example, a dry etching process until the nitride layer 32 is exposed. In this exemplary step, the nitride layer 32 may act as an etch stop.

As shown in fig. 12, the patterned stack layer 43 formed after etching includes two three-layer material stacks arranged alternately. Wherein the first three-layer material stack comprises, from top to bottom, a carbon-containing layer 350, a polysilicon layer 340, and a silicon oxide layer 330; another three-layer material stack comprises, from top to bottom, a planarization layer 420, a spacer material layer 410, and a silicon oxide layer 330. Furthermore, if the formed area is used for differentiation, the patterned stack layer 43 includes a plurality of first stacks 43a in the array area A1 and a plurality of second stacks 43b in the peripheral area A2.

Referring to fig. 13, the carbon-containing layer 350 and the planarization layer 420 are removed to form a patterned material stack layer 43'. The patterned material stack layer 43' includes a first material stack 43a ' in the array region A1 and a second material stack 43b ' in the peripheral region A2. In this example, the first material stack 43a' may be used as the third array pattern. In this example, the third array pattern 43a' includes line-type patterns spaced apart in the direction D1 and extending along the direction Dc (shown in fig. 7A). In other embodiments, the mask pattern 37a may also include line-shaped patterns spaced apart in the direction D2 and extending substantially along the direction D1.

To this end, the present invention defines a pattern (i.e., the third array pattern 43 a') extending in another direction in the array region A1 by using the above-described SADP process. Next, referring to fig. 13-15, 16A, 16B and related process descriptions, the present invention proceeds to etch the underlying material layer by using the third array pattern 43a' as an etching mask through an etching process to convert the underlying second array pattern 29a into a final array pattern (e.g., the final array pattern 290a shown in fig. 16A and 16B).

Referring again to fig. 13, a patterned masking layer 46 (e.g., a patterned photoresist) is formed on the second material stack 43b' and the nitride layer 32 in the peripheral region A2. The patterned mask layer 46 covers the second material stacks 43b ' and fills the openings between the second material stacks 43b ', exposing the third array patterns 43a ' of the array region A1. In one embodiment, the patterned mask layer 46 may further cover a portion of the array region A1 adjacent to the peripheral region A2 (as shown in fig. 13). However, the present invention is not limited thereto, and it can be determined whether the patterned mask layer 46 covers a portion of the array region A1 adjacent to the boundary according to a target pattern to be formed at the boundary between the array region A1 and the peripheral region A2.

Next, referring to fig. 14, the exposed portion of the underlying material layer is removed, for example, the exposed portion of the nitride layer 32 is removed by etching, using the patterned mask layer 46 and the third array pattern 43a' as masks, until the carbon-containing layer 31 is exposed, and the remaining nitride layer 32 forms the nitride layer 320. Next, the patterned mask layer 46 and the patterned material stack layer 43' may be removed by one or more steps including an ashing process, an etching process, and the like. In this example, after the patterned mask layer 46 is removed, the patterned material stack layer 43' is removed, leaving the nitride layer 320. As shown in fig. 14, the nitride layer 320 includes a first nitride pattern 32a in the array region A1 and a second nitride pattern 32b in the peripheral region A2.

Next, as shown in fig. 15, the carbon-containing layer 31 and the polysilicon pattern layer 29 which are not covered by the nitride layer 320 are removed by using the nitride layer 320 as a mask, thereby forming a carbon-containing layer 310 and a polysilicon pattern layer 290. In one embodiment, the carbon-containing layer 31 not covered by the first nitride pattern 32a and the corresponding portion of the underlying second array pattern 29a are removed, for example, by a dry etching process, to form the nitride layer 320, the carbon-containing layer 310 and the final array pattern 290a. In this exemplary step, the dielectric layer 14 may serve as an etch stop layer.

Thereafter, referring to fig. 16A and 16B, the nitride layer 320 and the carbon-containing layer 310 may be removed by one or more steps including an ashing process, an etching process, and the like, thereby exposing the polysilicon pattern layer 290. In one embodiment, a portion of the dielectric layer 14 may be removed during this removal step. As shown in fig. 16A and 16B, the polysilicon pattern layer 290 includes a final array pattern 290a and a second peripheral pattern (final peripheral pattern) 29B. In particular, the present invention can define a high-density target array pattern after the two-stage photolithography step illustrated in fig. 1A, 1B, 2 to 3, 4 to 5, 6A and 6B, and the SADP step illustrated in fig. 7A, 7B and 8 to 15. Since the present invention only needs one SADP step, and thus only needs one high-order immersion lithography (immersion lithography) technique, the manufacturing cost can be greatly reduced.

Next, referring to fig. 17, the pattern of the polysilicon pattern layer 290 may be transferred into the target material layer 12 by an etching process. For example, in this example, the polysilicon pattern layer 290 is used as a mask to etch the underlying material layers, such as the dielectric layer 14, the carbide layer 13, the target material layer 12, and the cap layer 11. After the etching, the final array pattern 290a and the second peripheral pattern 29b of the polysilicon pattern layer 290 are transferred to the target material layer 12, so as to form the target array pattern 120a and the target peripheral pattern 120b in the target material layer 12, respectively. In one application of a DRAM device, the target array pattern 120a may correspond to a pattern of capacitive contact pads (pads).

According to the method for manufacturing a semiconductor structure of the present invention, the final peripheral pattern of the peripheral region A2 and the line pattern of the array region A1 along a first direction are simultaneously defined by the two-stage photolithography and etching process illustrated in fig. 1A, 1B, 2 to 3, 4, 6A, and 6B. Next, after the line pattern of the array area A1 along a second direction is defined by the SADP process illustrated in fig. 7A, 7B, and 8 to 15, the line pattern of the array area A1 along the first direction is etched by using the line pattern of the second direction as an etching mask to obtain a final array pattern of the array area A1. Finally, the final array pattern and the final peripheral pattern are transferred to the target material layer at the same time, so as to form the target array pattern and the target peripheral pattern of the invention on the target material layer.

In summary, since the pattern of the peripheral region A2 is defined and the pattern of the array region A1 along the first direction is defined, compared to the conventional process of separately manufacturing the array pattern and the peripheral pattern, the method for manufacturing the semiconductor structure of the present invention can simplify the process steps and reduce the cost. In addition, since the present invention can produce high density array patterns by only one SADP process, only one high-level immersion lithography is required, which can greatly reduce the manufacturing cost compared to the conventional method that can produce array patterns of the same density by using more (e.g., more than four) complicated and expensive SADP processes.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (14)

1. A method of fabricating a semiconductor structure, comprising:

forming a first material stack over a substrate, the substrate comprising an array region and a periphery region, wherein the first material stack covers the array region and the periphery region, and the first material stack comprises a first pattern transfer layer and a second pattern transfer layer;

forming a first patterned masking layer over the first stack of materials in the array region and the peripheral region, the first patterned masking layer exposing portions of a top surface of the first stack of materials;

removing a portion of the first material stack using the first patterned mask layer as a mask to transfer the pattern of the first patterned mask layer to the second pattern transfer layer to form a first array pattern and a first periphery pattern in the array region and the periphery region, respectively;

providing a second patterned mask layer over the first array pattern and the first peripheral pattern corresponding to the array region and the peripheral region, wherein the second patterned mask layer is staggered from the first patterned mask layer;

using the second patterned mask layer as a mask to transfer the pattern of the second patterned mask layer downward to form a first sacrificial pattern and a second sacrificial pattern in the array region and the peripheral region; and

and performing pattern transfer on the first array pattern and the first sacrificial pattern to form a second array pattern in the array area, and simultaneously performing pattern transfer on the first peripheral pattern and the second sacrificial pattern to form a second peripheral pattern in the peripheral area.

2. The method of claim 1, wherein a first dielectric layer is disposed between the substrate and the first pattern transfer layer, and the second array pattern and the second peripheral pattern are formed on the first dielectric layer.

3. The method of claim 2, wherein a second dielectric layer is disposed between the second pattern transfer layer and the first pattern transfer layer, and wherein the first array pattern, the first peripheral pattern, the first sacrificial pattern, and the second sacrificial pattern are formed on the second dielectric layer.

4. The method of claim 1, further comprising, after forming the first array pattern and the first periphery pattern:

depositing a carbon-containing layer on the first array pattern and the first peripheral pattern to completely cover the first array pattern and the first peripheral pattern; and

forming an anti-reflective layer over the carbon-containing layer, wherein the second patterned masking layer is formed over the anti-reflective layer,

wherein, when the second patterned mask layer is used as a mask, the pattern of the second patterned mask layer is transferred into the anti-reflection layer and the carbon-containing layer to form the first sacrificial pattern and the second sacrificial pattern.

5. The method of fabricating a semiconductor structure of claim 1, further comprising:

forming a second material layer on the second array pattern and the second peripheral pattern;

forming a third patterned masking layer over the second stack of materials in the array region and the peripheral region; and

performing a self-aligned double patterning process according to the pattern of the third patterned mask layer to form a patterned stack of materials, wherein the patterned stack of materials includes a third array pattern formed in the array region.

6. The method of fabricating a semiconductor structure according to claim 5, wherein the step of forming the second material stack further comprises:

depositing a carbon-containing layer on the second array pattern and the second peripheral pattern;

depositing a nitride layer on the carbon-containing layer;

depositing a silicon oxide layer on the nitride layer; and

forming a third pattern transfer layer on the silicon oxide layer,

wherein the third patterned mask layer is formed on the third pattern transfer layer.

7. The method of fabricating a semiconductor structure according to claim 6, wherein the self-aligned double patterning process comprises:

transferring the pattern of the third patterned mask layer to the third pattern transfer layer to form a core pattern layer, wherein the core pattern layer includes a first core pattern and a second core pattern formed in the array region and the peripheral region;

depositing a spacer material layer over the silicon oxide layer and the core pattern layer, the spacer material layer conformally covering the core pattern layer;

forming a planarization layer to completely cover the spacer material layer;

removing part of the planarization layer and part of the spacer material layer until the top surface of the core pattern layer is exposed, and leaving the planarization layer filled between the remaining spacer material layers;

removing the remaining part of the spacer material layer to expose the silicon oxide layer;

removing the spacer material layer and the silicon oxide layer which are not covered by the remaining part of the planarization layer and the core pattern layer by using the remaining part of the planarization layer and the core pattern layer as a mask until the nitride layer is exposed; and

removing the carbon-containing layer and the remaining planarization layer to form the patterned material stack layer.

8. The method of claim 5, wherein a pattern of the third patterned masking layer extends at an angle of less than 90 degrees to the first direction, or wherein the pattern of the third patterned masking layer extends along the first direction.

9. The method of fabricating a semiconductor structure of claim 5, further comprising:

forming a fourth patterned mask layer to cover the peripheral region and expose the third array pattern of the array region; and

and removing the exposed part of the lower material layer and the corresponding part of the second array pattern by using the fourth patterned mask layer and the third array pattern as masks, so as to convert the second array pattern into a final array pattern.

10. The method of claim 9, wherein a layer of target material is disposed between the substrate and the first material stack to cover the array region and the peripheral region.

11. The method of fabricating a semiconductor structure of claim 10, further comprising:

simultaneously transferring the final array pattern of the array region and the second peripheral pattern of the peripheral region to the layer of target material to form a target array pattern and a target peripheral pattern in the array region and the peripheral region, respectively.

12. The method of fabricating a semiconductor structure according to claim 11, wherein the target array pattern is a capacitive contact pad in the array region of a dynamic random access memory device.

13. The method of claim 11, further comprising, between the substrate and the first material stack:

a carbon-containing layer formed on the target material layer and covering the array region and the peripheral region,

wherein the third array pattern is over the carbon-containing layer and the second array pattern and the second peripheral pattern are in the carbon-containing layer.

14. The method of fabricating a semiconductor structure of claim 13, further comprising:

a first dielectric layer formed on the target material layer, wherein the first dielectric layer is on the carbon-containing layer,

wherein the final array pattern of the array region and the second peripheral pattern of the peripheral region are formed on the first dielectric layer after the step of converting the second array pattern into the target array pattern.

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