CN115497842B - Method for preparing semiconductor structure and semiconductor structure - Google Patents
Method for preparing semiconductor structure and semiconductor structure Download PDFInfo
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- CN115497842B CN115497842B CN202211460328.2A CN202211460328A CN115497842B CN 115497842 B CN115497842 B CN 115497842B CN 202211460328 A CN202211460328 A CN 202211460328A CN 115497842 B CN115497842 B CN 115497842B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
Abstract
The application relates to a preparation method of a semiconductor structure and the semiconductor structure. A method of fabricating a semiconductor structure comprising: providing a device layer, wherein a plurality of conducting layers which are distributed at intervals are formed on the device layer; forming a passivation stack over the device layer, the passivation stack overlying each of the conductive layers; wherein at least an upper surface of the passivation stack between the conductive layers is arcuate. According to the preparation method of the semiconductor structure, the passivation lamination layer is formed on the device layer, the passivation lamination layer can play a role in fully isolating and protecting the device layer, a plurality of conducting layers which are distributed at intervals are formed on the device layer, the passivation lamination layer covers the conducting layers, the conducting layers can be isolated and protected, and at least the upper surface of the passivation lamination layer between the conducting layers is an arc-shaped surface, so that the problem that the semiconductor structure is invalid due to the fact that the passivation layer has sharp corners to cause subsequent plastic package to break is solved, and the device performance is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the development of semiconductor technology, the related art or products of semiconductor process and semiconductor structures are also continuously improved. Chip packaging is a critical process in chip production, and in order to avoid the effect of the diffusion of external impurities into the semiconductor device and the influence on the device, a protective layer must be deposited during the chip manufacturing process.
The device is generally packaged by a single passivation layer and a single plastic sealing layer, but sharp corners are generated after the passivation layer is deposited, and after the passivation layer is packaged by the plastic sealing layer, the plastic sealing layer is expanded and broken due to stress problems caused by the sharp corners, so that the semiconductor device fails due to leakage caused by the broken packaging layer.
Disclosure of Invention
Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure for solving the above-mentioned problems.
In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a semiconductor structure, including:
providing a device layer, wherein a plurality of conducting layers which are distributed at intervals are formed on the device layer;
forming a passivation stack over the device layer, the passivation stack overlying each of the conductive layers; wherein at least an upper surface of the passivation stack between the conductive layers is arcuate.
According to the preparation method of the semiconductor structure, the passivation lamination layer is formed on the device layer, the passivation lamination layer can play a role in fully isolating and protecting the device layer, a plurality of conducting layers which are distributed at intervals are formed on the device layer, the passivation lamination layer covers the conducting layers, the conducting layers can be isolated and protected, and at least the upper surfaces of the passivation lamination layers between the conducting layers are arc-shaped surfaces, so that the problem that the semiconductor structure is invalid due to the fact that the passivation layers have sharp corners to cause subsequent plastic package to break is solved, and the device performance is improved.
In one embodiment, the method further comprises:
and forming a plastic sealing layer on the surface of the passivation lamination layer far away from the conductive layer.
In one embodiment, the forming a passivation stack on the device layer includes:
forming a first passivation layer on the surface of the device layer and the surface of the conductive layer;
forming a second passivation layer on the surface of the first passivation layer far away from the device layer and the conductive layer, and forming a third passivation layer on the surface of the second passivation layer far away from the first passivation layer, wherein at least the upper surface of the third passivation layer between the adjacent conductive layers is an arc surface;
and forming a fourth passivation layer on the surface of the third passivation layer far away from the second passivation layer to obtain the passivation stack comprising the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer.
In one embodiment, the forming a second passivation layer on a surface of the first passivation layer away from the device layer and the conductive layer, and forming a third passivation layer on a surface of the second passivation layer away from the first passivation layer, includes:
forming a second passivation material layer on the surface of the first passivation layer far away from the device layer and the conductive layer, wherein the second passivation material layer right above the conductive layer is provided with a first sharp angle;
forming a third passivation material layer on the surface, far away from the first passivation layer, of the second passivation material layer, wherein the third passivation material layer right above the conductive layer is provided with a second sharp angle, and the third passivation material layer between the adjacent conductive layers is provided with a third sharp angle;
and carrying out rounding treatment on the first sharp angle, the second sharp angle and the third sharp angle to obtain the second passivation layer and the third passivation layer with smooth surfaces.
In one embodiment, an etching process is used to round the first sharp corner, the second sharp corner, and the third sharp corner.
In one embodiment, the second passivation material layer is formed using a high density plasma process; the second passivation material layer includes an oxide layer or a silicon nitride layer.
The present application also provides a semiconductor structure comprising:
the device layer is provided with a plurality of conductive layers which are distributed at intervals;
a passivation stack located on a surface of the device layer and covering each of the conductive layers; wherein at least an upper surface of the passivation stack between the conductive layers is arcuate.
According to the semiconductor structure, the plurality of conducting layers which are distributed at intervals are formed on the device layer, the passivation lamination layer is located on the surface of the device layer and covers the conducting layers, the passivation lamination layer can play a role in fully isolating and protecting the device layer and the conducting layers, and at least the upper surface of the passivation lamination layer located between the conducting layers is an arc-shaped surface, so that the problem that the semiconductor structure is invalid due to the fact that the passivation layer has sharp corners to cause subsequent plastic package to break is solved, and the device performance is improved.
In one embodiment, the semiconductor structure further comprises:
and the plastic layer is positioned on the surface of the passivation lamination layer far away from the device layer.
In one embodiment, the passivation stack comprises:
a first passivation layer located on the surfaces of the device layer and the conductive layer;
the second passivation layer is positioned on the surface of the first passivation layer, which is far away from the device layer and the conductive layer;
the third passivation layer is positioned on the surface of the second passivation layer far away from the first passivation layer; at least the upper surface of the third passivation layer positioned between the adjacent conductive layers is an arc-shaped surface;
and the fourth passivation layer is positioned on the surface of the third passivation layer far away from the second passivation layer.
In one embodiment, the thickness of the fourth passivation layer is 0.5 μm to 0.9 μm.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart illustrating steps of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a schematic cross-sectional view of the structure obtained in step S11 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 3 is a flowchart showing steps in the method for fabricating a semiconductor structure according to step S12;
FIG. 4 is a schematic cross-sectional view of the structure obtained in step S121 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 5 is a schematic cross-sectional view of the structure obtained in step S1221 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 6 is a schematic cross-sectional view of the structure obtained in step S1222 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 7 is a schematic cross-sectional view of the structure obtained in step S1223 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S123 in the method for fabricating a semiconductor structure according to one embodiment;
fig. 9 is a schematic cross-sectional structure of a structure obtained by forming a plastic layer on a surface of a passivation stack away from a conductive layer in a method for manufacturing a semiconductor structure according to an embodiment.
Reference numerals illustrate:
1. a conductive layer; 2. a passivation stack; 21. a first passivation layer; 22. a second passivation layer; 221. a second passivation material layer; 23. a third passivation layer; 231. a third passivation material layer; 24. a fourth passivation layer; 3. and (5) plastic sealing layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
With the development of semiconductor technology, the related art or products of semiconductor process and semiconductor structures are also continuously improved. Chip packaging is a critical process in chip production, and in order to avoid the effect of the diffusion of external impurities into the semiconductor device and the influence on the device, a protective layer must be deposited during the chip manufacturing process.
The device is generally packaged by a single passivation layer and a single plastic sealing layer, but sharp corners are generated after the passivation layer is deposited, after the passivation layer is packaged by the plastic sealing layer, the plastic sealing layer is expanded and broken due to stress problems caused by the sharp corners, so that inconvenience and loss are brought to packaging test, and the semiconductor device is disabled due to leakage caused by the broken packaging layer.
Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure for solving the above-mentioned problems.
In order to solve the above-mentioned problems, in one aspect, the present application provides a method for preparing a semiconductor structure, as shown in fig. 1, the method for preparing a semiconductor structure includes:
s11: providing a device layer, wherein a plurality of conducting layers which are arranged at intervals are formed on the device layer;
s12: forming a passivation stack over the device layer, the passivation stack covering the conductive layers; wherein at least the upper surface of the passivation stack between the conductive layers is arcuate.
Wherein, at least the upper surface of the passivation layer stack between the conductive layers is an arc surface, which may mean that the upper surface of the passivation layer stack between the conductive layers is an arc surface, or that the upper surface of the passivation layer stack between the conductive layers and the upper surface of the passivation layer stack above the conductive layers are both arc surfaces; in particular, an arcuate surface refers to a rounded transition surface without sharp corners.
According to the preparation method of the semiconductor structure, the passivation lamination layer is formed on the device layer, the passivation lamination layer can play a role in fully isolating and protecting the device layer, the device layer is provided with the plurality of conducting layers which are distributed at intervals, the passivation lamination layer covers the conducting layers, the conducting layers can be isolated and protected, and at least the upper surface of the passivation lamination layer between the conducting layers is an arc-shaped surface, so that the problem that the semiconductor structure is invalid due to the fact that the passivation layer has sharp corners to cause subsequent plastic package cracking is solved, and the device performance is improved.
In step S11, referring to fig. 2, a device layer is provided, and a plurality of conductive layers 1 are formed on the device layer at intervals.
Wherein, the material of the conductive layer 1 can be, but is not limited to, aluminum copper composite metal material; the thickness of the conductive layer 1 may be 2 μm to 4 μm, specifically, the thickness of the conductive layer 1 may be 2 μm, 2.8 μm, 3 μm, 3.5 μm or 4 μm, or may be other thicknesses between 2 μm to 4 μm, which is not limited by the specific embodiment illustrated.
In step S12, referring to fig. 3 to 8, a passivation layer stack 2 is formed on the device layer, and the passivation layer stack 2 covers each conductive layer 1; wherein at least the upper surface of the passivation stack 2 between the conductive layers 1 is curved.
In one embodiment, as shown in fig. 3, forming the passivation stack 2 on the device layer includes:
s121: forming a first passivation layer 21 on the surface of the device layer and the surface of the conductive layer 1;
s122: forming a second passivation layer 22 on the surface of the first passivation layer 21 far away from the device layer and the conductive layer 1, and forming a third passivation layer 23 on the surface of the second passivation layer 22 far away from the first passivation layer 21, wherein at least the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 is an arc surface;
s123: a fourth passivation layer 24 is formed on the surface of the third passivation layer 23 remote from the second passivation layer 22 to obtain a passivation stack comprising the first passivation layer 21, the second passivation layer 22, the third passivation layer 23 and the fourth passivation layer 24.
Wherein the first passivation layer 21 may be, but is not limited to, an ethyl silicate layer; the thickness of the first passivation layer 21 may be 0.9 μm to 1.3 μm, specifically, the thickness of the first passivation layer 21 may be 0.9 μm, 1 μm, 1.1 μm, 1.2 μm or 1.3 μm, or may be other thicknesses between 0.9 μm to 1.3 μm, which is not limited by the specific embodiment illustrated. The second passivation layer 22 may include, but is not limited to, any one of an oxide layer or a silicon nitride layer. The third passivation layer 23 may be, but is not limited to, a plasma enhanced tetraethyl orthosilicate layer. The fourth passivation layer 24 may be, but is not limited to, a silicon nitride layer; the thickness of the fourth passivation layer 24 may be 0.5 μm to 0.9 μm, specifically, the thickness of the fourth passivation layer 24 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm or 0.9 μm, or may be other thicknesses between 0.5 μm to 0.9 μm, which is not limited by the specific embodiment illustrated.
In step S121, referring to fig. 4, a first passivation layer 21 is formed on the surface of the device layer and the surface of the conductive layer 1.
The first passivation layer 21 may be formed on the surface of the device layer and the surface of the conductive layer 1 by chemical vapor deposition or atomic layer deposition.
In step S122, referring to fig. 5 to 7, a second passivation layer 22 is formed on the surface of the first passivation layer 21 away from the device layer and the conductive layer 1, and a third passivation layer 23 is formed on the surface of the second passivation layer 22 away from the first passivation layer 21, at least the upper surface of the third passivation layer 23 between adjacent conductive layers 1 is an arc surface.
Wherein, at least the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 is an arc surface, which may mean that the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 is an arc surface, or that the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 and the upper surface of the third passivation layer 23 above the conductive layers 1 are both arc surfaces; in particular, an arcuate surface refers to a rounded transition surface without sharp corners.
In one embodiment, forming the second passivation layer 22 on the surface of the first passivation layer 21 away from the device layer and the conductive layer 1, and forming the third passivation layer 23 on the surface of the second passivation layer 22 away from the first passivation layer 21 may include the following steps:
s1221: forming a second passivation material layer 221 on the surface of the first passivation layer 21 far from the device layer and the conductive layer 1, wherein the second passivation material layer 221 right above the conductive layer 1 has a first sharp angle, and the obtained structure is shown in fig. 5; wherein, a HDP (high density plasma, high-density plasma) deposition process may be used to form the second passivation material layer 221 on the surface of the first passivation layer 21 away from the device layer and the conductive layer 1; the second passivation material layer 221 may include, but is not limited to, any one of an oxide layer or a silicon nitride layer; the thickness of the second passivation material layer 221 may be 0.6 μm to 1.8 μm, specifically, the thickness of the second passivation material layer 221 may be 0.6 μm, 0.8 μm, 1 μm, 1.2 μm, 1.4 μm, 1.6 μm or 1.8 μm, or may be other thicknesses between 0.6 μm to 1.8 μm, which is not limited by the illustrated embodiment; further, if the thickness of the conductive layer 1 is higher, so that the surface of the first passivation layer 21 located between the conductive layers 1 is far lower than the surface of the first passivation layer 21 located above the conductive layers 1, the second passivation material layer 221 may be a silicon nitride layer, and by introducing silane and nitrogen gas, a silicon nitride layer is formed on the surface of the first passivation layer 21 as the second passivation material layer 221, and the depth and width adopted in the forming process of the second passivation material layer 221 are relatively higher, which is suitable for the situation that the surface of the first passivation layer 21 located between the conductive layers 1 is far lower than the surface of the first passivation layer 21 located above the conductive layers 1.
S1222: forming a third passivation material layer 231 on the surface of the second passivation material layer 221 far from the first passivation layer 21, wherein the third passivation material layer 231 right above the conductive layers 1 has a second sharp angle, and the third passivation material layer 231 between adjacent conductive layers 1 has a third sharp angle, and the resulting structure is shown in fig. 6; wherein, a high-density plasma deposition process may be used to form a third passivation material layer 231 on the surface of the second passivation material layer 221 away from the first passivation layer 21, and the third passivation material layer 231 may be, but is not limited to, PETEOS (Plasma Enhanced Tetraethyl orthosilicate, plasma enhanced tetraethyl orthosilicate layer); the thickness of the third passivation material layer 231 may be 0.5 μm to 0.9 μm, and specifically, the thickness of the third passivation material layer 231 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm or 0.9 μm, or may be other thicknesses between 0.5 μm to 0.9 μm, which is not limited by the specific embodiment illustrated.
S1223: the first sharp corner, the second sharp corner and the third sharp corner are rounded to obtain a second passivation layer 22 and a third passivation layer 23 with rounded surfaces, and the obtained structures are shown in fig. 7.
When the second passivation material layer 221 is formed on the surface of the first passivation layer 21 far from the device layer and the conductive layer 1, the second passivation material layer 221 of the first layer is formed on the surface of the first passivation layer 21, and then the second passivation material layer 221 of the second layer is formed on the surface of the second passivation material layer 221 of the first layer, so as to obtain a denser second passivation material layer 221, namely a second passivation layer 22 with more uniform film quality can be obtained; the second passivation material layer 221 of the first layer is close in thickness to the second passivation material layer 221 of the second layer.
In one embodiment, the first sharp corner, the second sharp corner, and the third sharp corner may be rounded using an etching process.
Specifically, the first sharp corner, the second sharp corner and the third sharp corner are rounded to remove the sharp corners on the second passivation material layer 221 and the third passivation material layer 231, so as to obtain smoother surfaces, i.e. the surfaces of the second passivation layer 22 and the third passivation layer 23 are also arc-shaped surfaces, so that the surface of the fourth passivation layer 24 formed on the surface of the third passivation layer 23 is also arc-shaped surface, i.e. the surface of the passivation layer stack 2 is smooth and has no sharp corners, and the problem of stress caused by sharp corners can be solved.
In step S123, referring to fig. 8, a fourth passivation layer 24 is formed on the surface of the third passivation layer 23 away from the second passivation layer 22 to obtain the passivation stack 2 including the first passivation layer 21, the second passivation layer 22, the third passivation layer 23 and the fourth passivation layer 24.
Wherein, a fourth passivation layer 24 may be formed on the surface of the third passivation layer 23 away from the second passivation layer 22 by chemical vapor deposition or atomic layer deposition; at least the upper surface of the fourth passivation layer 24 between adjacent conductive layers 1 is arcuate.
Specifically, at least the upper surface of the fourth passivation layer 24 located between the adjacent conductive layers 1 is an arc surface, which may mean that the upper surface of the fourth passivation layer 24 located between the adjacent conductive layers 1 is an arc surface, or may mean that the upper surface of the fourth passivation layer 24 located between the adjacent conductive layers 1 and the upper surface of the fourth passivation layer 24 located above the conductive layers 1 are arc surfaces, that is, the surface of the fourth passivation layer 24 is a smooth surface.
It should be noted that the passivation layer stack 2 may further include a fifth passivation layer, a sixth passivation layer, a seventh passivation layer, and the like, that is, the number of passivation layers in the passivation layer stack 2 is not limited to the above-mentioned four passivation layers, and the number of passivation layers in the passivation layer stack 2 may be greater than four to meet the design requirement.
In one embodiment, referring to fig. 8, a fourth passivation layer 24 over the conductive layer 1 is in contact with the second passivation layer 22.
In one embodiment, as shown in fig. 9, after forming the passivation stack 2 on the device layer, further comprises: and forming a plastic sealing layer 3 on the surface of the passivation lamination layer 2 away from the conductive layer 1.
Wherein, the plastic sealing layer 3 is formed on the surface of the passivation lamination layer 2 far away from the conductive layer 1, and because the surface of the passivation lamination layer 2 is a smooth surface, the situation that the plastic sealing layer 3 expands to generate cracking caused by stress problems caused by sharp corners does not exist, so that the failure condition of the semiconductor structure caused by the cracking of the plastic sealing layer 3 due to the sharp corners is improved.
Specifically, the plastic layer 3 is formed to improve the sealability of the device; the plastic layer 3 may be, but is not limited to, an epoxy resin layer, which has advantages of low shrinkage, good heat resistance, strong sealing property, good insulation property, etc., so as to better protect the device.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of the embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or others.
The present application also provides a semiconductor structure, as shown in fig. 8, the semiconductor structure includes: a device layer and passivation stack 2; a plurality of conducting layers 1 which are arranged at intervals are formed on the device layer; the passivation stack 2 is located on the surface of the device layer and covers the conductive layers 1; wherein at least the upper surface of the passivation stack 2 between the conductive layers 1 is curved.
Wherein, at least the upper surface of the passivation layer stack 2 between the conductive layers 1 is an arc surface, which may mean that the upper surface of the passivation layer stack 2 between the conductive layers 1 is an arc surface, or that the upper surface of the passivation layer stack 2 between the conductive layers 1 and the upper surface of the passivation layer stack 2 above the conductive layers 1 are both arc surfaces; in particular, an arcuate surface refers to a rounded transition surface without sharp corners.
In the semiconductor structure in the above embodiment, the device layer is formed with the plurality of conductive layers 1 arranged at intervals, the passivation lamination layer 2 is located on the surface of the device layer and covers each conductive layer 1, the passivation lamination layer 2 can perform the function of fully isolating and protecting the device layer and the conductive layers 1, and at least the upper surface of the passivation lamination layer 2 located between the conductive layers 1 is an arc surface, so that the problem that the semiconductor structure fails due to the fact that the passivation layer has sharp corners to cause the subsequent plastic package to break is solved, and the device performance is improved.
In some embodiments, the material of the conductive layer 1 may be, but is not limited to, an aluminum copper composite metal material; the thickness of the conductive layer 1 may be 2 μm to 4 μm, specifically, the thickness of the conductive layer 1 may be 2 μm, 2.8 μm, 3 μm, 3.5 μm or 4 μm, or may be other thicknesses between 2 μm to 4 μm, which is not limited by the specific embodiment illustrated.
In one embodiment, as shown in fig. 9, the semiconductor structure further comprises: a plastic layer 3; the plastic layer 3 is located at the surface of the passivation stack 2 remote from the device layer.
The plastic sealing layer 3 is located on the surface of the passivation lamination layer 2 far away from the device layer, and because the surface of the passivation lamination layer 2 is a smooth surface, the situation that the plastic sealing layer 3 expands to generate cracking caused by stress problems caused by sharp corners does not exist, and the semiconductor structure fails due to the cracking of the plastic sealing layer 3 caused by the sharp corners is improved.
Specifically, the plastic sealing layer 3 can be, but is not limited to, an epoxy resin layer, and the epoxy resin has the advantages of low shrinkage, good heat resistance, strong sealing property, good insulativity and the like, so that the sealing property of the device is improved, and the device is better protected.
In one embodiment, still referring to fig. 8, the passivation stack 2 comprises: a first passivation layer 21, a second passivation layer 22, a third passivation layer 23, and a fourth passivation layer 24; the first passivation layer 21 is located on the surfaces of the device layer and the conductive layer 1; the second passivation layer 22 is located on the surface of the first passivation layer 21 remote from the device layer and the conductive layer 1; the third passivation layer 23 is located on the surface of the second passivation layer 22 remote from the first passivation layer 21; at least the upper surface of the third passivation layer 23 between adjacent conductive layers 1 is an arc surface; the fourth passivation layer 24 is located on the surface of the third passivation layer 23 remote from the second passivation layer 22.
Wherein, at least the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 is an arc surface, which may mean that the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 is an arc surface, or that the upper surface of the third passivation layer 23 between the adjacent conductive layers 1 and the upper surface of the third passivation layer 23 above the conductive layers 1 are both arc surfaces; in particular, an arcuate surface refers to a rounded transition surface without sharp corners.
In some embodiments, the first passivation layer 21 may be, but is not limited to, an ethyl silicate layer; the thickness of the first passivation layer 21 may be 0.9 μm to 1.3 μm, specifically, the thickness of the first passivation layer 21 may be 0.9 μm, 1 μm, 1.1 μm, 1.2 μm or 1.3 μm, or may be other thicknesses between 0.9 μm to 1.3 μm, which is not limited by the specific embodiment illustrated. The second passivation layer 22 may include, but is not limited to, any one of an oxide layer or a silicon nitride layer. The third passivation layer 23 may be, but is not limited to, a plasma enhanced tetraethyl orthosilicate layer. The fourth passivation layer 24 may be, but is not limited to, a silicon nitride layer; the thickness of the fourth passivation layer 24 may be 0.5 μm to 0.9 μm, specifically, the thickness of the fourth passivation layer 24 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm or 0.9 μm, or may be other thicknesses between 0.5 μm to 0.9 μm, which is not limited by the specific embodiment illustrated.
In one embodiment, referring to fig. 8, a fourth passivation layer 24 over the conductive layer 1 is in contact with the second passivation layer 22.
In one embodiment, at least the upper surface of the fourth passivation layer 24 between adjacent conductive layers 1 is arcuate.
Specifically, at least the upper surface of the fourth passivation layer 24 located between the adjacent conductive layers 1 is an arc surface, which may mean that the upper surface of the fourth passivation layer 24 located between the adjacent conductive layers 1 is an arc surface, or may mean that the upper surface of the fourth passivation layer 24 located between the adjacent conductive layers 1 and the upper surface of the fourth passivation layer 24 located above the conductive layers 1 are arc surfaces, that is, the surface of the fourth passivation layer 24 is a smooth surface, which has no sharp corners, so as to solve the problem of stress caused by the sharp corners.
It should be noted that the passivation layer stack 2 may further include a fifth passivation layer, a sixth passivation layer, a seventh passivation layer, and the like, that is, the number of passivation layers in the passivation layer stack 2 is not limited to the above-mentioned four passivation layers, and the number of passivation layers in the passivation layer stack 2 may be greater than four to meet the design requirement.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a device layer, wherein a plurality of conducting layers which are distributed at intervals are formed on the device layer;
forming a first passivation layer on the surface of the device layer and the surface of the conductive layer;
forming a second passivation material layer on the surface of the first passivation layer far away from the device layer and the conductive layer, wherein the second passivation material layer right above the conductive layer is provided with a first sharp angle;
forming a third passivation material layer on the surface, far away from the first passivation layer, of the second passivation material layer, wherein the third passivation material layer right above the conductive layer is provided with a second sharp angle, and the third passivation material layer between the adjacent conductive layers is provided with a third sharp angle;
rounding the first sharp angle, the second sharp angle and the third sharp angle to obtain a second passivation layer and a third passivation layer with smooth surfaces;
and forming a fourth passivation layer on the surface of the third passivation layer far away from the second passivation layer to obtain a passivation stack layer comprising the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer.
2. The method of manufacturing a semiconductor structure of claim 1, further comprising:
and forming a plastic sealing layer on the surface of the passivation lamination layer far away from the conductive layer.
3. The method of claim 1, wherein forming a second passivation material layer on a surface of the first passivation layer remote from the device layer and the conductive layer, comprises:
forming a second passivation material layer of the first layer on the surface of the first passivation layer;
and forming a second passivation material layer of the second layer on the surface of the second passivation material layer of the first layer.
4. The method of claim 1, wherein the first sharp corner, the second sharp corner, and the third sharp corner are rounded by an etching process.
5. The method of claim 1, wherein the second passivation material layer is formed using a high density plasma process; the second passivation material layer includes an oxide layer or a silicon nitride layer.
6. A semiconductor structure, comprising:
the device layer is provided with a plurality of conductive layers which are distributed at intervals;
the first passivation layer is positioned on the surface of the device layer and the surface of the conductive layer;
the second passivation layer is positioned on the surface, far away from the device layer and the conductive layer, of the first passivation layer, and the second passivation layer positioned right above the conductive layer is provided with a smooth surface;
the third passivation layer is positioned on the surface, far away from the first passivation layer, of the second passivation layer, the third passivation layer positioned right above the conductive layer is provided with a smooth surface, and the third passivation layer positioned between the adjacent conductive layers is provided with a smooth surface;
the fourth passivation layer is positioned on the surface of the third passivation layer far away from the second passivation layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the second passivation layer is obtained by rounding a first sharp angle of a second passivation material layer positioned in the positive direction of the conductive layer; wherein the second passivation material layer is formed on a surface of the first passivation layer away from the device layer and the conductive layer;
the third passivation layer is obtained by rounding a second sharp angle of a third passivation material layer above the conductive layer and a third sharp angle of a third passivation material layer between adjacent conductive layers; wherein the third passivation material layer is formed on the surface of the second passivation material layer away from the first passivation layer.
7. The semiconductor structure of claim 6, wherein the semiconductor structure further comprises:
and the plastic layer is positioned on the surface of the fourth passivation layer far away from the third passivation layer.
8. The semiconductor structure of claim 6, wherein the fourth passivation layer over the conductive layer is in contact with the second passivation layer.
9. The semiconductor structure of claim 6, wherein the first passivation layer has a thickness of 0.9 μm to 1.3 μm.
10. The semiconductor structure of claim 6, wherein the fourth passivation layer has a thickness of 0.5 μm to 0.9 μm.
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| JPH07130732A (en) * | 1993-11-01 | 1995-05-19 | Nec Corp | Semiconductor device and its manufacture |
| US6358862B1 (en) * | 1999-09-02 | 2002-03-19 | Micron Technology, Inc | Passivation integrity improvements |
| EP2183775A2 (en) * | 2007-07-26 | 2010-05-12 | Nxp B.V. | Reinforced structure for a stack of layers in a semiconductor component |
| US8563095B2 (en) * | 2010-03-15 | 2013-10-22 | Applied Materials, Inc. | Silicon nitride passivation layer for covering high aspect ratio features |
| EP2420826A1 (en) * | 2010-08-17 | 2012-02-22 | Nxp B.V. | Integrated Circuit and Manufacturing Method Therefor |
| CN105336712A (en) * | 2014-07-24 | 2016-02-17 | 北大方正集团有限公司 | Semiconductor chip and manufacturing method therefor |
| US20230021655A1 (en) * | 2021-07-22 | 2023-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
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