CN115497823A - IGBT device preparation method and IGBT device - Google Patents

IGBT device preparation method and IGBT device Download PDF

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CN115497823A
CN115497823A CN202211097945.0A CN202211097945A CN115497823A CN 115497823 A CN115497823 A CN 115497823A CN 202211097945 A CN202211097945 A CN 202211097945A CN 115497823 A CN115497823 A CN 115497823A
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wafer
groove
buffer
collector
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刘道国
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Shenzhen Still Core Technology Co ltd
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Shenzhen Still Core Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0761—Vertical bipolar transistor in combination with diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

The invention discloses a preparation method of an IGBT device and the IGBT device, which are used as a wafer of an n-drift region, wherein the lower end of the wafer is provided with a groove, the top end in the groove is provided with an n buffer region, two opposite inner walls of the groove are provided with an n + cathode region, and one surface of the n buffer region close to the opening of the groove is also provided with a P + collector region; the cellular structure is formed on the upper surface of the wafer; the emitter is positioned on the upper surface of the cellular structure and is connected with the groove type gate electrode arranged on the cellular structure; the collector is formed on the lower end surface of the wafer; the unit cell structure, the n-drift region, the n buffer layer and the n + cathode region form a freewheeling diode; under the disconnected blocking state, the blocking voltage is mainly maintained through the lightly doped n-drift region, so that the device does not need to be connected with an external diode, the size of the device is greatly reduced, and the required packaging cost is reduced.

Description

IGBT device preparation method and IGBT device
Technical Field
The invention belongs to the field of IGBT device preparation, and particularly relates to an IGBT device preparation method and an IGBT device.
Background
In the power electronics industry, an Insulated Gate BiPolar Transistor (IGBT) is a composite fully-controlled voltage-driven power Semiconductor device composed of a BiPolar Junction Transistor (BJT) and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and has the advantages of the BJT and the MOSFET, i.e., the characteristics of high input impedance and low on-state voltage drop, so that the IGBT has good switching characteristics, and is widely applied to the fields with the characteristics of high voltage and high current (such as alternating current motors, frequency converters, switching power supplies, lighting circuits, traction transmission, and the like);
however, in the conventional IGBT, unlike a body diode inside a MOSFET, the conventional IGBT has different forward and reverse withstand voltage parameters due to the fact that the conventional IGBT belongs to an asymmetric device and further has different elements, and in application, inductive loads are more, and further a diode needs to be connected in parallel and reversely beside a conventional IGBT chip, but this method can lead to the increase of the volume of the IGBT chip, and the diode and the IGBT are connected by using a lead wire, so that when the wiring is not firm, the situation of large-current burning of the chip easily occurs.
Disclosure of Invention
To having present IGBT among the above-mentioned technique all be inductive load in industrial application and mostly, all need be a diode in anti-parallel connection beside the IGBT chip, but this way can lead to IGBT chip volume increase, use lead connection between diode and the IGBT moreover, when wiring department is insecure, the problem that the chip heavy current burns out appears easily, this application provides a solution.
The invention provides a preparation method of an IGBT device, which comprises the following steps:
obtaining a wafer, and forming a plurality of cell structures with interlayer dielectrics on the front surface of the wafer;
depositing a first mask layer on the reverse side of the wafer, etching at least one groove, and forming an n-drift region on the wafer body with the groove;
forming an n buffer region and an n + cathode region on the inner side of the trench, wherein the n buffer region is positioned at the top end of the trench, the n + cathode region is positioned at two sides of the top end of the trench, and a P + collector region is further formed on one surface of the n buffer region, which is close to the opening of the trench;
removing the redundant mask layer of the n-drift region, and then forming a collector by metal precipitation;
and etching the interlayer dielectric covering the second mask layer, and depositing a metal material to form the emitter.
Preferably, the method further comprises: after the collector-emitter electrodes are formed, the cellular structures are irradiated by high-energy particles.
Preferably, the irradiation is carried out on a 2MeV linear electron accelerator, the electron energy being 400keV; the beam intensity is 1.67 multiplied by 10A cm2; the irradiation fluence is between 1X 106cm2 and 2X 106cm 2.
Preferably, the method further comprises: and annealing the irradiated device, wherein the annealing temperature is 300-700 ℃, and the heat preservation time is 0.5-3h.
Preferably, the device is subjected to preheating treatment before annealing treatment, wherein the preheating treatment temperature is 200-250 ℃ and the time is 20-30min.
Preferably, in forming the n buffer region and the n + cathode region inside the trench, the n buffer region is formed by diffusion first, and the n + cathode region is formed by tilt ion implantation and annealing.
Preferably, in forming the n buffer and the n + cathode region inside the trench, the n + cathode region is formed by diffusion, and the n + buffer is formed by diffusion after etching the top of the trench by the anisotropic etching.
There is also provided an IGBT device comprising:
the wafer is used as an n-drift region, a groove is formed in the lower end of the wafer, an n buffer region is formed at the top end in the groove, n + cathode regions are formed on two opposite inner walls of the groove, and a P + collector region is further formed on one surface, close to an opening of the groove, of the n buffer region;
the cell structure is formed on the upper surface of the wafer;
the emitter is positioned on the upper surface of the cellular structure and is connected with the groove type gate electrode arranged on the cellular structure;
and the collector is formed on the lower end surface of the wafer.
Preferably, the cellular structure comprises:
the bottom of the P-type substrate is connected with the upper end surface of the wafer;
a P-type doped region formed on the upper surface of the P-type substrate,
the n + emitting region is formed on the upper surface of the P-type doped region and is connected with the emitting electrode;
a gate dielectric forming a gate communication extending from the n + emitter region into the wafer, the gate electrode being located in the channel;
and an interlayer dielectric between the gate electrode and the emitter.
Preferably, the doping concentration of the P + collector region is 1 × 10 18 cm -3 To 1 × 10 21 cm -3 And a depth of between 0.1 μm and 1 μm.
The beneficial effects of the invention are: compared with the prior art, the preparation method of the IGBT device provided by the invention has the advantages that the IGBT device is prepared by the method; a groove is formed in the bottom of the wafer serving as the n-drift region, an n buffer region is formed at the top end in the groove, n + cathode regions are formed on two opposite inner walls of the groove, and a P + collector region is formed on one surface, close to the opening of the groove, of the n buffer region; the unit cell structure, the n-drift region, the n buffer layer and the n + cathode region form a fly-wheel diode; in operation, when the IGBT device bears the back voltage, the formed freewheeling diode is conducted, which is equivalent to the connection between the traditional IGBT and the diode; by the structural characteristic of forming the freewheeling diode, the blocking voltage is mainly maintained by the lightly doped n-drift region in the off-blocking state, so that the device does not need to be connected with an external diode, the size of the device is greatly reduced, and the required cost of packaging is reduced
Drawings
FIG. 1 is a schematic structural diagram of step 1 according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of step 2 according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of step 3 according to an embodiment of the present invention;
FIG. 4 is another schematic diagram of step 3 according to the present invention;
FIG. 5 is a schematic structural diagram of step 4 according to an embodiment of the present invention;
FIG. 6 is another schematic diagram of step 4 according to the present invention;
FIG. 7 is a schematic structural diagram of step 5 according to an embodiment of the present invention.
The main element symbols are as follows:
1. a cellular structure; 11. a P-type substrate; 12. a P-type doped region; 13. an n + emitter region; 14. An interlayer dielectric; 15. a gate dielectric; 16. a gate electrode; 2. a wafer; 21. a trench; 22. n buffer regions; 23. an n + cathode region; 24. a P + collector region; 25. an n-drift region; 3. A first mask layer; 4. a collector electrode; 5. and an emitter.
Detailed Description
In order to more clearly describe the present invention, the present invention will be further described with reference to the accompanying drawings.
In the following description, details of general examples are given to provide a more thorough understanding of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. It should be understood that the specific embodiments are illustrative of the invention and are not to be construed as limiting the invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
Aiming at the problems that the existing IGBT in the prior art has more inductive loads in industrial application and needs to be reversely connected with a diode in parallel beside an IGBT chip, but the volume of the IGBT chip is increased by the method, and the diode and the IGBT are connected by using a lead wire, so that the chip is easy to burn out by large current when the wiring position is not firm;
in order to solve the technical problems, the invention provides a preparation method of an IGBT device and the IGBT device, wherein the preparation method comprises the following steps:
step 1, referring to fig. 1, a wafer is obtained, and a plurality of cell structures with interlayer dielectrics are formed on the front surface of the wafer;
the wafer is used as a raw material for processing a semiconductor, the component of the wafer is monocrystalline silicon, for convenience of understanding, the wafer can be understood as a substrate structure, n-type doping is performed on the wafer so as to form an n-drift region 25 in a subsequent step, and the cell structure 1 is formed by a trench gate technology, which belongs to the prior art and is not described in detail;
step 2, referring to fig. 2, depositing a first mask layer 3 on the reverse side of the wafer 2, etching at least one trench 21, and forming an n-drift region 25 in the wafer body with the trench; specifically, a first mask layer 3 is deposited on the reverse side of a wafer 2, patterning is performed on the first mask layer 3, a groove 21 is etched under the action of the first mask layer 3, and the remaining part of the wafer 2 is subjected to n-type doping and then serves as an n-drift region 25;
step 3, referring to fig. 3 to 4, an n buffer region 22 and an n + cathode region 23 are formed inside the trench 21, the n buffer region 22 is located at the top of the trench 21, the n + cathode region 23 is located at two sides of the top of the trench 22, wherein a P + collector region 24 is further formed on one side of the n buffer region 22 close to the trench opening; the n buffer region 23 and the n + cathode region 24 may be formed simultaneously by a diffusion process, such as diffusing phosphorus into silicon at a temperature of 1000 ℃ to form the n buffer region 22 and the n + cathode region 23 on the inner wall of the trench; the P + collector region 24 is located at the lower end of the n buffer region 22, and the n + cathode region 23 is located at two sides of the trench 21, so that the n + cathode region 23 is not affected by consumption;
step 4, please refer to fig. 5 to 6, remove the excess first mask layer 3 of the n-drift region 25, and deposit metal to form a collector; specifically, the remaining first mask layer 3 is removed by wet etching, and a metal layer is deposited to form a collector 4; the metal can be deposited by sputtering, evaporation or electroplating; and after the collector 4 is molded, the collector is subjected to planarization, wherein the planarization is mechanical grinding or chemical mechanical polishing after the mechanical grinding, so that the collector 4 has a smooth surface, the packaging is facilitated, and the gap on the back of the device in the packaging process is further reduced.
Step 5, referring to fig. 7, the interlayer dielectric 14 is etched covering the second mask layer (not shown), and then a metal material is deposited to form an emitter 5; specifically, firstly, covering a second mask layer on the interlayer dielectric 14, then performing etching treatment on the interlayer dielectric 14, and then depositing a metal layer on the front surface of the cellular structure 1 to form the emitter 4;
in this embodiment, the preparation method further includes step 6, step 6: after forming the collecting and emitting electrode, irradiating the cellular structure by high-energy particles; the cellular structure 1 may specifically be a P-type substrate 11, a P-type doped region 12, and an n + emitter region 13, which are sequentially connected from bottom to top, and further has a gate dielectric 15, the gate dielectric 15 forms a gate link extending from the n + emitter region 13 to the n-drift region 25, and the gate electrode 16 is located in the channel; in the irradiation treatment, the high-energy particles are fast neutrons or electrons, the irradiated area is between the doped area and the emitter 5, and the performance of the element can be effectively improved through irradiation;
more specifically, in step 6, irradiation is performed on a 2MeV linear electron accelerator with an electron energy of 400keV; the beam intensity is 1.67 multiplied by 10A cm 2 (ii) a The irradiation fluence is 1X 10 6 cm 2 To 2X 10 6 cm 2 To (c) to (d); the irradiation fluence should be 1X 10 6 cm 2 To 2X 10 6 cm 2 Ensuring the irradiation uniformity of the irradiated surface of the sample during irradiation, otherwise causing the irradiation area to generate induced defects; when the irradiation fluence is less than 1X 10 6 cm 2 It is impossible to generate a pair of a hole and a self-interstitial atom in the crystal and to react with an impurity such as oxygen, nitrogen, phosphorus, etc. in the silicon single crystal to form a complex which compensates for the original doping of the silicon single crystal, and the vacancy-related complex also affects a thermal donor in the subsequent heat treatment of the silicon single crystal.
Preferably, the preparation method further comprises the step 7: annealing the irradiated device, wherein the annealing temperature is 300-700 ℃, and the heat preservation time is 0.5-3h; the annealing temperature stage can be divided into two stages, and at the beginning of the 450 ℃ stage, the irradiated silicon can generate a plurality of acceptor energy levels in forbidden bands; after the temperature is over 650 ℃, the four-vacancy type defect in the monocrystalline silicon disappears quickly, and the conductivity type begins to recover; the formation of thermal donors in irradiated single crystal silicon can be slowed or inhibited by the pre-heat treatment.
Further, the device is required to be preheated before annealing treatment, the preheating treatment temperature is 200-250 ℃, and the time is 20-30min; the formation of thermal donors in the irradiated monocrystalline silicon can be slowed down or inhibited through preheating treatment, and the inhibition effect on the thermal donors is enhanced along with the increase of the irradiation dose; furthermore, when annealing is carried out, the mixed gas of nitrogen, hydrogen and nitrogen and hydrogen is used as protective gas, so that the structure of the crystal can be better recovered, and defects can be eliminated; in practice, the annealing treatment may be performed by pulsed laser rapid annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, incoherent broadband light source (such as halogen lamp, arc lamp, graphite heating) rapid annealing, or any annealing method may be used.
As a modification of the embodiment of the present invention, in step 3, an n buffer region 22 is formed by diffusion, and then an n + cathode region 23 is formed by tilted ion implantation and annealing; if the N buffer 22 and the N + cathode 23 are formed simultaneously by diffusion, the doping concentration in the N buffer 22 may be increased, which is not favorable for implementing the field stop mechanism, therefore, in this embodiment, the N buffer 22 is formed by diffusion, and then the N + cathode 23 is formed by tilted ion implantation and annealing, in this case, the doping concentration of the N buffer 22 may be independent of the doping concentration of the N + cathode 23, and the N + cathode 23 may be far away from the top of the trench 21 by controlling the tilt angle, which will generate relatively high resistance at the PN junctions formed by the N + cathode 23, the P + collector 24 and the N buffer 22, and is more favorable for practical applications.
As another improvement of the embodiment of the present invention, in step 3, the n + cathode region 23 is formed by diffusion first, and at the top of the trench by anisotropic etching, the n + buffer region 22 is formed by diffusion; in the present embodiment, the doping concentration of the n buffer region 22 may be independent of the n + cathode region 23. Furthermore, by controlling the over-etching of silicon, the n + cathode region 23 can also be made far from the top of the trench, and thus the forward curve flyback effect of the device can be suppressed.
The present invention further provides an IGBT device, referring to fig. 7, including:
the wafer 2 is used as an n-drift region 26, the lower end of the wafer 2 is provided with at least one group of grooves 21, the top end of each group of grooves 21 is provided with an n buffer region 22, two opposite inner walls of the grooves 21 are provided with an n + cathode region 23, and one surface of the n buffer region 22 close to the groove opening is also provided with a P + collector region 24;
the structure comprises a cellular structure 1, wherein the cellular structure 1 is formed on the upper surface of a wafer 2;
the emitter 5 is positioned on the upper surface of the cellular structure 1, and is connected with the groove type gate electrode 16 arranged on the cellular structure 1;
and a collector 4, wherein the collector 4 is formed on the lower surface of the wafer 1.
Further, the cell structure 1 includes:
a P-type substrate 11, a P-type substrate bottom 12 and the upper surface of the wafer 1 are connected; the P-type doped region 11 and the P-type doped region 12 are formed on the upper surface of the P-type substrate 11; an n + emitting region 13 and an n + emitting region 13 are formed on the upper surface of the P-type doped region 2 and connected with the emitter 5; a gate dielectric 15, the gate dielectric 15 forming a gate communication extending from the n + emitter region 1 into the n-drift region, a gate electrode 16 being located in the gate channel; an interlayer dielectric 14, the interlayer dielectric 14 being located between the gate electrode 16 and the emitter 5.
Further, the doping concentration of the P + collector region 24 is 1 × 10 18 cm -3 To 1 × 10 21 cm -3 And a depth of between 0.1 μm and 1 μm.
The IGBT device of the present invention is explained in principle with reference to fig. 7:
in the IGBT device, there are a plurality of deep trenches 21 at the back surface, and in each trench 21, a P + collector region 24 is located at the top end of the inner wall of the trench 21, and integrated n + cathode regions 23 are located on the opposite two side inner walls; the trenches 1 enable the IGBT device to have a relatively thin device thickness while the wafer between the trenches remains thick for mechanical support;
furthermore, the P-type substrate 11, the N-drift region 26, the N + buffer layer 22 and the N + cathode region 23 in the cell structure form a freewheeling diode to achieve the same connection effect as the conventional IGBT and diode, and the present invention is further explained with respect to the working state of the IGBT device;
1. and (3) conducting state:
1.1, if the current density in the conducting state is smaller, the IGBT device can be used as a power MOSFET to operate, and the n + cathode region can be regarded as a drain region of the MOSFET;
1.2, if the current density in the conducting state is larger, at this time, a PN junction formed by the P + collector region 24 and the n buffer region 22 is biased in the positive direction, so that the device operates as an IBGT; in the IGBT mode, holes are injected from the P + collector region 24 into the n-drift region 25, thereby forming a relatively lower conduction loss compared to that in the power MOSFET mode, however, the hole injection efficiency of the PN junction formed by the backside P + collector region 24 and the n buffer region 22 should not be too high, otherwise the switching speed is significantly reduced, and therefore, it is preferable for the P + collector region 24 to be from 1 × 10 18 cm -3 To 1X 10 21 cm -3 And a depth of between 0.1 μm and 1 μm.
2. A blocking state:
when the IGBT device is in a blocking state, blocking voltage is mainly maintained through the lightly doped n-drift region 25; the doping concentration and the length of the n-drift region 25 depend on the nominal voltage of the device, since IGBT devices have a nominal voltage between 400V and 6000V, based on which the doping concentration of the n-drift region 25 is 1 × 10 12 cm -3 And 1X 10 15 cm -3 And the length of the n-drift region 25 is between 30 and 400 μm. Since the blocking voltage is mainly maintained by the depleted n-drift region 25, the length of the n-buffer region 22 can be much smaller than the length of the n-drift region. On the other hand, the doping concentration of the n-buffer region 22 should be higher than the doping concentration of the n-drift region 25, since the n-buffer region 22 should prevent the expansion of the depletion region in the blocking state.
3. Reverse conducting state:
the free-wheeling diode formed by the P-type substrate 11, the n-drift region 25, the n + cathode region 23 is forward biased and a reverse current can flow from the emitter 5 to the collector 4 to achieve a coupling effect equivalent to that of the conventional IGBT and diode of the prior art.
The invention has the advantages that:
compared with the traditional IGBT, the invention has the advantages that the P-type doped region, the N-drift region, the N + buffer layer and the N + cathode region in the cellular structure form a fly-wheel diode, and the blocking voltage is mainly maintained through the lightly doped N-drift region under the disconnection blocking state through the structural characteristics, so that the device does not need to be connected with an external diode, the volume of the device is greatly reduced, and the packaging cost is greatly reduced; furthermore, the IGBT device has low loss, good SOA (service oriented architecture) characteristics, positive temperature coefficient, good soft turn-off characteristics, short-circuit characteristics and good power cycle characteristics; the super junction structure formed in the preparation process can reduce the influence of current on a charge balance state, so that the IGBT device has better stability and reliability.
The above disclosure is only for a few specific embodiments of the present invention, but the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.

Claims (10)

1. A preparation method of an IGBT device is characterized by comprising the following steps:
obtaining a wafer, and forming a plurality of cell structures with interlayer dielectrics on the front surface of the wafer, wherein the interlayer dielectrics are positioned on one surface of the cell structures, which is far away from the wafer;
depositing a first mask layer on the reverse side of the wafer, etching at least one groove, and forming an n-drift region on the wafer body with the groove;
forming an n buffer region and an n + cathode region in the trench, wherein the n buffer region is positioned at the top end of the trench, the n + cathode region is positioned at two sides of the top end of the trench, and a P + collector region is further formed on one surface of the n buffer region, which is close to the opening of the trench;
removing the redundant first mask layer of the n-drift region, and depositing metal on the reverse side of the wafer to form a collector;
and etching the interlayer dielectric covering the second mask layer, and depositing a metal material to form an emitter.
2. The method for manufacturing the IGBT device according to claim 1, further comprising: after the collector-emitter electrodes are formed, the cell structures are irradiated by high-energy particles.
3. The method according to claim 2, wherein the irradiation is performed on a 2MeV linear electron accelerator with an electron energy of 400keV; the beam intensity is 1.67 multiplied by 10Acm2; the irradiation fluence is 1X 10 6 cm 2 -2×10 6 cm 2 In the meantime.
4. The preparation method of the IGBT device according to claim 2, characterized in that the method further comprises: and annealing the irradiated device, wherein the annealing temperature is 300-700 ℃, and the heat preservation time is 0.5-3h.
5. The method of claim 2, wherein the device is further subjected to a preheating treatment before the annealing treatment, wherein the preheating treatment is performed at a temperature of 200-250 ℃ for 20-30min.
6. The method of claim 1, wherein in the step of forming the N buffer region and the N + cathode region inside the trench, the N buffer region is formed by diffusion, and the N + cathode region is formed by tilted ion implantation and annealing.
7. The method of claim 1, wherein in the step of forming the n buffer and the n + cathode region inside the trench, the n + cathode region is formed by diffusion, the top of the trench is etched by anisotropic etching, and the n + buffer region is formed by diffusion.
8. An IGBT device, characterized by comprising:
the wafer is used as an n-drift region, a groove is formed in the lower surface of the wafer, an n buffer region is formed at the top end in the groove, n + cathode regions are formed on two opposite inner walls of the groove, and a P + collector region is further formed on one surface, close to an opening of the groove, of the n buffer region;
the cell structure is formed on the upper surface of the wafer;
the emitter is positioned on the upper surface of the cellular structure and is connected with the groove type gate electrode arranged on the cellular structure;
and the collector is formed on the lower surface of the wafer.
9. The IGBT device according to claim 8, wherein the cell structure comprises:
the bottom of the P-type substrate is connected with the upper surface of the wafer;
a P-type doped region formed on the upper surface of the P-type substrate,
the n + emitting region is formed on the upper surface of the P-type doped region and is connected with the emitting electrode;
a gate dielectric forming a gate communication extending from the n + emitter region into the wafer, the gate electrode being located in the channel;
an interlayer dielectric between the gate electrode and the emitter.
10. The IGBT device of claim 8, wherein the doping concentration of the P + collector region is 1 x 10 18 cm -3 To 1X 10 21 cm -3 And a depth of between 0.1 μm and 1 μm.
CN202211097945.0A 2022-09-08 2022-09-08 IGBT device preparation method and IGBT device Pending CN115497823A (en)

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