CN115497521B - Power supply circuit, memory and electronic equipment - Google Patents
Power supply circuit, memory and electronic equipment Download PDFInfo
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- CN115497521B CN115497521B CN202211389603.6A CN202211389603A CN115497521B CN 115497521 B CN115497521 B CN 115497521B CN 202211389603 A CN202211389603 A CN 202211389603A CN 115497521 B CN115497521 B CN 115497521B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
- Y04S20/20—End-user application control systems
Abstract
The present disclosure relates to the field of semiconductors, and the power consumption of current power supply circuits is high. The disclosed embodiment provides a power supply circuit, a memory and an electronic device, wherein the power supply circuit comprises: the standby power supply circuit is connected with the power supply network and is configured to provide a first voltage signal to the power supply network so that the voltage value of the power supply network is a first value; the active power supply circuit is configured to charge the power supply network under the condition that one storage block enters an active state from a standby state, so that the voltage value of the power supply network is not lower than a first value; and the bleeding circuit is configured to perform charge bleeding processing on the power supply network if the voltage value of the power supply network is greater than a second value during the period that the power supply circuit is activated to charge the power supply network, so that the voltage value of the power supply network is stabilized to a first value. The power supply circuit of the embodiment of the disclosure can reduce power consumption.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a power supply circuit, a memory, and an electronic device.
Background
The semiconductor memory includes a plurality of memory blocks and a power supply network that supplies power to the plurality of memory blocks. During operation of the semiconductor memory, the memory blocks in the active state consume more power than the memory blocks in the standby state. In order to avoid the instability of the power supply network, power supply modules with the same number as the storage blocks need to be arranged to supply power to the power supply network, and the power supply modules need to work all the time, so that the power consumption of the circuit is high.
Disclosure of Invention
The present disclosure provides a power supply circuit, a memory, and an electronic apparatus, which can reduce a circuit area and reduce circuit power consumption.
The technical scheme of the disclosure is realized as follows:
in a first aspect, an embodiment of the present disclosure provides a power supply circuit, where the power supply circuit is connected to a power supply network, and the power supply network supplies power to a plurality of storage blocks; wherein, power supply circuit includes:
the standby power supply circuit is connected with the power supply network and is configured to provide a first voltage signal to the power supply network so that the voltage value of the power supply network is a first value;
the activation power supply circuit is connected with the power supply network and is configured to charge the power supply network under the condition that one storage block enters an activation state from a standby state, so that the voltage value of the power supply network is not lower than a first value;
the bleeder circuit is connected with the power supply network and is configured to perform charge bleeder processing on the power supply network if the voltage value of the power supply network is greater than a second value during the period of activating the power supply circuit to charge the power supply network so as to stabilize the voltage value of the power supply network to a first value; wherein the second value is greater than the first value.
In some embodiments, the active power supply circuit includes a plurality of active power supply modules, each active power supply module is configured to supply power to a corresponding storage block through a corresponding power supply node, the power supply node is located on the power supply network, and the bleeder circuit includes a plurality of bleeder modules, each bleeder module is configured to perform charge bleeding processing through a corresponding power supply node;
the activated power supply circuit is configured to charge the activated storage block by using the corresponding activated power supply module and the corresponding power supply node, so that the voltage value of the power supply node of the storage block is not lower than a first value;
the bleeder circuit is configured to perform charge bleeder processing on the power supply node of the activated memory block by using the corresponding bleeder module so as to stabilize the voltage value of the power supply node of the memory block to a first value;
each active power supply module and each discharge module are connected with a power supply network.
In some embodiments, the number of the memory blocks is A, each memory block comprises B memory arrays, and a row decoder is arranged between the adjacent memory arrays;
the number of the activated power supply modules is (A multiplied by B), and the activated power supply modules correspond to the storage arrays one by one;
the number of the bleeder modules is (A multiplied by B)/n, and each bleeder module corresponds to n storage arrays; wherein A, B, n are all positive integers, and (a × B) is an integer multiple of n.
In some embodiments, B =2,n =4, 2 memory blocks per bleeding module, and all memory arrays in each memory block correspond to the same bleeding module.
In some embodiments, B =3,n =4, and each bleeding module corresponds to 2 memory blocks, and the same memory array corresponds to one bleeding module.
In some embodiments, the supply node of a memory block comprises the supply node of each memory array in the memory block;
the activated power supply module is directly connected with a power supply node of the corresponding storage array; the bleeding module is directly connected with the power supply node of the corresponding at least one storage array.
In some embodiments, the power supply circuit further comprises a reference circuit, the reference circuit being connected to the standby power supply circuit; wherein:
a reference circuit configured to generate a first reference signal;
the standby power supply circuit is specifically configured to receive a power switch signal and a first reference signal, and output a first voltage signal to a power network based on the first reference signal under the condition that the power switch signal is in an effective state, so as to control the voltage values of a plurality of power supply nodes to be first values;
the product of the voltage value of the first reference signal and a preset coefficient is a first value, the preset coefficient is larger than 1, and the product of the maximum voltage fluctuation value of the first reference signal and the preset coefficient is a second value; the voltage value of the first voltage signal is a first value.
In some embodiments, each active power supply module comprises a first active power supply unit and a second active power supply unit, both connected to the power supply network; wherein:
the first active power supply unit is configured to receive a first enable signal and a first reference signal, and output a second voltage signal to a directly connected power supply node based on the first reference signal when the first enable signal is in an effective state;
the second activation power supply unit is configured to receive a second enabling signal and the first power supply signal, and when the second enabling signal is in an effective state, a third voltage signal is output to a directly connected power supply node based on the first power supply signal; the voltage values of the second voltage signal and the third voltage signal are both first values;
under the condition that a storage block corresponding to the power supply module is activated to enter an activated state, the first enabling signal is in an effective state in all time periods of the activated state; the second enable signal is in an active state only for a target period of the active state, which is a period in which power consumption of the memory block is increased.
In some embodiments, the reference circuit is further connected to the bleeding module;
the reference circuit is also configured to generate a second reference signal, and the voltage value of the second reference signal is the maximum voltage fluctuation value of the first reference signal;
a bleeding module configured to receive a third enable signal and a second reference signal; under the condition that the third enabling signal is in an effective state, a fourth voltage signal is obtained from the connected power supply node, and if the voltage value of the fourth voltage signal is larger than the product of the voltage value of the second reference signal and a preset coefficient, charge discharge processing is performed on the connected power supply node;
and under the condition that the storage block corresponding to the bleeding module enters an activated state, the third enabling signal is in an effective state.
In some embodiments, the bleeding module comprises a comparison module and a bleeding branch, and both the comparison module and the bleeding branch are connected with the power supply network; wherein:
the comparison module is configured to receive a third enable signal, a fourth voltage signal and a second reference signal, and if the voltage value of the fourth voltage signal is greater than the product of the voltage value of the second reference signal and a preset coefficient under the condition that the third enable signal is in an effective state, the bleeding branch circuit is conducted; if the voltage value of the fourth voltage signal is smaller than the product of the voltage value of the second reference signal and a preset coefficient, the bleeder branch is turned off;
and the bleeder branch circuit is configured to receive the fourth voltage signal and conduct the fourth voltage signal to the ground under the condition of conduction.
In some embodiments, the comparison module comprises a first error amplifier, a bias resistor, a first switch tube, and the bleeding branch comprises a second switch tube;
the enabling end of the first error amplifier and the control end of the first switching tube both receive a third enabling signal; the power supply end of the first error amplifier and the first end of the first switching tube both receive a first power supply signal, and the second end of the first switching tube is connected with the first end of the bias resistor;
the negative phase input end of the first error amplifier receives a threshold voltage signal, the threshold voltage signal is generated by a second reference signal, and the voltage value of the threshold voltage signal is the product of the voltage value of the second reference signal and a preset coefficient;
the control end of the second switching tube is connected with the output end of the first error amplifier, and the second end of the second switching tube is connected with the ground signal end; the positive phase input end of the first error amplifier, the second end of the bias resistor and the first end of the second switching tube form a connection point, and the connection point is used for receiving a fourth voltage signal.
In some embodiments, the power supply circuit further comprises a regulating module, the regulating module being connected to the second active power supply unit;
a regulation module configured to receive a first reference signal and generate a first control signal based on the first reference signal;
a second active power supply unit further configured to receive a first control signal; and clamping the voltage value of the third voltage signal to be a first value by using the first control signal.
In some embodiments, the power supply circuit further comprises a control module connected to each active power module, each bleeding module;
and the control module is configured to receive the power switch signal and the activation indication signal of each storage block, and output a first enable signal of each activation power supply module, a second enable signal of each activation power supply module and a third enable signal of each bleeding module.
In a second aspect, the disclosed embodiments provide a memory, which includes the power supply circuit, the power supply network and a plurality of memory blocks as described in the first aspect;
the power supply circuit is connected with the power supply network and is configured to provide power to the power supply network so as to maintain the voltage value of the power supply network to be a first value;
a plurality of storage blocks connected to a power supply network and configured to obtain power from the power supply network; wherein the memory block has a standby state and an active state, and the power consumed by the memory block in the active state is higher than the power consumed by the memory block in the standby state.
In a third aspect, the disclosed embodiments provide an electronic device, which includes at least the memory according to the second aspect.
The embodiment of the disclosure provides a power supply circuit, a memory and an electronic device, wherein the power supply circuit comprises a standby power supply circuit, an active power supply circuit and a bleeder circuit, and the voltage of a power supply network is stabilized to a first value through the cooperation of the standby power supply circuit, the active power supply circuit and the bleeder circuit, so that the normal work of each memory block is ensured; meanwhile, in the embodiment of the disclosure, only the standby power supply circuit works continuously, and the activation power supply circuit and the discharge circuit only work at a specific time, so that the circuit power consumption is low, the circuit area is reduced, and the linearity of the power supply network is better.
Drawings
Fig. 1 is a schematic structural diagram of a power supply circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another power supply circuit provided in the embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another power supply circuit provided in the embodiment of the present disclosure;
fig. 4 is a schematic diagram of a partial structure of a power supply circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a current variation provided by an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a partial structure of a power supply circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a partial structure of a power supply circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating a partial structure of a power supply circuit according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram of a partial structure of a power supply circuit according to an embodiment of the present disclosure;
fig. 10 is a schematic view of an application scenario of a power supply circuit according to an embodiment of the present disclosure;
fig. 11 is a schematic diagram illustrating an operation process of a power supply circuit according to an embodiment of the disclosure;
fig. 12 is a schematic structural diagram of a memory according to an embodiment of the disclosure;
fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present embodiment are shown in the drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to be limiting of the disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
It should be noted that the terms "first \ second \ third" are used merely to distinguish similar objects and do not represent a specific ordering for the objects, and it should be understood that "first \ second \ third" may be interchanged with a specific order or sequence where permitted to enable the embodiments of the present disclosure described herein to be performed in an order other than that illustrated or described herein.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In an embodiment of the present disclosure, referring to fig. 1, a schematic structural diagram of a power supply circuit 10 provided in an embodiment of the present disclosure is shown. As shown in fig. 1, the power supply circuit 10 is connected to a power supply network 20, and the power supply network 20 supplies power to a plurality of memory blocks (e.g., memory block 1, memory block 2 … … memory block a); wherein, power supply circuit 10 includes:
the standby power supply circuit 11 is connected with the power supply network 20 and is configured to provide a first voltage signal to the power supply network 20 so that the voltage value of the power supply network 20 is a first value;
an active power supply circuit 12 connected to the power supply network 20 and configured to charge the power supply network 20 so that the voltage value of the power supply network 20 is not lower than a first value when a memory block enters an active state from a standby state;
the bleeding circuit 13 is connected to the power supply network 20, and configured to perform charge bleeding processing on the power supply network 20 to stabilize the voltage value of the power supply network 20 to a first value if the voltage value of the power supply network 20 is greater than a second value during the period when the power supply circuit 12 is activated to charge the power supply network 20; wherein the second value is greater than the first value.
It should be noted that the power supply circuit 10 of the embodiment of the present disclosure may be applied to a Memory, such as a Dynamic Random Access Memory (DRAM), and is specifically configured to supply power to the power network 20 in the Memory.
It is understood that the memory includes a large number of memory cells for storing data, which are divided into a plurality of memory blocks (banks) to be managed. Each storage block has a standby state and an activated state, and is in the standby state when the storage block is not selected as an operation object; when the memory block is selected as an operation object, the memory block enters an activated state.
The power supply network 20 needs to supply power to the memory blocks and the voltage value of the power supply network 20 needs to be kept stable. However, the memory blocks need to draw more power from the power supply network 20 in the active state than in the standby state, which may cause the voltage of the power supply network 20 to be unstable. In the embodiment of the present disclosure, the standby power supply circuit 11 is capable of providing part of the power for the power network 20, maintaining the power consumption of the memory block in the standby state; when a certain memory block is activated, the power supply circuit 12 is activated to charge the power supply network 20, so that the voltage value of the power supply network 20 is prevented from being reduced, and further, part of functional modules in the activated memory block cannot be started due to insufficient power supply voltage or other memory blocks in a standby state cannot work normally; at the same time, in order to avoid overcharging the power supply network 20, the bleeder circuit 13 may bleed off excess charge on the power supply network 20.
Thus, through the cooperation of the standby power supply circuit 11, the active power supply circuit 12 and the bleeder circuit 13, the voltage of the power supply network 20 is always maintained within an allowable fluctuation range centered on the first value, and the normal work of each storage block is ensured; meanwhile, in the embodiment of the present disclosure, only the standby power supply circuit 11 performs continuous operation, and the active power supply circuit 12 and the bleeding circuit 13 only need to operate at a specific time, so that energy consumption can be saved.
In some embodiments, as shown in fig. 2, the active power supply circuit 12 includes a plurality of active power supply modules (only 2 are shown in fig. 2, and more may be used in practical cases), each active power supply module is configured to supply power to a corresponding storage block through a corresponding power supply node, the power supply node is located on the power supply network 20, and the bleeding circuit 13 includes a plurality of bleeding modules (only 1 is shown in fig. 2, and more may be used in practical cases), each bleeding module is configured to perform charge bleeding processing through a corresponding power supply node. Each active power module, each bleeding module is connected to the power network 20.
It should be noted that, in fig. 2, 1 memory block corresponds to 1 active power supply module, and each 2 memory blocks corresponds to 1 bleeding module, but this does not constitute a relevant limitation. That is, each memory block has its corresponding active power supply module, for example, 1 memory block corresponds to several active power supply modules, or several memory blocks correspond to 1 active power supply module. Similarly, each memory block has its corresponding bleeding module, for example, 1 memory block corresponds to several bleeding modules, or several memory blocks correspond to 1 bleeding module.
Correspondingly, the active power supply circuit 12 is configured to charge the activated memory block with the corresponding active power supply module and power supply node, so that the voltage value of the power supply node of the memory block is not lower than the first value;
and the bleeding circuit 13 is configured to perform charge bleeding processing on the power supply node of the activated memory block by using the corresponding bleeding module, so that the voltage value of the power supply node of the memory block is stabilized to a first value.
It should also be noted that, in order to avoid noise interference, resistors and buffers (for increasing the signal voltage) may be respectively disposed at different positions of the power supply network 20, so as to ensure that the voltage values at different power supply nodes are the first value. Here, the specific number and distribution of resistors and buffers need to be determined according to actual scenarios.
In some embodiments, as shown in fig. 2, the number of the memory blocks is a, and each memory block includes B memory arrays, a Row Decoder (Row Decoder) is disposed between adjacent memory arrays, and fig. 2 temporarily does not show the Row Decoder. Here, the row decoder is configured to turn on a corresponding word line according to a row address signal to operate the memory cells on the word line.
The number of the activated power supply modules is (A multiplied by B), and the activated power supply modules correspond to the storage arrays one by one; the number of the bleeder modules is (A multiplied by B)/n, and each bleeder module corresponds to n storage arrays; wherein A, B, n are all positive integers, and (a × B) is an integer multiple of n.
Thus, each storage array can correspond to one activated power supply module, and the voltage value on the power supply network 20 can be better stabilized; a plurality of memory arrays may share the same bleeder module, which may reduce the device count and circuit area of the power supply circuit 10, and reduce circuit cost.
In a first specific embodiment, B =2,n =4, each bleeding module corresponds to 2 memory blocks, and all memory arrays in each memory block correspond to the same bleeding module.
In a second specific embodiment, B =3,n =4, each bleeding module corresponds to 2 memory blocks, and the same memory block may correspond to a plurality of bleeding modules, and the same memory array corresponds to one bleeding module, that is, all the memory arrays in each memory block may not correspond to the same bleeding module. That is, 1 bleeder module is shared by 3 storage arrays of the 1 st storage block and 1 storage array of the 2 nd storage block, 1 bleeder module is shared by the remaining 2 storage arrays of the 2 nd storage block and 2 storage arrays of the 3 rd storage block, and 1 bleeder module is shared by the remaining 1 storage array of the 3 rd storage block and 3 storage arrays of the 4 th storage block, so as to cycle.
In a third specific embodiment, B =4,n =4, and 4 memory arrays of each memory block correspond to the same 1 bleeding module; or, 3 storage arrays of the 1 st storage block and 1 storage array of the 2 nd storage block correspond to 1 bleeder module, and the remaining 3 storage arrays of the 2 nd storage block and 1 storage array of the 3 rd storage block correspond to 1 bleeder module, so as to circulate. Or, the 2 storage arrays of the 1 st storage block and the 2 storage arrays of the 2 nd storage block correspond to 1 bleeder module, so as to cycle.
Correspondingly, the power supply node of the storage block comprises a power supply node of each storage array in the storage block, and each active power supply module is used for supplying power to the corresponding storage array through the corresponding power supply node.
It should be further noted that the power supply network 20 is an integral current path, and all active power supply modules are directly or indirectly connected to all storage arrays, and all bleeding modules are directly or indirectly connected to all storage arrays. However, due to the effects of resistance and distance, activating the power/bleed off module has a greater impact on the power network 20 near its access point. Thus, in some embodiments, an active power module is disposed in proximity to a power supply node of its corresponding storage array, and the active power module is directly connected with the power supply node of the corresponding storage array; the bleeding module is arranged near the power supply node of the corresponding storage array, and the bleeding module is directly connected with the power supply node of the corresponding at least one storage array.
Here, the power supply node of the storage array is an overall concept, and all nodes in the power supply network 20 that may have significant influence on the power supply signal of the storage array may be regarded as the power supply node of the storage array.
In some embodiments, as shown in fig. 3, the power supply circuit 10 further includes a reference circuit 14, the reference circuit 14 being connected to the standby power supply circuit 11;
a reference circuit 14 configured to generate a first reference signal Vref;
the standby power supply circuit 11 is specifically configured to receive the power switch signal PwrOn and the first reference signal Vref, and output a first voltage signal VsaP to the power supply network 20 based on the first reference signal Vref when the power switch signal PwrOn is in an active state, so as to control voltage values of the plurality of power supply nodes to be a first value; the product of the voltage value of the first reference signal Vref and a preset coefficient is a first value, the preset coefficient is more than 1, and the product of the maximum voltage fluctuation value of the first reference signal Vref and the preset coefficient is a second value; the voltage value of the first voltage signal VsaP is a first value.
It should be noted that, as shown in fig. 3, the reference circuit 14 may include a bandgap reference module 141 and a voltage generation module 142, where the bandgap reference module 141 outputs an initial voltage signal Vbgr, and a voltage value of the initial voltage signal Vbgr is stable to 1.25 volts (V) and is not affected by temperature; the voltage generation module 142 generates a first reference signal Vref based on the initial voltage signal Vbgr, the voltage value of the first reference signal Vref may fluctuate due to the influence of the power voltage and the air pressure, and the product of the fluctuation maximum value and the preset coefficient is a second value.
The standby power supply circuit 11 may be implemented by a Low Dropout Regulator (LDO). For example, referring to fig. 4, the main devices of the low dropout regulator include a second error amplifier 301, a switching device (e.g., P-type fet), a first resistor 302 (with a resistance of R1) and a second resistor 303 (with a resistance of R2), where the predetermined coefficient is (R1 + R2)/R2. That is, the relationship between the first reference signal Vref and the first voltage signal VsaP is shown in equation (1).
In equation (1), vref is the voltage value of the first reference signal, and VsaP is the voltage value of the first voltage signal.
It should be understood that the power switch signal PwrOn serves as an enable signal for the second error amplifier 301 (not shown in fig. 4). In addition, fig. 4 only shows the main devices of the LDO for explanation, and the specific structure of the standby power supply circuit 11 may include more functional devices.
In some embodiments, as shown in fig. 3, each active power supply module comprises a first active power supply unit 121 and a second active power supply unit 122, each of the first active power supply unit 121 and the second active power supply unit 122 being connected to the power supply network 20;
a first active power supply unit 121 configured to receive a first enable signal (e.g., en0, enk in fig. 3) and a first reference signal Vref, and output a second voltage signal to a directly connected power supply node based on the first reference signal Vref when the first enable signal is in an active state;
a second active power supply unit 122 configured to receive a second enable signal (e.g., regen 0, regenk in fig. 3) and the first power supply signal VPwr, and output a third voltage signal to a directly connected power supply node based on the first power supply signal VPwr when the second enable signal is in an active state; the voltage values of the second voltage signal and the third voltage signal are both the first value. Here, k in Enk and regenk is the number, and k = a-1.
It should be noted that, when the memory block corresponding to the activated power supply module enters the activated state, the first enable signal is in the valid state in all time periods of the activated state; the second enable signal is in an active state only for a target period of time in the active state, which is a period of time in which the power consumption of the memory block is increased (gradually increased) or the like, which may cause a voltage drop in the power supply network 20.
Specifically, the memory block needs to be precharged, charge-shared, amplified with a small signal, etc. after entering the active state, and the power consumption is different in different stages. In the embodiment of the present disclosure, the active state may be divided into different time periods according to the situation that the storage block obtains power from the power supply network 20, for example, a target time period in which power consumption is continuously increased, and the power demand of the active state for a part of time may cause a voltage drop of the power supply network 20. Based on such a feature, in addition to the first active power supply unit 121 charging the power network 20 in the active state, the second active power supply unit 122 also charges the power network 20 for the target time period, avoiding the voltage of the power network 20 from being unstable.
For example, referring to fig. 5, a current (IsaP) condition between the memory block and the power network 20 is shown. As shown in fig. 5, the activation state may be divided into a first period (1), a second period (2), a third period (3), and a fourth period (4). The IsaP in the first time period (1) is the same as the IsaP in the standby state (the current value is a stable value and is not 0), that is, the memory block does not generate extra power consumption; in the second period (2) (i.e., the target period), isaP is gradually increased, i.e., the memory block generates additional power consumption, and the power consumption is gradually increased; in the third time period (3), isaP is gradually decreased, that is, the memory block generates extra power consumption, and the power consumption is gradually decreased; the IsaP in the fourth period (4) is the same as the IsaP in the standby state. In the embodiment of the present disclosure, the first active power supply unit 121 is turned on during the first time period to the fourth time period, but the second active power supply unit 122 is turned on only during the second time period, and is turned off during other time periods, so that power consumption in the second time period can be compensated better, and linearity of the power supply network 20 is better.
Illustratively, the first active power supply unit 121 may be implemented by an LDO. Referring to fig. 6, the first active power supply unit 121 includes a third error amplifier 311, a third resistor 312, a fourth resistor 313, a third switching tube 314, a fourth switching tube 315, and a capacitor 316; a negative phase input end of the third error amplifier 311 receives the first reference signal Vref, a positive phase input end of the third error amplifier 311 is connected to a first end of the third resistor 312 and a first end of the fourth resistor 313, an output end of the third error amplifier 311 is connected to a control end of the third switching tube 314, both a power supply end of the third error amplifier 311 and the first end of the third switching tube 314 receive the first power supply signal VPwr, a second end of the fourth resistor 313 is connected to a first end of the fourth switching tube 315, and a second end of the fourth switching tube 315 is grounded.
The enable terminal of the third error amplifier 311 and the control terminal of the fourth switching tube 315 both receive the first enable signal En. It should be understood that for the 1 st first active power supply unit 121, the first enable signal may be specifically En0; for the 2 nd first active power supply unit 121, the first enable signal may be embodied as En1, and so on.
A second terminal of the third switching tube 314 is connected to a second terminal of the third resistor 312 to form an output terminal of the first active power supply unit 121, and the output terminal is connected to the power supply node and is used for outputting the second voltage signal V2. Here, the third resistor 312 and the first resistor 302 have the same resistance value, which is R1; the fourth resistor 313 and the second resistor 303 have the same resistance and are both R2. Therefore, the voltage value of the second voltage signal V2 is as shown in equation (2):
in equation (2), vref is the voltage value of the first reference signal, and V2 is the voltage value of the second voltage signal.
In addition, the output terminal of the first active power supply unit 121 is also connected to ground through a capacitor 316 to reduce noise interference.
For example, referring to fig. 6, the second active power supply unit 122 includes a fifth switch tube 317 and a sixth switch tube 318. A first end of the fifth switching tube 317 receives the first power signal VPwr, a second end of the fifth switching tube 317 is connected to a first end of the sixth switching tube 318, and a second end of the sixth switching tube 318 is connected to the power supply node, and is configured to output a third voltage signal.
The control end of the fifth switch tube 317 receives the second enable signal RegEnN; it should be understood that for the 1 st second active power supply unit 122, the second enable signal may specifically be regen n0; for the 2 nd second active power supply unit 122, the second enable signal may be embodied as regen 1, and so on.
In addition, the control terminal of the sixth switching tube 318 receives the first control signal Vctrl. The source of the first control signal Vctrl is explained below. Referring to fig. 7, the power supply circuit 10 further includes a regulating module 15, and the regulating module 15 is connected to the second active power supply unit 122; a regulation module 15 configured to receive a first reference signal Vref and generate a first control signal Vctrl based on the first reference signal Vref; a second active power supply unit 122, further configured to receive a first control signal Vctrl; and clamping the voltage value of the third voltage signal to be a first value by using the first control signal Vctrl.
Specifically, as shown in fig. 7, the adjusting module 15 includes a power processing circuit, a fourth error amplifier 321, a fifth resistor 322, a sixth resistor 323, a seventh switch tube 324, and an eighth switch tube 325. The non-inverting input terminal of the fourth error amplifier 321 and the input terminal of the power processing circuit both receive the first reference signal Vref, the power processing circuit outputs the power processing signal Vhv, and the power processing signal Vhv is used as a power signal of the fourth error amplifier 321, the control terminal of the seventh switch tube 324 receives a ground signal (i.e., the seventh switch tube 324 is normally open), the first terminal of the seventh switch tube 324 receives the first power signal VPwr, the second terminal of the seventh switch tube 324 is connected to the first terminal of the eighth switch tube 325, the second terminal of the eighth switch tube 325 is connected to the second terminal of the fifth resistor 322, and the second terminal of the sixth resistor 323 is connected to ground.
An output end of the fourth error amplifier 321 is connected to a control end of the eighth switch 325 and then used for outputting the first control signal Vctrl, and a negative phase input end of the fourth error amplifier 321 and a first end of the fifth resistor 322 are connected to a first end of the sixth resistor 323. The fifth resistor 322 and the first resistor 302 have the same resistance value, and are both R1; the sixth resistor 323 and the second resistor 303 have the same resistance and are both R2. At this time, the voltage value of the second terminal of the eighth switching tube 325 is as shown in formula (3):
in equation (3), voutR refers to a voltage value of the second terminal of the eighth switch 325, and Vref refers to a voltage value of the first reference signal.
On the basis, the voltage value of the first control signal is shown as formula (4):
in the formula (4), the reaction mixture is,
refers to the voltage value of the first control signal, vref refers to the voltage value of the first reference signal,
refers to the threshold voltage of the eighth switching tube 325.
Referring to fig. 6, the threshold voltage of the sixth switch tube 318 is also
Therefore, during the operation of the second active power supply unit 122, due to the clamping effect of the first control signal Vctrl, the voltage value of the third voltage signal output by the second active power supply unit 122 is equal to
I.e. the first value.
In addition, the voltage value of the power supply processing signal Vhv is at least larger than the first control signal
Voltage value and threshold voltage of
And (3) is (a).
In this way, the second active power supply unit 122 has a simple structure and a faster start-up speed, thereby compensating for a fast power draw during the activation of the memory block.
In some embodiments, referring to fig. 3, the reference circuit 14 is further connected to the bleeding module;
a reference circuit 14, further configured to generate a second reference signal VrefH, and a voltage value of the second reference signal VrefH is a maximum fluctuation value of the first reference signal Vref, that is, a product of the second reference signal VrefH and a preset coefficient is the aforementioned second value;
a bleeding module configured to receive a third enable signal EnNpdn and a second reference signal VrefH; and under the condition that the third enable signal EnNpdn is in an effective state, acquiring a fourth voltage signal from the connected power supply node, and if the voltage value of the fourth voltage signal is greater than the product of the voltage value of the second reference signal VrefH and a preset coefficient, executing charge draining processing on the connected power supply node; and under the condition that the storage block corresponding to the bleeding module enters an activated state, the third enable signal EnNpdn is in an effective state.
In some embodiments, as shown in fig. 8, the bleeding module includes a comparison module 131 and a bleeding branch 132, and both the comparison module 131 and the bleeding branch 132 are connected to the power supply network 20;
a comparing module 131 configured to receive the third enable signal EnNpdn, the fourth voltage signal Vout1 (obtained from the power supply node), and the second reference signal VrefH, and when the third enable signal EnNpdn is in an active state, if a voltage value of the fourth voltage signal Vout1 is greater than a product of a voltage value of the second reference signal VrefH and a preset coefficient, turn on the bleeding branch 132; if the voltage value of the fourth voltage signal Vout1 is smaller than the product of the voltage value of the second reference signal VrefH and the preset coefficient, the bleeding branch 132 is turned off;
the bleeding branch 132 is configured to receive the fourth voltage signal Vout1 and conduct the fourth voltage signal Vout1 to ground when conducting.
It should be noted that the bleeder module further includes a clamp module (not shown in fig. 8), and the clamp module receives the second reference signal VrefH and outputs a threshold voltage signal. Here, the voltage value of the threshold voltage signal is a product of a voltage value of the second reference signal VrefH and a preset coefficient, which is a voltage reference of the comparison module 131.
Thus, if the voltage value of the supply node is greater than the second value (i.e., the product of the voltage value of the second reference signal VrefH and the preset coefficient), indicating that the power supply network 20 is overcharged, the bleed branch 132 conducts to place the supply node in communication with ground, conducting excess charge to ground until the voltage value of the supply node is equal to or less than the second value.
In some embodiments, as shown in fig. 8, the comparing module 131 includes at least a first error amplifier 331, a bias resistor 332, a first switching tube 333, and the bleeding branch 132 includes a second switching tube 334;
the enable terminal of the first error amplifier 331 and the control terminal of the first switch tube 333 both receive the third enable signal EnNpdn; the power source terminal of the first error amplifier 331 and the first terminal of the first switching tube 333 both receive the first power signal VPwr, and the second terminal of the first switching tube 333 is connected to the first terminal of the bias resistor 332;
the negative phase input terminal of the first error amplifier 331 receives a threshold voltage signal, the threshold voltage signal is generated by the second reference signal VrefH, and the voltage value of the threshold voltage signal is the product of the voltage value of the second reference signal VrefH and a preset coefficient;
the control end of the second switching tube 334 is connected to the output end of the first error amplifier 331, and the second end of the second switching tube 334 is connected to the ground signal end; the non-inverting input terminal of the first error amplifier 331, the second terminal of the bias resistor 332, and the first terminal of the second switching transistor 334 form a connection point, which is connected to a corresponding power supply node and receives the fourth voltage signal Vout1.
In this way, under the condition that the third enable signal EnNpdn is asserted, the first error amplifier 331 and the first switch tube 333 enter an operating state, if the voltage value of the fourth voltage signal Vout1 is greater than the threshold voltage signal, the first error amplifier 331 outputs a high level signal, the second switch tube 334 is turned on, and the power supply node is connected to the ground to discharge the charge until the voltage value of the power supply node is less than or equal to the threshold voltage signal.
In the above description, the first switch tube 333, the third switch tube 314, the fifth switch tube 317, and the seventh switch tube 324 are P-type field effect transistors, and the second switch tube 334, the fourth switch tube 315, the sixth switch tube 318, and the eighth switch tube 325 are N-type field effect transistors.
In some embodiments, as shown in fig. 9, the power supply circuit 10 further includes a control module 16, the control module 16 being connected to each active power module, each bleeding module;
the control module 16 is configured to receive the power switch signal PwrOn, the activation indication signal (e.g., bank _0En, bank _ kEn in fig. 9) of each memory block, and output the first enable signal (e.g., en0, enk in fig. 9) of each active power module, the second enable signal (e.g., regen 0, regenk in fig. 9) of each active power module, and the third enable signal (e.g., endn in fig. 9) of each bleeder module.
In particular, the third enable signals of different bleeding modules are different, i.e. the third enable signal of the 1 st bleeding module may be specifically denoted as EnNPd0, the third enable signal of the 2 nd bleeding module may be specifically denoted as EnNPd1, and so on.
In this way, under the condition that the power switch signal PwrOn is valid, if the memory block 1 needs to be adjusted from the standby state to the active state, the active indication signal Bank _0En of the memory block 1 is in the active state, and the remaining active indication signals are all in the inactive state, so that the specified first enable signal, second enable signal and third enable signal are in the active state, so as to enable the active power supply module corresponding to the memory block 1 and the bleeding module corresponding to the memory block 1 to enter the working state.
To sum up, the embodiment of the present disclosure provides a power supply circuit 10, which at least includes the following: (1) Generating a first reference signal Vref and a second reference signal VrefH by a bandgap reference module 141 and a voltage generation module 142; (2) The adjusting module 15 generates a first control signal Vctrl, and the first control signal Vctrl clamps the voltage value of the third voltage signal to a first value through an N-type field effect transistor (i.e., a sixth switching transistor 318) in the second active power supply unit 122; (3) The standby power supply circuit 11 maintains the working voltage of each memory block in the standby state, and the voltage value of the working voltage is a first value; (4) The first active power supply unit 121 and the second active power supply unit 122 supply active operating currents of the memory blocks in an active state; (5) The bleeding module bleeds redundant charges on the power supply node so as to maintain the voltage value of the power supply node to be accurate enough; (6) The control module 16 is configured to provide respective enable signals of the first active power supply unit 121, the second active power supply unit 122, and the bleeding module.
In particular, the first active power supply unit 121 employs an LDO architecture as shown in fig. 6, and is capable of providing a large driving current according to the state of the memory block; the bleeding module is composed of an error amplifier, a bleeding transistor (i.e. the second switch tube 334 in fig. 8), and a bias resistor, and when the power supply node is overcharged, a charge bleeding path to the ground is provided through the bleeding transistor, so as to prevent the power supply node from being overcharged, and quickly reach the target potential.
For example, please refer to fig. 10, which shows an application scenario diagram of a power supply circuit 10 according to an embodiment of the present disclosure. In fig. 10, a white triangle represents a first active power supply unit, a rectangle filled with vertical lines represents a second active power supply unit, a white cylinder represents a bleeding module, a pentagon filled with vertical lines represents a reference circuit and a regulating module, and a triangle filled with vertical lines represents a standby charging circuit.
As shown in FIG. 10, the memory comprises at least 4 memory blocks (Bank 0~ Bank 3) and corresponding peripheral circuits (including analog circuits, input/output circuits, command/address circuits, etc.), each memory block comprises 2 memory arrays (memory array U and memory array V), and a row decoder is arranged between the 2 memory arrays of each memory block. The memory is provided with 1 reference circuit, 1 standby charging circuit and 1 adjusting module, wherein the reference circuit, the standby charging circuit and the adjusting module are arranged near the analog circuit, and only one set of memory is arranged; in addition, each storage array is provided with 1 first activated power supply unit and 1 second activated power supply unit, and the first activated power supply unit/the second activated power supply unit are respectively arranged along with the corresponding storage array; every 2 storage blocks correspond to 1 bleeder module, and the bleeder module is placed between its corresponding 2 storage blocks.
It should be understood that the above is only an example and is not limiting. For example, each memory block may be provided with a bleeding module; alternatively, each memory block may also include 3 memory arrays, with each 4 memory arrays sharing a bleeder module.
Referring to fig. 11, a schematic diagram of an operation process of the power supply circuit provided in the embodiment of the disclosure is shown. In fig. 11, except for the power switch signal PwrOn, the remaining parts respectively show the change of the activated Bank and its related modules (including the first active power supply unit, the second active power supply unit, the bleeding module, and the power supply node) when different memory blocks (Bank 0/1/2/3) are activated, and Bank0/1/2/3 \ u vsap represents the voltage value of the power supply node corresponding to Bank 0/1/2/3.
To explain in detail by taking Bank0 as an example, and referring to fig. 3 and 11, after the power switching signal PwrOn is adjusted to the high state, the power supply circuit 10 enters the operating state, and first, the standby power supply circuit 11 charges the power supply network 20 to the first value, that is, bank0/1/2/3 \ u vsap is rapidly increased to the first value. Next, when the word line in Bank0 is turned on (i.e., bank0_ WL in fig. 11 is high), bank0 enters an active state, and both the corresponding first active power supply unit and the bleeding block enter an active state (i.e., bank0_ first active power supply unit and Bank0_ bleeding block in fig. 11 are high). As can be seen from FIG. 5, in the first phase of the active state, bank0_ IsaP is a stable value, and no additional current consumption is generated; in the second stage of the active state, bank0_ IsaP gradually increases, bank0 needs to get a large amount of power from the power supply network 20, at this time, the second active power supply unit 122 enters the working state (regen 0 in fig. 11 is low, which is an active low signal), since the first active power supply unit 121 and the second active power supply unit 122 charge the power supply network 20 at the same time, bank0_ VsaP increases from the first value to the second value, at this time, the bleeding module starts to bleed off the charge, so Bank0_ VsaP starts to gradually decrease; in the third stage, isaP is gradually decreased, the speed of taking power from the power network 20 by Bank0 is gradually decreased, at this time, the second active power supply unit 122 stops working, and Bank0_ VsaP starts to decrease as Bank0 still takes power from the power network; in the fourth phase, isaP returns to the stable value, and the first active power supply unit 121 is still operating, continuously keeping IsaP stable.
As can be seen from the above, the embodiment of the present disclosure provides a power supply circuit, and a standby power supply circuit, an active power supply circuit, and a bleeding circuit are mutually matched, so that a voltage value of a power supply network is stabilized to a first value, the power supply network can be more efficiently supplied with power, each power supply node in the power supply network responds quickly, and the voltage value of the power supply network has good linearity; in addition, the power supply module which is independent and always in a working state is not required to be arranged for each storage block, so that the overall power consumption is lower, the circuit layout area is reduced, the circuit design is more friendly, and the number of LDOs is reduced.
In another embodiment of the present disclosure, please refer to fig. 12, which illustrates a schematic structural diagram of a memory 40 provided in an embodiment of the present disclosure. As shown in fig. 12, the memory 40 includes the power supply circuit 10, the power supply network 20, and a plurality of memory blocks as described previously;
a power supply circuit 10 connected to the power supply network 20 and configured to supply power to the power supply network 20 to maintain a voltage value of the power supply network 20 at a first value;
a plurality of storage blocks connected to the power supply network 20 and configured to obtain power from the power supply network 20; wherein the memory block has a standby state and an active state, and the power consumed by the memory block in the active state is higher than the power consumed by the memory block in the standby state.
In another embodiment of the present disclosure, please refer to fig. 13, which illustrates a schematic structural diagram of an electronic device 50 according to an embodiment of the present disclosure. As shown in fig. 13, the electronic device 50 includes the memory 40 as previously described.
The above description is only for the preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. It should be noted that, in the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments. Features disclosed in several of the product embodiments provided in this disclosure may be combined in any combination to yield new product embodiments without conflict. The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present disclosure, and shall cover the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (15)
1. A power supply circuit is characterized in that the power supply circuit is connected with a power supply network, and the power supply network supplies power to a plurality of storage blocks; wherein the power supply circuit comprises:
the standby power supply circuit is connected with the power supply network and is configured to provide a first voltage signal to the power supply network so that the voltage value of the power supply network is a first value;
the activation power supply circuit is connected with the power supply network and is configured to charge the power supply network under the condition that one storage block enters an activation state from a standby state, so that the voltage value of the power supply network is not lower than the first value;
the bleeding circuit is connected with the power supply network and is configured to perform charge bleeding processing on the power supply network if the voltage value of the power supply network is greater than a second value during the period that the power supply network is charged by the active power supply circuit, so that the voltage value of the power supply network is stabilized to be the first value; wherein the second value is greater than the first value.
2. The power supply circuit of claim 1, wherein the active power supply circuit comprises a plurality of active power supply modules, each active power supply module is configured to supply power to a corresponding storage block through a corresponding power supply node, the power supply node is located on the power supply network, and the bleeding circuit comprises a plurality of bleeding modules, each bleeding module is configured to perform charge bleeding processing through a corresponding power supply node;
the activated power supply circuit is configured to charge the activated memory block by using the corresponding activated power supply module and the corresponding power supply node, so that the voltage value of the power supply node of the memory block is not lower than the first value;
the bleeding circuit is configured to perform charge bleeding processing on the power supply node of the activated memory block by using the corresponding bleeding module, so that the voltage value of the power supply node of the memory block is stabilized to the first value;
wherein each of the active power supply module and the bleeding module is connected to the power network.
3. The power supply circuit according to claim 2, wherein the number of the memory blocks is a, each memory block comprises B memory arrays, and a row decoder is arranged between adjacent memory arrays;
the number of the activated power supply modules is (A multiplied by B), and the activated power supply modules correspond to the storage arrays one by one;
the number of the bleeder modules is (A multiplied by B)/n, and each bleeder module corresponds to n storage arrays; wherein A, B, n are all positive integers, and (a × B) is an integer multiple of n.
4. The power supply circuit of claim 3, wherein B =2,n =4, wherein each of the bleeding modules corresponds to 2 of the memory blocks, and wherein all of the memory arrays in each of the memory blocks correspond to the same bleeding module.
5. The power supply circuit of claim 3, wherein B =3,n =4, and each of the bleeder modules corresponds to 2 memory blocks, and the same memory array corresponds to one bleeder module.
6. The power supply circuit according to any one of claims 3 to 5, wherein the power supply node of the memory block comprises a power supply node of each memory array in the memory block;
the activated power supply module is directly connected with a corresponding power supply node of the storage array; the bleeding module is directly connected with a power supply node of the corresponding at least one storage array.
7. The power supply circuit of claim 6, further comprising a reference circuit, the reference circuit being connected to the standby power supply circuit; wherein:
the reference circuit configured to generate a first reference signal;
the standby power supply circuit is specifically configured to receive a power switch signal and the first reference signal, and output the first voltage signal to the power network based on the first reference signal when the power switch signal is in an active state, so as to control voltage values of the plurality of power supply nodes to be a first value;
the product of the voltage value of the first reference signal and a preset coefficient is the first value, the preset coefficient is greater than 1, and the product of the maximum voltage fluctuation value of the first reference signal and the preset coefficient is the second value; the voltage value of the first voltage signal is the first value.
8. The power supply circuit of claim 7, wherein each of the active power supply modules comprises a first active power supply unit and a second active power supply unit, the first active power supply unit and the second active power supply unit being connected to the power supply network; wherein:
the first active power supply unit is configured to receive a first enable signal and the first reference signal, and output a second voltage signal to the directly connected power supply node based on the first reference signal when the first enable signal is in an active state;
the second active power supply unit is configured to receive a second enable signal and a first power supply signal, and output a third voltage signal to the directly connected power supply node based on the first power supply signal when the second enable signal is in an active state; the voltage values of the second voltage signal and the third voltage signal are both the first value;
under the condition that the storage block corresponding to the activated power supply module enters an activated state, the first enabling signal is in an effective state in all time periods of the activated state; the second enable signal is in an active state only for a target period of time of the active state, the target period of time being a period of time during which power consumption of the memory block is increased.
9. The power supply circuit of claim 8, wherein the reference circuit is further coupled to the bleeding module;
the reference circuit is further configured to generate a second reference signal, and the voltage value of the second reference signal is the maximum voltage fluctuation value of the first reference signal;
the bleeding module is configured to receive a third enable signal and the second reference signal; under the condition that the third enabling signal is in an effective state, a fourth voltage signal is obtained from the connected power supply node, and if the voltage value of the fourth voltage signal is larger than the product of the voltage value of the second reference signal and the preset coefficient, charge discharge processing is performed on the connected power supply node;
and when the memory block corresponding to the bleeding module enters an activated state, the third enabling signal is in an effective state.
10. The power supply circuit of claim 9, wherein the bleeding module comprises a comparison module and a bleeding branch, and the comparison module and the bleeding branch are both connected to the power supply network; wherein:
the comparison module is configured to receive the third enable signal, the fourth voltage signal and the second reference signal, and if the voltage value of the fourth voltage signal is greater than a product of the voltage value of the second reference signal and a preset coefficient, the bleeding branch is turned on when the third enable signal is in an active state; if the voltage value of the fourth voltage signal is smaller than the product of the voltage value of the second reference signal and a preset coefficient, the bleeding branch is turned off;
the bleeding branch is configured to receive the fourth voltage signal and conduct the fourth voltage signal to ground when conducting.
11. The power supply circuit according to claim 10, wherein the comparing module comprises a first error amplifier, a bias resistor, a first switching tube, and the bleeding branch comprises a second switching tube;
the enabling end of the first error amplifier and the control end of the first switching tube both receive the third enabling signal; a power end of the first error amplifier and a first end of the first switching tube both receive a first power signal, and a second end of the first switching tube is connected with a first end of the bias resistor;
the negative phase input end of the first error amplifier receives a threshold voltage signal, the threshold voltage signal is generated by the second reference signal, and the voltage value of the threshold voltage signal is the product of the voltage value of the second reference signal and a preset coefficient;
the control end of the second switching tube is connected with the output end of the first error amplifier, and the second end of the second switching tube is connected with a ground signal end; and the positive phase input end of the first error amplifier, the second end of the bias resistor and the first end of the second switch tube form a connection point, and the connection point is used for receiving the fourth voltage signal.
12. The power supply circuit of claim 9, further comprising a regulation module coupled to the second active power supply unit;
the adjusting module is configured to receive the first reference signal and generate a first control signal based on the first reference signal;
the second active power supply unit further configured to receive the first control signal; and clamping the voltage value of the third voltage signal to the first value by using the first control signal.
13. The power supply circuit of claim 9, further comprising a control module coupled to each of the active power modules, each of the bleeding modules;
the control module is configured to receive the power switch signal and an activation indication signal of each memory block, and output the first enable signal of each active power supply module, the second enable signal of each active power supply module, and the third enable signal of each bleeding module.
14. A memory, characterized in that the memory comprises a power supply circuit according to any one of claims 1-13, a power supply network and a plurality of memory blocks;
the power supply circuit is connected with the power supply network and is configured to provide power to the power supply network so as to maintain the voltage value of the power supply network to be a first value;
a plurality of the storage blocks connected to the power supply network and configured to obtain power from the power supply network; wherein the memory block has a standby state and an active state, and the power consumed by the memory block in the active state is higher than the power consumed by the memory block in the standby state.
15. An electronic device, characterized in that the electronic device comprises the memory of claim 14.
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| CN107219427A (en) * | 2017-06-27 | 2017-09-29 | 天津市滨海新区军民融合创新研究院 | Power supply circuit and electromagnetic compatibility test system |
| CN111796199A (en) * | 2020-07-30 | 2020-10-20 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
| CN215498356U (en) * | 2021-08-18 | 2022-01-11 | 北京车和家信息技术有限公司 | Low-voltage power supply network protection circuit and vehicle |
| CN114365139A (en) * | 2021-12-08 | 2022-04-15 | 长江存储科技有限责任公司 | System and method for modeling and simulating on-die capacitors |
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