CN115496021A - Automatic testing method, device, chip, equipment and system for system chip - Google Patents
Automatic testing method, device, chip, equipment and system for system chip Download PDFInfo
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Abstract
The application discloses an automatic testing method, device, chip, equipment and system of a system chip, and belongs to the technical field of chips. The method comprises the following steps: configuring a test unit in a system chip; receiving test contents sent by an automatic test machine; calling a testing unit configured in the system chip according to the testing content, and testing the system chip according to the testing unit; and generating a fingerprint according to the test result obtained after the test, sending the fingerprint to an automatic test machine, wherein the automatic test machine is used for comparing the fingerprint with the standard fingerprint and determining the test result of the system chip according to the comparison result. According to the method and the device, the test unit configured by the device can be called according to the test content to complete the test, so that the data transmission in the test process is reduced, the test speed is improved, and the fingerprint of the test result can be fed back to reduce the data transmission and improve the safety of a system chip.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to an automatic testing method, device, chip, equipment and system of a system chip.
Background
The traditional System On Chip (SOC) test highly depends on the Design For Testability (DFT), which can provide the test excitation with high fault coverage rate, and ensure that the semiconductor test can screen out the faulty System Chip with the minimum time cost. However, as the complexity of software and hardware in a system chip increases, many problems cannot or are difficult to abstract a corresponding fault model, and this part of tests is generally performed by using Automatic Test Equipment (ATE).
Currently, when an automatic test machine tests a system chip, a test program is generally downloaded into the system chip through a diskless boot ROM interface (boot ROM) or a bypass interface, and the system chip returns a test result after running the test program, or directly accesses the inside of the system chip through a bypass interface. However, the testing speed of the two testing methods is relatively slow, and the safety of the system chip is hidden.
Disclosure of Invention
The embodiment of the application provides an automatic testing method, device, chip, equipment and system of a system chip, which are used for solving the problems that when the system chip is tested by downloading a testing program, the testing speed is low, and the safety of the system chip has hidden danger. The technical scheme is as follows:
in one aspect, a method for automatically testing a system chip is provided, the method comprising:
configuring a test unit in a system chip;
receiving test contents sent by the automatic test machine;
calling a test unit configured in the system chip according to the test content, and testing the system chip according to the test unit;
and generating a fingerprint according to a test result obtained after the test, sending the fingerprint to the automatic test machine, wherein the automatic test machine is used for comparing the fingerprint with a standard fingerprint and determining the test result of the system chip according to the comparison result.
In a possible implementation manner, the invoking a test unit configured in the system chip according to the test content and testing the system chip according to the test unit include:
when the test content comprises the pointer and the test parameters of a single test unit, calling the test unit configured in the system chip according to the pointer, and testing the system chip according to the test unit and the test parameters.
In a possible implementation manner, the invoking a test unit configured in the system chip according to the test content and testing the system chip according to the test unit include:
when the test content comprises calling information and test parameters of a plurality of test units, sequentially calling the test units configured in the system chip according to the calling information, and testing the system chip according to the test units and the test parameters.
In a possible implementation manner, before the receiving the test content sent by the automatic test machine, the method further includes:
sending a random number to the automatic test machine;
receiving a first message authentication code sent by the automatic test machine, wherein the first message authentication code is generated after the automatic test machine calculates a message authentication code for the received random number by using an agreed password;
calculating a message authentication code for the random number by using the agreed password to obtain a second message authentication code;
and when the first message authentication code is the same as the second message authentication code, determining that the authentication is successful, and triggering and executing the step of receiving the test content sent by the automatic test machine.
In one possible implementation, the method further includes:
determining that authentication fails when the first message authentication code is different from the second message authentication code;
and when the times of authentication failure exceed a preset time threshold, programming a one-time programmable (OTP) flag bit, wherein the OTP flag bit indicates that the system chip does not perform automatic testing any more.
In a possible implementation manner, when a plurality of test units are configured in the system chip, the plurality of test units correspond to at least two levels, and the test units of different levels can be called each other.
In one possible implementation, when the plurality of test units correspond to three levels, a first level of test units is used for calling basic function functions in the system chip, and a second level of test units is used for calling the first level of test units to test intermediate function functions in the system chip; a third level of test units is to invoke the second level of test units and/or the first level of test units to test high level functional functions in the system chip.
In a possible implementation manner, when the system on a chip includes multiple processors and multiple functional DUTs to be tested, the receiving test content sent by the automatic test machine includes: each processor selects test content corresponding to the processor identifier of the processor from a plurality of test contents sent by the automatic test machine;
the calling the test unit configured in the system chip according to the test content and testing the system chip according to the test unit comprise: and the processors call the test units configured in the system chip in parallel according to the test content, and test the DUTs in parallel according to the test units.
In one aspect, a method for automatically testing a system chip is provided, the method comprising:
generating test content;
sending the test content to a system chip, wherein the system chip is used for calling a test unit configured in the system chip according to the test content, testing the system chip according to the test unit, generating a fingerprint according to a test result obtained after testing, and sending the fingerprint to an automatic test machine;
receiving the fingerprint sent by the system chip;
and comparing the fingerprint with a standard fingerprint, and determining the test result of the system chip according to the comparison result.
In one possible implementation, the method further includes: acquiring a standard test result corresponding to the test content, and generating a standard fingerprint according to the standard test result;
the determining the test result of the system chip according to the comparison result includes: when the fingerprint is the same as the standard fingerprint, determining that the test of the system chip is successful; and when the fingerprint is different from the standard fingerprint, determining that the test of the system chip fails.
In one aspect, an apparatus for automated testing of a system chip is provided, the apparatus comprising:
the configuration module is used for configuring a test unit in the system chip;
the receiving module is used for receiving the test content sent by the automatic test machine;
the test module is used for calling a test function configured in the system chip according to the test content and testing the system chip according to the test unit;
and the sending module is used for generating a fingerprint according to a test result obtained after the test, sending the fingerprint to the automatic test machine, and the automatic test machine is used for comparing the fingerprint with a standard fingerprint and determining the test result of the system chip according to the comparison result.
In one aspect, an apparatus for automated testing of system chips is provided, the apparatus comprising:
the generating module is used for generating test contents;
the sending module is used for sending the test content to a system chip, the system chip is used for calling a test unit configured in the system chip according to the test content, testing the system chip according to the test unit, generating a fingerprint according to a test result obtained after the test, and sending the fingerprint to an automatic test machine;
the receiving module is used for receiving the fingerprint sent by the system chip;
and the comparison module is used for comparing the fingerprint with a standard fingerprint and determining the test result of the system chip according to the comparison result.
In one aspect, a system chip is provided, which includes a processor and a memory, where the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the method for automatically testing the system chip as described above.
In one aspect, an automatic test machine is provided, where the automatic test machine includes a processor and a memory, where the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the above-mentioned method for automatically testing a system chip.
In one aspect, an automated testing system is provided, which includes the system chip and the automatic testing machine station as described above.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
because the system chip is provided with the test unit, the automatic test machine only needs to send test contents to the system chip, and does not need to send the test unit to the system chip, and the system chip can call the self-configured test unit according to the test contents to complete the test, thereby reducing the data transmission in the test process and improving the test speed.
The system chip sends the fingerprint of the test result to the automatic test machine, and the data volume of the fingerprint is smaller than that of the test result, so that the data transmission can be reduced, and the test speed is improved. In addition, the test result cannot be reversely deduced according to the fingerprint, so that the safety of the system chip can be improved.
The system chip authenticates the automatic test machine according to the message authentication code, tests after the authentication is successful, and burns the OTP flag bit when the authentication failure times exceed a preset time threshold value so as to indicate that the system chip does not perform automatic test any more through the OTP flag bit, thereby avoiding the system chip from being tested after being lost.
When the system chip comprises a plurality of processors and a plurality of DUTs, the plurality of processors can call the test units configured in the system chip in parallel according to the test content, and the plurality of DUTs are tested in parallel according to the plurality of test units, so that the test efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flowchart of a method for automated testing of a system-on-chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a storage location of a test unit according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating an authentication process between a system chip and an automatic test equipment according to an embodiment of the present disclosure;
FIG. 4 is a schematic flow chart diagram illustrating concurrent testing of DUTs according to one embodiment of the present application;
FIG. 5 is a schematic flow chart diagram illustrating concurrent testing of DUTs according to one embodiment of the present application;
FIG. 6 is a flowchart illustrating a method for automated testing of a system-on-chip according to one embodiment of the present application;
fig. 7 is a schematic flowchart of programming fast Fuse by calling a Fuse programming function according to an embodiment of the present application;
FIG. 8 is a schematic flow chart illustrating an adjustment of an analog quantity by calling a TRIM function according to an embodiment of the present application;
FIG. 9 is a block diagram of an apparatus for automated testing of a system on a chip according to an embodiment of the present application;
FIG. 10 is a block diagram of an apparatus for automated testing of a system chip according to an embodiment of the present application;
fig. 11 is a block diagram illustrating an automated testing apparatus for a system chip according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of an automated testing method for a system on chip according to an embodiment of the present application is shown, where the automated testing method for a system on chip can be applied to a system on chip. The automatic testing method of the system chip can comprise the following steps:
A test cell refers to the smallest unit that is called when testing a certain function of a system chip. In one example, the test unit includes a test function, or alternatively, the test unit includes a test function for individually testing a certain function of the system chip and other data, parameters, etc. that may be used in the test process. In another example, the test unit includes a series of test functions, or the test unit includes a series of test functions and other data, parameters, etc. that may be used in the test process, and the series of test functions are used to jointly test a certain function of the system chip, in which case the test unit may be understood as a small test program. It should be noted that the test unit configured in the system chip is the same as the test unit configured in the automatic test machine in the related art.
The test unit designed in this embodiment can be set and adjusted according to the test requirements of the system chip. When a plurality of test units are configured in the system chip, the plurality of test units correspond to at least two levels, and the test units of different levels can be called mutually. Therefore, different functions of the system chip can be flexibly tested by designing the calling relationship, and the testing flexibility is improved.
In this embodiment, the plurality of test units are divided into three levels, the first level test unit is used for calling a basic function in the system chip, and the second level test unit is used for calling the first level test unit to test a middle-level function in the system chip; the third level of test units is used to invoke the second level of test units and/or the first level of test units to test the high level functional functions in the system chip.
For ease of understanding, some commonly used test cells are illustrated below. In practical use, the test unit configured in the system chip may include all or part of the test units illustrated, or may include a test unit not illustrated in this embodiment.
The test unit of the first level is used to call the following basic function functions to implement the following functions:
(1) Sequentially reading a certain length of content in a section of address or a fixed address, and returning the fingerprint of the read content;
(2) Transporting data of a determined length from a fixed address or a continuous address to the fixed address or a section of the continuous address, wherein the fixed address is the condition of processing FIFO (First In First Out);
(3) Moving indefinite length data from a fixed address or a continuous address to the fixed address or a continuous address until values in the data match values in the configured test content;
(4) Continuously reading an address until the value of the address changes to an expected value, writing a specific value into another address, and returning the waiting time or the reading times, for example, clearing an interrupt action after waiting for the interrupt;
(5) Searching data matched with the test content in the data of a section of address, and returning the address of the data;
(6) Configuring a Phase Locked Loop (PLL) to a certain frequency;
the test unit of the second level is used for calling the following intermediate function functions to realize the following functions:
(1) Programming a section of data to OTP (One Time Programmable), and returning the fingerprint of the programming result;
(2) Programming a section of data to a Flash/EEPROM (Electrically Erasable Programmable read only memory), and returning the fingerprint of the programming result;
(3) In the Analog measurement process, the TRIM configuration sequence is increased or decreased, and handshake is performed with external IO (Input/Output) or a timer;
(4) Writing a length of data to a contiguous or fixed address and reading from another fixed address or contiguous address and returning a fingerprint of the read data, e.g. for use as a loopback test for some peripherals;
(5) Some work flows customized by the system chip, for example, entering a low power consumption work mode or entering a maximum power consumption mode, etc., can measure the current of various modes;
the third level of test units is used to call the following high-level functional functions, such as some high-level digital signal processing functions and IP-specific custom functions, to implement the following functions:
(1) Counting the average value and the variance of the data;
(2) Calculating an FFT (Fast Fourier Transform) or iFFT (Inverse Fast Fourier Transform) of a piece of data;
(3) Calculating the signal-to-noise ratio, the linearity and the like of AD (analog/digital)/DA (digital/analog) data;
(4) And preparing the AD/DA for data acquisition or output.
After the test cells are designed, they may be configured in a system chip. Specifically, the test unit may be configured in a ROM, or the test unit may be downloaded into a Static Random-Access Memory (SRAM) before the test is started.
Referring to fig. 2, in fig. 2, ATE Tester represents an automatic Test machine, pattern represents Test content, soC represents a system chip, ATE I/F represents an interface of a system chip, test Mode Ctrl represents a Test Mode controller for controlling the system chip to be in a Test Mode or a normal operating Mode, ATE Ctrl represents a machine controller, ATE DUT represents a function to be tested, ATE function represents a Test unit, and the Test unit is configured in ROM.
After the test unit is configured, the system chip can be connected with the automatic test machine so that the automatic test machine can test the system chip. For some system chips with high security requirements, the system chips can use passwords (password) to establish connection with automatic test machines, and only the automatic test machines with known passwords and handshake protocols can establish test authentication.
Specifically, when establishing the connection, the system chip may send a random number to the automatic test machine; receiving a first message authentication code sent by an automatic test machine, wherein the first message authentication code is generated by the automatic test machine after calculating a message authentication code for a received random number by using an appointed password; calculating a message authentication code for the random number by using the appointed password to obtain a second message authentication code; when the first message authentication code and the second message authentication code are the same, it is determined that the authentication is successful, and step 102 is performed. And when the first message authentication code is different from the second message authentication code, determining that the authentication fails, and updating the authentication failure times. When the authentication failure times exceed the preset times threshold, the system chip burns the OTP flag bit, and the OTP flag bit indicates that the system chip does not perform automatic testing any more, so that the system chip is prevented from being tested after being lost.
The algorithm of the Message Authentication Code may be an HMAC (Hash-based Message Authentication Code ) or a CMAC (Cipher Block Chaining-Message Authentication Code, message Authentication Code based on a symmetric key Block encryption algorithm), and the like, which is not limited in this embodiment.
Referring to fig. 3, a first step in fig. 3 is that the system chip sends a Random Number (Random Number) to the automatic tester, a second step is that the automatic tester sends a first Message Authentication Code (MAC) to the system chip, and a third step is that the system chip sends a result of passing/failing authentication to the automatic tester.
Therefore, the system chip can authenticate the automatic test machine without sending the password, and can prevent other equipment from being disguised as the automatic test machine to attack the system chip when the password is revealed to other equipment, so that the safety of the system chip is improved. In addition, the random numbers sent each time are different, even if the random numbers are leaked to other equipment, the other equipment cannot copy the random numbers to attack the system chip, and the safety of the system chip is further improved.
The test content is used to define the test unit and test parameters that need to be called when testing a certain function of the system chip. Because the system chip is provided with the test unit, the test content does not need to include the content of the test unit, thereby reducing the data volume of the test content, reducing the data transmission in the test process and improving the test speed.
In a first implementation, when a single test unit needs to be called for testing, the test content includes a pointer and test parameters of the single test unit.
In a second implementation manner, when a plurality of test units need to be called for testing, the test content includes call information and test parameters of the plurality of test units. For example, if the call information is the pointer of the test unit 1, the pointer of the test unit 2, and the pointer of the test unit 3, it means that the test unit 1 is called first, then the test unit 2 is called, and finally the test unit 3 is called.
And 103, calling a test unit configured in the system chip according to the test content, and testing the system chip according to the test unit.
In a first implementation manner, invoking a test unit configured in a system chip according to test content, and testing the system chip according to the test unit may include: and when the test content comprises the pointer and the test parameters of the single test unit, calling the test unit configured in the system chip according to the pointer, and testing the system chip according to the test unit and the test parameters.
In a second implementation manner, invoking a test unit configured in a system chip according to test content, and testing the system chip according to the test unit may include: when the test content comprises the calling information and the test parameters of the plurality of test units, the test units configured in the system chip are called in sequence according to the calling information, and the system chip is tested according to the test units and the test parameters.
And 104, generating a fingerprint according to the test result obtained after the test, sending the fingerprint to an automatic test machine, wherein the automatic test machine is used for comparing the fingerprint with the standard fingerprint and determining the test result of the system chip according to the comparison result.
The system chip sends the fingerprint of the test result to the automatic test machine, and the data volume of the fingerprint is smaller than that of the test result, so that the data transmission can be reduced, and the test speed is improved. In addition, the test result cannot be reversely deduced according to the fingerprint, so that the safety of the system chip can be improved.
There are many algorithms for generating a fingerprint based on the test result, and the specific algorithm is not limited in this embodiment. In one example, the system chip may calculate the test result by using a message digest algorithm, where the obtained fingerprint is a message digest, and the message digest algorithm may be a hash algorithm or other compression algorithm such as CRC.
The system chip sends the fingerprint to an automatic test machine, the automatic test machine can obtain a standard test result according to the simulation of the test content, a standard fingerprint is generated according to the standard test result, the received fingerprint is compared with the standard fingerprint, and when the fingerprint is the same as the standard fingerprint, the successful test of the system chip is determined; and when the fingerprint is different from the standard fingerprint, determining that the test of the system chip fails.
It should be noted that, for a test unit that does not return a test result, the system chip generates a pass or fail signal according to a test condition, and sends the pass or fail signal to the automatic test machine, and the automatic test machine determines a test result of the system chip according to the pass or fail signal.
The test in this embodiment may include not only a test for circuit correctness, but also a test for programming a nonvolatile memory in a system chip, for example, before shipping, OTP or flash in the system chip needs to be programmed, and the method provided in this embodiment may be used to improve efficiency.
The test method described in this embodiment can be applied to various test stages of the system chip, including CP (wafer test), FT (post package test), system test, factory return test, and the like, and is not limited to a test at a certain stage.
In summary, according to the automated testing method for the system chip provided by the embodiment of the present application, since the testing unit is configured in the system chip, the automatic testing machine only needs to send the testing content to the system chip, and does not need to send the testing unit to the system chip, and the system chip can call the testing unit configured by itself according to the testing content to complete the testing, thereby reducing data transmission in the testing process and improving the testing speed.
The system chip sends the fingerprint of the test result to the automatic test machine, and the data volume of the fingerprint is smaller than that of the test result, so that the data transmission can be reduced, and the test speed is improved. In addition, the test result cannot be reversely deduced according to the fingerprint, so that the safety of the system chip can be improved.
The system chip authenticates the automatic test machine according to the message authentication code, tests after the authentication is successful, and burns the OTP flag bit when the authentication failure times exceed a preset time threshold value so as to indicate that the system chip does not perform automatic test any more through the OTP flag bit, thereby avoiding the system chip from being tested after being lost.
When the system on a chip includes a plurality of processors and a plurality of DUTs (Design Under Test, functions to be tested), the plurality of processors can Test the plurality of DUTs in parallel, please refer to the parallel Test flow shown in fig. 4.
The configuration process of the test unit is described in step 101, and is not described herein again.
Referring to fig. 5, after the machine controller in the system chip receives a plurality of test contents through the ATE I/F interface, each test content is distributed to a corresponding processor according to the processor identifier corresponding to the test content.
In step 403, the multiple processors call the test units configured in the system chip in parallel according to the test content, and perform parallel testing on the multiple DUTs according to the multiple test units.
In fig. 5, pattern for DUT1 indicates the test contents of DUT1, and Pattern for DUT2 indicates the test contents of DUT 2.
After one processor acquires one test content, the DUT to be tested is determined according to the test parameters in the test content, so that a plurality of processors can test different DUTs in a system chip in parallel.
And 404, generating a fingerprint according to the test result obtained after the test, sending the fingerprint to an automatic test machine, wherein the automatic test machine is used for comparing the fingerprint with the standard fingerprint and determining the test result of the system chip according to the comparison result.
When the system chip comprises a plurality of processors and a plurality of DUTs, the processors can call the test units configured in the system chip in parallel according to the test content, and the DUTs are tested in parallel according to the test units, so that the test efficiency is improved.
Please refer to fig. 6, which illustrates a flowchart of an exemplary method for automatically testing a system chip according to an embodiment of the present disclosure. The automatic testing method of the system chip can comprise the following steps:
The test contents are used to define the test unit and test parameters to be called when testing a certain function of the system chip. Because the system chip is provided with the test unit, the test content does not need to include the content of the test unit, thereby reducing the data volume of the test content, reducing the data transmission in the test process and improving the test speed.
In a first implementation, when a single test unit needs to be called for testing, the test content includes a pointer and test parameters of the single test unit.
In a second implementation manner, when a plurality of test units need to be called for testing, the test content includes call information and test parameters of the plurality of test units.
It should be noted that, when the system chip includes a plurality of processors and a plurality of DUTs, the automatic test equipment generates a plurality of test contents, each test content corresponding to a processor identifier to instruct the corresponding processor to test the corresponding DUT.
And step 604, comparing the fingerprint with the standard fingerprint, and determining the test result of the system chip according to the comparison result.
Before determining the test result, the automatic test machine needs to obtain a standard test result corresponding to the test content, and generates a standard fingerprint according to the standard test result. The standard fingerprint generation algorithm is the same as the fingerprint generation algorithm, and is specifically obtained by running a completely correct chip prototype, wherein the chip prototype can be EDA simulation or hardware accelerator simulation.
When the fingerprint is the same as the standard fingerprint, determining that the test of the system chip is successful; and when the fingerprint is different from the standard fingerprint, determining that the test of the system chip fails.
In summary, according to the automated testing method for the system chip provided by the embodiment of the present application, since the testing unit is configured in the system chip, the automatic testing machine only needs to send the testing content to the system chip, and does not need to send the testing unit to the system chip, and the system chip can call the testing unit configured by itself according to the testing content to complete the testing, thereby reducing data transmission in the testing process and improving the testing speed.
The system chip sends the fingerprint of the test result to the automatic test machine, and the data volume of the fingerprint is smaller than that of the test result, so that the data transmission can be reduced, and the test speed is improved. In addition, the test result can not be reversely deduced according to the fingerprint, so that the safety of the system chip can be improved.
The following describes the test procedure by taking the test unit as a Fuse burn function (Fuse burn function) and calling the Fuse burn function to burn the fast Fuse, with reference to fig. 7.
(1) And writing the value to be programmed into the RAM through an ATE I/F interface.
(2) And the machine controller sends the test content to the CPU after receiving the test content, and the CPU calls a Fuse programming function built in the ROM according to the test content.
(3) The CPU executes the Fuse programming function and reads the value written in the RAM.
(4) And the CPU sequentially writes the numerical values into Fuse, and reads all written contents and calculates fingerprints after the numerical values are written.
(5) The CPU returns the fingerprint to the ATE I/F interface.
(6) And the ATE I/F interface sends the fingerprint to an ATE Tester, and the ATE Tester judges whether the programming is successful according to the fingerprint.
Comparing the present invention with the conventional method, the number of cycles required for Fuse programming and the memory space requirement are compared.
Assuming that 1KB of data needs to be written, the fixed procedure of writing the OTP each time is to write an address into the register of the OTP controller, then write the data into the register of the OTP controller, then configure the register of the OTP controller to perform a write operation corresponding to the address, then read the register of the OTP controller to confirm that the write operation is completed, and then write the next data.
After the write is completed, the data needing to read the OTP confirms whether the write is successful, each address is read by writing the address into a register of the OTP controller, then configuring the register of the OTP controller to perform a corresponding address read operation, then reading the register of the OTP controller confirms that the read is completed, and then the data stored in the corresponding address of the OTP can be read from the data register of the OTP controller.
Assuming that the ATE interface can run to 50MHz frequency, the CPU can run to 300mhz, 30 cycles are required for the ATE to access a word in the inner space once, while 5 cycles are required for the CPU (the actual CPU can perform burst mode for continuous address operation, and can turn on the cache faster). For the programming of 1KB of data, the time comparison is needed if the traditional mode and the mode of the invention are adopted.
In the traditional mode, read-write operation is required respectively, so that 2KB of storage space is required; in the invention, only read operation is needed, the data volume of the written fingerprint is very small and can be ignored, so that 1KB of storage space is needed.
Next, the test flow will be described by taking an example in which the test unit is a TRIM function (TRIM function), and the TRIM function is called to adjust the simulation (analog) amount, please refer to fig. 8.
(1) And writing test contents (TRIM program) into the RAM through the ATEI/F interface, wherein the test contents comprise the initialization of analog and TRIM flow control.
(2) And the machine controller sends the test content to the CPU after receiving the test content, and starts the CPU.
(3) The CPU calls the parameters of the TRIM function stored in the ROM, wherein the parameters comprise the register address of the analog TRIM value, an initial value, the configuration of each added value and the handshake condition (IO is adopted).
(4) And after the CPU finishes the preparation, setting a first TRIM value in Analog IO, sending a handshake request at a port of the GPIO controller, and waiting for an ATE Tester to respond.
(5) And after waiting for the system chip to send a handshake request, the ATE Tester measures Analog quantity at Analog IO, and responds to the handshake request of the system chip after measurement is finished.
(6) And after the response of the handshake request is obtained, configuring the value of the TRIM register as a current value + +, outputting through Analog IO, sending out the handshake request at a port of the GPIO controller, and waiting for the response of an ATE Tester.
(7) And repeating the two steps until the TRIM is set, and returning the test to be finished by the CPU.
(8) And the ATE Tester compares the test items of analog quantity according to the initial value of the TRIM and the convention that the TRIM is increased after each handshake, obtains the TRIM value under the optimal condition and records the TRIM value.
Referring to fig. 9, a block diagram of an apparatus for automatically testing a system on a chip according to an embodiment of the present application is shown. The automatic testing device of the system chip can comprise:
a configuration module 910, configured to configure a test unit in a system chip;
a receiving module 920, configured to receive test contents sent by an automatic test machine;
a testing module 930, configured to call a testing function configured in the system chip according to the testing content, and test the system chip according to the testing unit;
and a sending module 940, configured to generate a fingerprint according to a test result obtained after the test, send the fingerprint to an automatic test machine, where the automatic test machine is configured to compare the fingerprint with a standard fingerprint, and determine a test result of the system chip according to the comparison result.
In an alternative embodiment, the testing module 930 is further configured to:
and when the test content comprises the pointer and the test parameters of the single test unit, calling the test unit configured in the system chip according to the pointer, and testing the system chip according to the test unit and the test parameters.
In an alternative embodiment, the testing module 930 is further configured to:
when the test content comprises the calling information and the test parameters of the plurality of test units, the test units configured in the system chip are sequentially called according to the calling information, and the system chip is tested according to the test units and the test parameters.
In an optional embodiment, the sending module 940 is further configured to send a random number to the automatic test equipment before receiving the test content sent by the automatic test equipment;
the receiving module 920 is further configured to receive a first message authentication code sent by the automatic test machine, where the first message authentication code is generated by the automatic test machine computing a message authentication code for a received random number by using an agreed password;
referring to fig. 10, the apparatus further includes an encryption module 950 for calculating a message authentication code for the random number by using the agreed password to obtain a second message authentication code;
the determining module 960 is configured to determine that the authentication is successful when the first message authentication code is the same as the second message authentication code, and trigger execution of a step of receiving the test content sent by the automatic test equipment.
In an alternative embodiment, the determining module 960 is further configured to determine that the authentication fails when the first message authentication code is different from the second message authentication code;
the apparatus further includes a programming module 970, configured to program a one-time programmable OTP flag when the number of authentication failures exceeds a preset number threshold, where the OTP flag indicates that the system chip does not perform the automatic test any more.
In an alternative embodiment, when a plurality of test units are configured in the system chip, the plurality of test units correspond to at least two levels, and the test units of different levels can be called each other.
In an alternative embodiment, when the plurality of test units correspond to three levels, the test unit of the first level is used for calling a basic function in the system chip, and the test unit of the second level is used for calling the test unit of the first level to test a middle-level function in the system chip; the third level test unit is used for calling the second level test unit and/or the first level test unit to test the high-level function in the system chip.
In an optional embodiment, when the system on chip includes a plurality of processors and a plurality of DUTs, the receiving module 920 is further configured to select, by each processor, a test content corresponding to its own processor identifier from a plurality of test contents sent by the automatic test equipment;
a test module 930 further configured to: and calling the test units configured in the system chip in parallel according to the test content through the plurality of processors, and testing the plurality of DUTs in parallel according to the plurality of test units.
To sum up, the automatic testing device for the system chip provided by the embodiment of the application has the advantages that the testing unit is configured in the system chip, so that the automatic testing machine only needs to send the testing content to the system chip, the testing unit does not need to be sent to the system chip, and the system chip can call the testing unit configured by the system chip according to the testing content to complete the testing, so that the data transmission in the testing process is reduced, and the testing speed is improved.
The system chip sends the fingerprint of the test result to the automatic test machine, and the data volume of the fingerprint is smaller than that of the test result, so that the data transmission can be reduced, and the test speed is improved. In addition, the test result cannot be reversely deduced according to the fingerprint, so that the safety of the system chip can be improved.
The system chip authenticates the automatic test machine according to the message authentication code, tests after the authentication is successful, and burns the OTP flag bit when the authentication failure times exceed a preset time threshold value so as to indicate that the system chip does not perform automatic test any more through the OTP flag bit, thereby avoiding the system chip from being tested after being lost.
When the system chip comprises a plurality of processors and a plurality of DUTs, the plurality of processors can call the test units configured in the system chip in parallel according to the test content, and the plurality of DUTs are tested in parallel according to the plurality of test units, so that the test efficiency is improved.
Referring to fig. 11, a block diagram of an automated testing apparatus for a system on chip according to an embodiment of the present disclosure is shown, where the automated testing apparatus for a system on chip can be applied to an automated testing machine. The automatic testing device of the system chip can comprise:
a generating module 1110, configured to generate test content;
the sending module 1120 is configured to send the test content to the system chip, and the system chip is configured to call a test unit configured in the system chip according to the test content, test the system chip according to the test unit, generate a fingerprint according to a test result obtained after the test, and send the fingerprint to an automated test machine;
a receiving module 1130, configured to receive a fingerprint sent by a system chip;
and a comparing module 1140, configured to compare the fingerprint with the standard fingerprint, and determine a test result of the system on chip according to the comparison result.
In an optional embodiment, the generating module 1110 is further configured to obtain a standard test result corresponding to the test content, and generate a standard fingerprint according to the standard test result;
the comparison module 1140 is further configured to determine that the testing of the system chip is successful when the fingerprint is the same as the standard fingerprint; and when the fingerprint is different from the standard fingerprint, determining that the test of the system chip fails.
To sum up, the automatic testing device for a system chip provided by the embodiment of the present application, because the system chip is configured with the testing unit, the automatic testing machine only needs to send the testing content to the system chip, and does not need to send the testing unit to the system chip, and the system chip can call the testing unit configured by itself according to the testing content to complete the testing, thereby reducing the data transmission in the testing process and improving the testing speed.
The system chip sends the fingerprint of the test result to the automatic test machine, and the data volume of the fingerprint is smaller than that of the test result, so that the data transmission can be reduced, and the test speed is improved. In addition, the test result cannot be reversely deduced according to the fingerprint, so that the safety of the system chip can be improved.
One embodiment of the present application provides a system chip, which includes a processor and a memory, where the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the method for automatically testing the system chip as described above.
An embodiment of the present application provides an automatic test machine, where the automatic test machine includes a processor and a memory, where the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the above-mentioned automatic test method for a system chip.
An embodiment of the present application provides an automatic test system, which includes the system chip and the automatic test machine as described above.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is not intended to limit the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.
Claims (15)
1. An automated testing method for a system chip, the method comprising:
configuring a test unit in a system chip;
receiving test contents sent by the automatic test machine;
calling a test unit configured in the system chip according to the test content, and testing the system chip according to the test unit;
and generating a fingerprint according to a test result obtained after the test, sending the fingerprint to the automatic test machine, wherein the automatic test machine is used for comparing the fingerprint with a standard fingerprint and determining the test result of the system chip according to the comparison result.
2. The method according to claim 1, wherein the calling a test unit configured in the system chip according to the test content and testing the system chip according to the test unit comprises:
and when the test content comprises a pointer and a test parameter of a single test unit, calling the test unit configured in the system chip according to the pointer, and testing the system chip according to the test unit and the test parameter.
3. The method according to claim 1, wherein the invoking a test unit configured in the system chip according to the test content and testing the system chip according to the test unit comprises:
when the test content comprises calling information and test parameters of a plurality of test units, sequentially calling the test units configured in the system chip according to the calling information, and testing the system chip according to the test units and the test parameters.
4. The method for automatically testing soc of claim 1, wherein before the receiving test contents sent by the automatic test equipment, the method further comprises:
sending a random number to the automatic test machine;
receiving a first message authentication code sent by the automatic test machine, wherein the first message authentication code is generated after the automatic test machine calculates a message authentication code for the received random number by using an agreed password;
calculating a message authentication code for the random number by using the agreed password to obtain a second message authentication code;
and when the first message authentication code is the same as the second message authentication code, determining that the authentication is successful, and triggering and executing the step of receiving the test content sent by the automatic test machine.
5. The method for automated testing of a system-on-chip as claimed in claim 4, wherein the method further comprises:
determining that authentication fails when the first message authentication code is different from the second message authentication code;
and when the number of times of authentication failure exceeds a preset number threshold, programming a one-time programmable (OTP) flag bit, wherein the OTP flag bit indicates that the system chip does not perform automatic test any more.
6. The method as claimed in claim 1, wherein when a plurality of test units are configured in the soc, the plurality of test units correspond to at least two levels, and the test units of different levels can be mutually invoked.
7. The method for automatically testing a system-on-chip as claimed in claim 6, wherein when the plurality of test units correspond to three levels, a first level of test units is used for calling basic function functions in the system-on-chip, and a second level of test units is used for calling the first level of test units to test intermediate function functions in the system-on-chip; the third level test unit is used for calling the second level test unit and/or the first level test unit to test the high-level function in the system chip.
8. The method for automated testing of a system-on-chip according to any one of claims 1 to 7,
when the system chip comprises a plurality of processors and a plurality of functional DUTs to be tested, the receiving of the test content sent by the automatic test machine comprises: each processor selects test content corresponding to the processor identifier of the processor from a plurality of test contents sent by the automatic test machine;
the calling the test unit configured in the system chip according to the test content and testing the system chip according to the test unit comprise: and the processors parallelly call the test units configured in the system chip according to the test content, and parallelly test the DUTs according to the test units.
9. A method for automated testing of a system chip, the method comprising:
generating test content;
sending the test content to a system chip, wherein the system chip is used for calling a test unit configured in the system chip according to the test content, testing the system chip according to the test unit, generating a fingerprint according to a test result obtained after testing, and sending the fingerprint to an automatic test machine;
receiving the fingerprint sent by the system chip;
and comparing the fingerprint with a standard fingerprint, and determining the test result of the system chip according to the comparison result.
10. The method for automatically testing a system-on-chip as claimed in claim 9,
the method further comprises the following steps: acquiring a standard test result corresponding to the test content, and generating a standard fingerprint according to the standard test result;
the determining the test result of the system chip according to the comparison result includes: when the fingerprint is the same as the standard fingerprint, determining that the test of the system chip is successful; and when the fingerprint is different from the standard fingerprint, determining that the test of the system chip fails.
11. An apparatus for automated testing of system chips, the apparatus comprising:
the configuration module is used for configuring the test unit in the system chip;
the receiving module is used for receiving the test content sent by the automatic test machine;
the test module is used for calling a test function configured in the system chip according to the test content and testing the system chip according to the test unit;
and the sending module is used for generating a fingerprint according to a test result obtained after the test, sending the fingerprint to the automatic test machine, and the automatic test machine is used for comparing the fingerprint with a standard fingerprint and determining the test result of the system chip according to the comparison result.
12. An apparatus for automated testing of a system chip, the apparatus comprising:
the generating module is used for generating test contents;
the sending module is used for sending the test content to a system chip, the system chip is used for calling a test unit configured in the system chip according to the test content, testing the system chip according to the test unit, generating a fingerprint according to a test result obtained after the test, and sending the fingerprint to an automatic test machine;
the receiving module is used for receiving the fingerprint sent by the system chip;
and the comparison module is used for comparing the fingerprint with a standard fingerprint and determining the test result of the system chip according to the comparison result.
13. A system chip, comprising a processor and a memory, the memory having stored therein at least one instruction, the instruction being loaded and executed by the processor to implement the method for automated testing of a system chip according to any of claims 1 to 8.
14. An automatic test machine, comprising a processor and a memory, wherein the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the method for automatically testing the system chip according to claim 9 or 10.
15. An automatic test system, characterized in that the automatic test system comprises the system chip of claim 13 and the automatic test machine of claim 14.
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