CN115483207A - Resistor layout, design method thereof and semiconductor structure - Google Patents

Resistor layout, design method thereof and semiconductor structure Download PDF

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Publication number
CN115483207A
CN115483207A CN202211163913.6A CN202211163913A CN115483207A CN 115483207 A CN115483207 A CN 115483207A CN 202211163913 A CN202211163913 A CN 202211163913A CN 115483207 A CN115483207 A CN 115483207A
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resistor
layout
resistor array
array
contact vias
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梁子骞
高东旭
徐浩然
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Ehiway Microelectronic Science And Technology Suzhou Co ltd
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Ehiway Microelectronic Science And Technology Suzhou Co ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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Abstract

The invention provides a resistor layout, a design method thereof and a semiconductor structure, wherein the resistor layout comprises the following steps: a first resistor array and a second resistor array; the first resistor array comprises a plurality of first resistor unit segments which extend along a first direction and are arranged along a second direction, wherein the first direction and the second direction are intersected; the second resistor array comprises a plurality of second resistor unit segments which extend along a first direction and are arranged along a second direction; wherein the second resistive array is located outside the first resistive array in a second direction. According to the embodiment of the invention, the second resistor array is arranged on the periphery of the first resistor array, so that the first resistor unit section at the edge is far away from the process processing edge, the finally obtained expected resistor is less influenced by the process in the manufacturing process, and the precision and reliability of the resistor are improved.

Description

Resistor layout, design method thereof and semiconductor structure
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a resistor layout, a design method thereof and a semiconductor structure.
Background
The resistor can be used as a bias resistor in an analog circuit to determine the working point of the circuit, and the resistor and the capacitor can form a filter and delay circuit, a voltage divider, a shunt and a load resistor. The resistor is widely applied to analog circuits. An accurate resistor is designed in the design of an analog circuit, for example, in an LDO (low drop out regulator) circuit, a reference (ref) voltage is obtained by multiplying a current by a resistor, so that the requirement on the accuracy of the resistor is high; semiconductor device resistors during manufacturing, the resistors will be affected by semiconductor process tolerances and different semiconductor process handling when manufacturing other devices around the resistors. Therefore, the actually produced resistance value has deviation with the resistance value in the circuit design, and if the deviation of the resistance value is ignored, the stability and the reliability of the product can not be ensured.
The resistor produced based on the current resistor layout structure has a large error with the expected resistance value in the circuit design. Therefore, how to optimize the resistor layout structure and further improve the accuracy and reliability of the resistor is a problem to be solved urgently.
Disclosure of Invention
The invention aims to solve all or part of problems in the prior art, and provides a resistor layout.A second resistor array is arranged at the periphery of a first resistor array, so that a first resistor unit section at the edge is farther away from a process processing edge, the finally obtained expected resistor is less influenced by the process in the manufacturing process, and the precision and reliability of the resistor are improved.
The invention provides a resistor layout, which comprises: a first resistor array and a second resistor array; the first resistor array comprises a plurality of first resistor unit segments which extend along a first direction and are arranged along a second direction, wherein the first direction and the second direction are intersected; the second resistor array comprises a plurality of second resistor unit segments which extend along a first direction and are arranged along a second direction; wherein the second resistive array is located outside the first resistive array in a second direction. According to the embodiment of the invention, the second resistor array is arranged on the periphery of the first resistor array, so that the environment of the first resistor unit section at the edge in the first resistor array is the same as the environment of other first resistor unit sections, and the resistor precision is improved. And the first resistance unit section at the edge is farther from the process processing edge, so that the finally obtained expected resistance is less influenced by the process in the manufacturing process, and the precision and reliability of the resistance are improved. Meanwhile, the influence of noise on the first resistance unit section located at the edge can be reduced. The second resistor array not only improves the resistance accuracy of the first resistor array, but also provides a spare second resistor unit section for correcting the resistance of the first resistor array.
Normally, the second resistor arrays can be arranged in one group; two sets of resistors can be arranged and are respectively positioned on two opposite sides of the first resistor array in the second direction. Preferably, the second resistor array is symmetrically disposed outside the first resistor array, and the symmetrical disposition protects both side edges of the first resistor array.
The resistance layout further comprises: a plurality of first contact vias, wherein the first contact vias are disposed along a first direction in the first resistor unit segment, and are electrically connected to the first resistor unit segment, preferably, the first contact vias are disposed at two ends of the first resistor unit segment along the first direction, and of course, the number and the positions of the first contact vias may be set according to actual needs; a plurality of first connection conductors electrically connected to the first contact via holes on different first resistance unit sections, respectively; a plurality of second contact vias, the second contact vias being disposed along the first direction in the second resistor unit segment, and the second contact vias being electrically connected to the second resistor unit segment, preferably, the second contact vias are disposed at two ends of the second resistor unit segment along the first direction, and of course, the number and positions of the second contact vias may be set according to actual needs; optimally, the number and the position of the second contact vias arranged on one second resistance unit segment are the same as the number and the position of the first contact vias of the closest first resistance unit segment; and the second connecting conductors are respectively and electrically connected with the second contact guide holes on different second resistance unit sections. Here, the first resistance unit segment includes, but is not limited to, a polysilicon resistor, a well resistor, a metal resistor, etc., and the first resistance unit segment and the second resistance unit segment may be the same. The plurality of first resistor unit sections are connected with the first contact via holes through the first connecting conductors, so that the total resistance of the first resistor array can be regulated. The plurality of first resistance unit segments are connected in series by a plurality of first connecting conductors, and/or the plurality of second resistance unit segments are connected in series by a plurality of second connecting conductors. Therefore, the total resistance of the first resistor unit sections can be adjusted conveniently in the following process.
The resistance layout further comprises: a plurality of third connecting conductors, each of which electrically connects two of the second contact via holes located on the same second resistance unit segment; and the second resistor array is connected with the ground wire through the fourth connecting conductor. Therefore, the two second contact guide holes of each second resistor unit section are in short circuit, and the second resistor array is connected with the ground wire in the circuit, so that the interference of noise on the resistor is further reduced.
The distance between adjacent first resistance unit sections along the second direction is a first width; the distance between the first resistor array and the second resistor array along a second direction is a second width; the distance between every two adjacent second resistance unit sections in the second direction is a third width; wherein the first width, the second width, and the third width are equal. Due to the edge process effect, theoretical and experimental data show that when the distance between the first resistor array and the second resistor array along the second direction is equal to the distance between the first resistor unit segments along the second direction, the protection effect of the second resistor array is better than that when the distances are not equal; when the distance between the adjacent second resistor unit sections along the second direction is equal to the distance between the adjacent first resistor unit sections along the second direction, the protection effect of the second resistor array is better than that of the second resistor array when the distances are not equal; wherein the best technical effect is when the first width, the second width and the third width are equal.
The resistance layout further comprises: a dummy resistor located outside the second resistor array in a second direction, the dummy resistor extending in a first direction and parallel to the second resistor unit segment. In this manner, the dummy resistor may further enable the process environment of the second resistor unit segment at the edge to be consistent with the process environment of the other second resistor unit segments. In the subsequent process, all the second resistor unit sections can be used as standby trimming resistors of the first resistor unit sections.
The resistance layout further comprises: a third resistor array including a plurality of third resistor unit segments extending in the first direction and arranged in the second direction; wherein the third resistor array is located outside the first resistor array in the first direction. Preferably, the third resistor arrays are respectively located at two opposite sides of the first resistor array in the first direction. Therefore, the third resistor array can protect the first resistor array, the influence of the process edge is reduced, and the resistor precision is improved.
The invention also provides a semiconductor structure which comprises the resistance layout or is prepared from the resistance layout.
The invention also provides a design method of the resistor layout, which comprises the following steps: step S1: obtaining an original resistor layout group, wherein the original resistor layout group at least comprises a first resistor array layout, and the first resistor array layout comprises a plurality of first resistor unit segments which extend along a first direction and are distributed along a second direction; step S2: and arranging a second resistor array layout in the original resistor layout group, wherein the second resistor array layout is positioned at the outer side of the first resistor array layout in the second direction, and the second resistor array layout comprises a plurality of second resistor unit segments which extend along the first direction and are distributed along the second direction. In general, the layout layer of the second resistor unit segment is the same as the layout layer of the first resistor unit segment; under specific process conditions, the two can also be located in different plate layers.
In the step S1, the first resistor array layout is further provided with: a plurality of first contact vias provided in the first resistor unit segment in a first direction, the first contact vias being electrically connected to the first resistor unit segment; a plurality of first connection conductors electrically connected to the first contact vias on different first resistance unit sections, respectively. In the step S2, the second resistor array layout is further provided with: a plurality of second contact vias provided along a first direction in the second resistor unit section, the second contact vias being electrically connected to the second resistor unit section; and the second connecting conductors are respectively and electrically connected with the second contact guide holes on different second resistance unit sections. In general, the layout layer of the second contact via is the same as the layout layer of the first contact via, and the layout layer of the second connection conductor is the same as the layout layer of the first connection conductor; under specific process conditions, the layout layer of the second contact guide hole and the layout layer of the first contact guide hole can be located on different layout layers, and the layout layer of the second connecting conductor and the layout layer of the first connecting conductor can be located on different layout layers.
After the second resistor array layout is set, the method further comprises: arranging a plurality of third connecting conductors, wherein each third connecting conductor is electrically connected with two second contact guide holes on the same second resistor unit section; and arranging a fourth connecting conductor, wherein the second resistor array layout is connected with the ground wire through the fourth connecting conductor. The layout layer of the third connecting conductor, the layout layer of the fourth connecting conductor and the layout layer of the second connecting conductor may be the same.
After the fourth connecting conductor is provided, the method further comprises: arranging a fifth connecting conductor, wherein the fifth connecting conductor is connected with the first resistor array layout and the second resistor array layout; removing part of the second connecting conductor to decompose the second resistor array layout into a practical second resistor array layout and a virtual second resistor array layout, wherein the practical second resistor array layout is connected with the first resistor array layout through a fifth connecting conductor; removing a third connecting conductor located within the utility second resistor array layout. The layout layer of the fifth connecting conductor and the layout layer of the second connecting conductor may be the same.
Compared with the prior art, the invention has the main beneficial effects that:
according to the resistor layout provided by the invention, the second resistor array is arranged at the periphery of the first resistor array, so that the environment of the first resistor unit section at the edge in the first resistor array is the same as the environment of other first resistor unit sections, and the resistor precision is improved. And the first resistance unit section at the edge is far away from the process processing edge, so that the finally obtained expected resistance is less influenced by the process in the manufacturing process, and the precision and reliability of the resistance are improved. Meanwhile, the influence of noise on the first resistance unit section located at the edge can be reduced. The second resistor array not only improves the resistance value precision of the first resistor array, but also provides a spare second resistor unit section for correcting the resistance value of the first resistor array.
According to the method for designing the resistor layout, the second resistor unit segment in the second resistor array layout can be directly utilized, the connecting line is changed to connect part of the second resistor unit segment with the first resistor array layout, so that the resistance value of the original layout group is modified, the resistor layout design time can be reduced, the layout design efficiency is improved, and the cost is saved.
Drawings
Fig. 1 is a schematic structural diagram of a resistor layout provided in an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another resistor layout provided in the embodiment of the present invention;
fig. 3 is a schematic structural diagram of another resistor layout according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for designing a resistor layout according to an embodiment of the present invention;
fig. 5a to 5f are schematic structural diagrams of the resistor layout provided in the embodiment of the present invention in the design process.
Reference numerals:
10-original resistance layout group; 11-a first resistor array; 111-a first resistive unit segment; 112-a first contact via; 113-a first connection conductor; 12-a second resistive array; 121-a second resistive unit segment; 122-a second contact via; 123-a second connection conductor; 124-third connecting conductor; 125-a fourth connecting conductor; 126-ground; 127-dummy resistance; 128-fifth connecting conductor; 13-a third resistor array; 14-utility second resistor array; 15-dummy second resistor array.
Detailed Description
The technical solutions in the specific embodiments of the present invention will be clearly and completely described below, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In a semiconductor manufacturing process, a complete semiconductor device is completed by a plurality of process steps, and the semiconductor device closer to the process processing edge is more influenced by process errors. In practical operation, in the process of preparing the resistor through the resistor layout, the resistor unit section at the edge may fail to be etched due to exposure transition or insufficiency, or the size and precision of the physical pattern of the resistor unit section may be affected due to light reflection and diffraction in the photolithography process. In layout design, adding a resistor protection structure around a resistor is a common practice for improving resistor precision. The traditional resistor protection layout structure method comprises the following steps: taking polysilicon resistor as an example, dummy resistors (dummy) equal to polysilicon resistor segment size and spacing are added on both sides of the polysilicon resistor, and the conventional resistor protection structure has a limited effect on improving resistor precision.
Based on this, referring to fig. 1, the present invention provides a resistor layout, which includes: a first resistor array 11 and a second resistor array 12; the first resistor array 11 includes a plurality of first resistor unit segments 111 extending in a first direction and arranged in a second direction, wherein the first direction and the second direction intersect; the second resistor array 12 includes a plurality of second resistor unit segments 121 extending in the first direction and arranged in the second direction; wherein the second resistor array 12 is located outside the first resistor array 11 in the second direction.
According to the embodiment of the invention, the second resistor array is arranged at the periphery of the first resistor array, so that the environment of the first resistor unit section at the edge in the first resistor array is the same as the environment of other first resistor unit sections, and the resistor precision is improved. And the first resistance unit section at the edge is farther from the process processing edge, so that the finally obtained expected resistance is less influenced by the process in the manufacturing process, and the precision and reliability of the resistance are improved. Meanwhile, the influence of noise on the first resistance unit section located at the edge can be reduced. The second resistor array not only improves the resistance value precision of the first resistor array, but also provides a spare second resistor unit section for correcting the resistance value of the first resistor array. Here, the width and length of the first resistor unit segment may be any values allowed by the process, and are not limited. The first resistor unit segment includes, but is not limited to, a poly (polysilicon) resistor, a well resistor, a metal resistor, etc. The first resistance unit segment and the second resistance unit segment may be the same. The resistor array may include Positive (PLUS) and negative (MINUS) poles, and may be used for input and output of test signals.
In some embodiments, the resistor array may also include Positive (PLUS), negative (MINUS), and B tripolar. Taking the polysilicon resistor as an example, the substrate right below the three-terminal resistor is connected to a fixed potential, i.e. corresponding to the B pole. For example, the B terminal of the n-well resistor is power, and the B terminal of the p-well resistor is ground. The influence of substrate noise (noise) on the polysilicon is reduced by applying a potential to the substrate below the resistor through the B pole.
In some embodiments, the second resistor arrays 12 may be arranged in one group; two sets of resistors may be disposed, respectively on two opposite sides of the first resistor array 11 in the second direction. Preferably, the second resistor array may be symmetrically disposed outside the first resistor array, and the symmetrical disposition enables both side edges of the first resistor array to be protected.
Continuing with fig. 1, the resistor layout further includes: a plurality of first contact vias 112, the first resistor unit segment 111 is provided with first contact vias 112 along a first direction, the first contact vias 112 are electrically connected with the first resistor unit segment 111, preferably, the first contact vias are arranged at two ends of the first resistor unit segment along the first direction, and of course, the number and positions of the first contact vias can be set according to actual requirements; a plurality of first connection conductors 113, the first connection conductors 113 being electrically connected to the first contact vias 112 located on different first resistance unit segments 111, respectively; a plurality of second contact vias 122, wherein the second contact vias 122 are disposed along the first direction in the second resistor unit segment 121, and the second contact vias 122 are electrically connected to the second resistor unit segment 111, preferably, the second contact vias are disposed at two ends of the second resistor unit segment along the first direction, and of course, the number and positions of the second contact vias may be set according to actual needs; optimally, the number and the position of the second contact vias arranged on one second resistance unit segment are the same as the number and the position of the first contact vias of the closest first resistance unit segment; and a plurality of second connection conductors 123, wherein the second connection conductors 123 are electrically connected to the second contact vias 122 located on different second resistance unit segments 121, respectively. In practice, the first connection conductor and the second connection conductor may extend in the second direction. The plurality of first resistor unit sections are connected with the first contact via holes through the first connecting conductors, so that the total resistance of the first resistor array can be regulated.
In some embodiments, as shown in fig. 1, a plurality of first resistive unit segments are connected in series by a plurality of first connecting conductors 113, and/or a plurality of second resistive unit segments are connected in series by a plurality of second connecting conductors 123. Therefore, the total resistance of the first resistor unit sections can be adjusted conveniently in the following process. In other embodiments, a plurality of first resistance unit segments may be connected in parallel by a plurality of first connection conductors 113, and/or a plurality of first resistance unit segments may be connected in parallel by a plurality of first connection conductors 113. Taking the example that the first resistor unit segments are connected in series through the first connecting conductors 113, the resistance of each first resistor unit segment is R1, and the resistances of the first connecting conductors and the second connecting conductors and the resistances of the contact vias are much smaller than the resistance of the first resistor unit segments, so that the resistance can be omitted.
In some embodiments, with continued reference to fig. 1, the resistance layout further includes: a plurality of third connecting conductors 124, each third connecting conductor 124 electrically connecting two second contact vias 122 located on the same second resistive unit segment 121; and a fourth connecting conductor 125, and the second resistor array 121 is connected to the ground line 126 through the fourth connecting conductor 125. The third connecting conductor may be parallel to the second resistance unit segment.
Therefore, the two second contact guide holes of each second resistor unit section are in short circuit, the second resistor array is connected with the ground wire in the circuit, and the interference of noise to the resistor is further reduced.
The first, second, third and fourth connection conductors include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The resistances of the first connection conductor, the second connection conductor, the third connection conductor, and the fourth connection conductor are very small and negligible compared to the resistance of the first resistance unit segment.
In some embodiments, as shown in fig. 1, a spacing (spacing) of adjacent first resistor unit segments 111 in the second direction is a first width W1; the distance between the first resistor array 11 and the second resistor array 12 in the second direction is a second width W2; the distance between adjacent second resistance unit segments 121 along the second direction is a third width W3; the first width W1, the second width W2, and the third width W3 are equal. Due to the edge process effect, theories and experiments show that when the distance between the first resistor array 11 and the second resistor array 12 in the second direction is equal to the distance between the first resistor unit segments in the second direction, the protection effect of the second resistor array is better than that when the distances are not equal, namely W2= W1; when the distance between the adjacent second resistor unit segments 121 in the second direction is equal to the distance between the adjacent first resistor unit segments in the second direction, the protection effect of the second resistor array is better than that when the distances are not equal, that is, W3= W1; the best technical effect is when the first width, the second width and the third width are equal, i.e. W3= W2= W1.
In some embodiments, as shown in fig. 2, the resistance layout further includes: and the dummy resistors 127, the dummy resistors 127 are positioned outside the second resistor array 12 along the second direction, and the dummy resistors 127 extend along the first direction and are parallel to the second resistor unit segment 121. The second resistor array 12 and the dummy resistors 127 are spaced apart by a fourth width W4 in the second direction, and the fourth width W4 is equal to the third width W3. In this manner, the dummy resistor may further enable the process environment of the second resistor unit segment at the edge to be consistent with the process environment of the other second resistor unit segments. In the subsequent process, all the second resistance unit sections can be used as standby trimming resistors of the first resistance unit sections.
In some embodiments, as shown in fig. 3, the resistance layout further includes: a third resistor array 13, the third resistor array 13 including a plurality of third resistor unit segments 131 extending in the first direction and arranged in the second direction; the third resistor array is positioned on the outer side of the first resistor array in the first direction. Preferably, the third resistor arrays are respectively located at two opposite sides of the first resistor array in the first direction. In practical operation, the connection manner of each third resistor unit segment in the third resistor array may be the same as the connection manner of each first resistor unit segment in the first resistor array. Here, a pitch of adjacent third resistance unit segments in the second direction is a fifth width W5; experiments show that when the distance of the third resistor unit segments in the second direction is equal to the distance of the first resistor unit segments in the second direction, the protection effect of the second resistor array is the best, i.e., W5= W1. Therefore, the third resistor array can protect the first resistor array, the process edge influence is reduced, and the resistor precision is improved. The third resistance unit segment 131 may be identical to the first resistance unit segment 111.
The invention also provides a design method of the resistor layout, which comprises the following steps of:
the method comprises the following steps of S1, obtaining an original resistance layout, wherein the original resistance layout comprises a first resistance array, the first resistance array comprises a plurality of first resistance unit sections which extend along a first direction and are distributed along a second direction, and the first direction and the second direction are intersected;
and S2, arranging a second resistor array, wherein the second resistor array is positioned on the outer side of the first resistor array in the second direction and comprises a plurality of second resistor unit sections which extend along the first direction and are distributed along the second direction.
The following describes a method for designing a resistor layout according to an embodiment of the present invention with reference to fig. 5a to 5 f.
First, step S1 is executed, referring to fig. 5a, to obtain an original resistor layout group 10, where the original resistor layout group 10 at least includes a first resistor array 11 layout, and the first resistor array 11 layout includes a plurality of first resistor unit segments 111 extending along a first direction and arranged along a second direction, where the first direction and the second direction intersect. In general, the layout layer of the second resistor unit segment is the same as the layout layer of the first resistor unit segment; under specific process conditions, the two can also be located in different plate layers.
The first resistor array 11 layout is further provided with: a plurality of first contact vias 112, wherein the first contact vias 112 are respectively arranged at two ends of the first resistor unit section along the first direction, and the first contact vias 112 are electrically connected with the first resistor unit section 111; and a plurality of first connection conductors 113, the first connection conductors 113 electrically connecting the first contact vias 112 respectively located on different first resistance unit segments 111.
Next, step S2 is executed, referring to fig. 5b, a second resistor array 12 layout is set, the second resistor array 12 layout is located at the outer side of the first resistor array 11 layout in the second direction, and the second resistor array 12 layout includes a plurality of second resistor unit segments 121 extending along the first direction and arranged along the second direction.
The second resistor array 12 layout is also provided with: a plurality of second contact vias 122, wherein the second contact vias 122 are respectively disposed at two ends of the second resistor unit segment 121 along the first direction, and the second contact vias 122 are electrically connected with the second resistor unit segment 121; and a plurality of second connection conductors 123, the second connection conductors 123 electrically connecting the second contact vias 122 respectively located on different second resistance unit segments 121. In general, the layout layer of the second contact via is the same as the layout layer of the first contact via, and the layout layer of the second connection conductor is the same as the layout layer of the first connection conductor; under specific process conditions, the layout layer of the second contact guide hole and the layout layer of the first contact guide hole can be located in different layout layers, and the layout layer of the second connecting conductor and the layout layer of the first connecting conductor can be located in different layout layers.
In some embodiments, as shown in fig. 5b, the spacing between adjacent first resistor unit segments 111 along the second direction is a first width W1; the distance between the first resistor array 11 and the second resistor array 12 in the second direction is a second width W2; the distance between adjacent second resistance unit segments 121 along the second direction is a third width W3; the first width W1, the second width W2, and the third width W3 are equal. Due to the edge process effect, theories and experiments show that when the distance between the first resistor array 11 and the second resistor array 12 in the second direction is equal to the distance between the first resistor unit segments in the second direction, the protection effect of the second resistor array is better than that when the distances are not equal, namely W2= W1; when the distance between the adjacent second resistor unit segments 121 in the second direction is equal to the distance between the adjacent first resistor unit segments in the second direction, the protection effect of the second resistor array is better than that when the distances are not equal, that is, W3= W1; the best technical effect is when the first width, the second width and the third width are equal, i.e. W3= W2= W1.
In some embodiments, referring to fig. 5c, after setting the second resistor array layout, the method further comprises: providing a plurality of third connecting conductors 124, each third connecting conductor 124 electrically connecting two second contact vias 122 located on the same second resistive unit segment 121; a fourth connecting conductor 125 is provided, and the second resistor array 12 layout is connected to the ground line 126 through the fourth connecting conductor 125. The layout layer of the third connecting conductor, the layout layer of the fourth connecting conductor and the layout layer of the second connecting conductor may be the same.
In some embodiments, referring to fig. 5 d-5 f, after the fourth connection conductor 125 is provided, the method further comprises: arranging a fifth connecting conductor 128, wherein the fifth connecting conductor 128 is connected with the first resistor array 11 layout and the second resistor array 12 layout; removing part of the second connecting conductor 123, so that the layout of the second resistor array 12 is decomposed into a practical layout of the second resistor array 14 and a dummy layout of the second resistor array 15, and the practical layout of the second resistor array 14 is connected with the layout of the first resistor array 11 through a fifth connecting conductor 128; the third connecting conductor 124 located within the layout of the utility second resistor array 14 is removed. The layout layer of the fifth connecting conductor and the layout layer of the second connecting conductor may be the same.
Specifically, referring to fig. 5d, a fifth connecting conductor 128 is provided, and the fifth connecting conductor 128 connects the layout of the first resistor array 11 and the layout of the second resistor array 12.
Next, referring to fig. 5e, a portion of the second connection conductor 123 is removed, so that the second resistor array 12 layout is decomposed into a utility second resistor array 14 layout and a dummy second resistor array 15 layout, and the utility second resistor array 14 layout is connected to the first resistor array 11 layout through the fifth connection conductor 128.
Then, referring to fig. 5f, the third connection conductor 124 located within the layout of the utility second resistor array 14 is removed.
The resistance value of the first resistor array in the original layout group is the expected resistance value designed in the analog circuit. As shown in fig. 5, taking 6 first resistor unit segments connected in series as an example, the first resistor array 11 includes 6 first resistor unit segments 111 extending along the first direction and arranged along the second direction, and the resistance of the first resistor array is 6R1.
But after actual testing, the resistance value of the resistor may need to be changed. For example, when an ECO (Engineering Change Order) circuit is modified, a resistance value needs to be changed, that is, a resistance layout needs to be redesigned, so that design time is wasted, and project schedule is affected.
As shown in fig. 5a-5f, by providing a fifth connection conductor, parts of the second connection conductor and the third connection conductor are removed, so that parts of the second resistor unit segment are connected to the first resistor array layout. Take 6 first resistor unit segments and 3 second resistor unit segments respectively disposed on two sides of the first resistor array as an example. The resistance value of the first resistance unit section is R1, and the resistance value of the second resistance unit section is R2. The desired resistance is 6R1, and the modified resistance is 6R1+4R2, and in general, R1 is equal to R2, i.e. the modified resistance is 10R1. It should be appreciated that, taking the chain series resistor as an example, the input and output of the test signal are correspondingly shifted to the second resistor unit segment at the edge in the practical second resistor array layout.
In some embodiments, the dummy second resistor array layouts located on both sides of the first resistor array layout are symmetric with respect to the first resistor array layout. Therefore, the second resistor unit segments positioned at two sides of the first resistor array layout are used while the second resistor unit segments are symmetrical, and the reliability of the resistor can be improved.
In some embodiments, referring to fig. 2, after the second resistor array layout is set, the method further comprises: dummy resistors 127 are provided, the dummy resistors 127 being located outside the layout of the second resistor array 12 in the second direction, the dummy resistors 127 extending in the first direction and being parallel to the second resistor unit segments 121. The pitch of the second resistor array 12 layout and the dummy resistors 127 in the second direction is a fourth width W4, and the fourth width W4 is equal to the third width W3. In this manner, the dummy resistor may further enable the process environment of the second resistor unit segment at the edge to be consistent with the process environment of the other second resistor unit segments. Therefore, all the second resistance unit sections can be used as standby trimming resistors of the first resistance unit sections. In general, the layout layer of the dummy resistor is the same as the layout layer of the second resistor unit segment; under specific process conditions, the two can also be located in different plate layers.
According to the layout design method provided by the invention, the second resistor unit segment in the second resistor array layout can be directly utilized, and the connecting line is changed to connect part of the second resistor unit segment with the first resistor array layout, so that the resistance value of the original layout group is modified, the resistor layout design time can be reduced, the layout design efficiency is improved, the ECO progress is accelerated, and the cost is saved.
The embodiment of the invention also provides a semiconductor structure which comprises the resistor layout or is formed by preparing the resistor layout. According to the resistor layout provided by the invention, the second resistor array is arranged at the periphery of the first resistor array. Thus, the semiconductor structure (such as a resistor) prepared and formed by using the resistor layout is less influenced by the process in the manufacturing process. The performance, reliability and precision of the semiconductor structure prepared by the method are improved.
In summary, in the embodiments of the present invention, the second resistor array is disposed at the periphery of the first resistor array, so that the environment of the first resistor unit segment at the edge in the first resistor array is the same as the environment of the other first resistor unit segments, thereby improving the resistor accuracy. And the first resistance unit section at the edge is far away from the process processing edge, so that the finally obtained expected resistance is less influenced by the process in the manufacturing process, and the precision and reliability of the resistance are improved. Meanwhile, the influence of noise on the first resistance unit section located at the edge can be reduced. The second resistor array not only improves the resistance value precision of the first resistor array, but also provides a spare second resistor unit section for correcting the resistance value of the first resistor array.
For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof.
It is further noted that, herein, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

Claims (12)

1. A resistance layout, comprising:
a first resistive array (11) and a second resistive array (12);
the first resistor array (11) comprises a plurality of first resistor unit segments (111) extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect;
the second resistor array (12) comprises a plurality of second resistor unit segments (121) which extend along a first direction and are arranged along a second direction; wherein the content of the first and second substances,
the second resistor array (12) is located outside the first resistor array (11) in a second direction.
2. The resistive layout of claim 1,
the second resistor arrays (12) are respectively positioned at two opposite sides of the first resistor array (11) in the second direction.
3. The resistive layout according to claim 1 or 2, further comprising:
a plurality of first contact vias (112), the first resistance unit segment (111) being provided with the first contact vias (112) in a first direction, the first contact vias (112) being electrically connected with the first resistance unit segment (111);
a plurality of first connection conductors (113), the first connection conductors (113) being electrically connected to the first contact vias (112) located on different first resistance unit segments (111), respectively;
a plurality of second contact vias (122), the second resistance unit segment (121) being provided with the second contact vias (122) along a first direction, the second contact vias (122) being electrically connected with the second resistance unit segment (121);
and a plurality of second connecting conductors (123), wherein the second connecting conductors (123) are respectively electrically connected with the second contact vias (122) on different second resistance unit sections (121).
4. The resistive layout of claim 3, further comprising:
a plurality of third connecting conductors (124), each of the third connecting conductors (124) electrically connecting two of the second contact vias (122) located on the same second resistive unit segment (121);
a fourth connection conductor (125), through which the second resistor array (12) is connected to ground (126).
5. The resistive layout according to claim 1 or 2,
the distance between adjacent first resistance unit segments (111) along the second direction is a first width;
the distance between the first resistor array (11) and the second resistor array (12) along the second direction is a second width;
the distance between adjacent second resistance unit segments (121) along the second direction is a third width; wherein the content of the first and second substances,
the first width, the second width, and the third width are equal.
6. The resistive layout of claim 1 or 2, further comprising:
a dummy resistor (127), the dummy resistor (127) located outside the second resistor array (12) in the second direction, the dummy resistor (127) extending in the first direction and parallel to the second resistor unit segment (121).
7. The resistive layout according to claim 1 or 2, further comprising:
a third resistor array (13), wherein the third resistor array (13) comprises a plurality of third resistor unit segments (131) extending along the first direction and arranged along the second direction; wherein the content of the first and second substances,
the third resistor arrays (13) are respectively positioned at two opposite sides of the first resistor array (11) in the first direction.
8. A method for designing a resistor layout is characterized by comprising the following steps:
step S1: obtaining an original resistor layout group (10), wherein the original resistor layout group (10) comprises a first resistor array (11) layout, the first resistor array (11) layout comprises a plurality of first resistor unit segments (111) which extend along a first direction and are arranged along a second direction, and the first direction and the second direction are intersected;
step S2: and arranging a second resistor array (12) layout, wherein the second resistor array (12) layout is positioned at the outer side of the first resistor array (11) layout in the second direction, and the second resistor array (12) layout comprises a plurality of second resistor unit segments (121) which extend along the first direction and are arranged along the second direction.
9. The design method according to claim 8,
in the step S1, the layout of the first resistor array (11) is further provided with:
a plurality of first contact vias (112), the first resistance unit segment (111) being provided with the first contact vias (112) in a first direction, the first contact vias (112) being electrically connected with the first resistance unit segment (111);
a plurality of first connection conductors (113), the first connection conductors (113) being electrically connected to the first contact vias (112) located on different first resistance unit segments (111), respectively;
in the step S2, the layout of the second resistor array (12) is further provided with:
a plurality of second contact via holes (122), the second resistance unit segment (121) being provided with the second contact via holes (122) in a first direction, the second contact via holes (122) being electrically connected to the second resistance unit segment (121);
and a plurality of second connecting conductors (123), wherein the second connecting conductors (123) are respectively and electrically connected with the second contact vias (122) on different second resistance unit sections (121).
10. The design method according to claim 9, wherein after setting the layout of the second resistor array (12), the method further comprises:
a plurality of third connecting conductors (124) are arranged, and each third connecting conductor (124) is electrically connected with two second contact guide holes (122) on the same second resistance unit section (121);
and a fourth connecting conductor (125) is arranged, and the layout of the second resistor array (12) is connected with the ground wire (126) through the fourth connecting conductor (125).
11. The design method according to claim 10, characterized in that after providing the fourth connection conductor (125), the method further comprises:
-providing a fifth connecting conductor (128), said fifth connecting conductor (128) connecting said first resistor array (11) layout and said second resistor array (12) layout;
removing part of the second connecting conductor (123) so that the second resistor array (12) is decomposed into a practical second resistor array (14) layout and a dummy second resistor array (15) layout, wherein the practical second resistor array (14) layout is connected with the first resistor array (11) layout through a fifth connecting conductor (128);
removing a third connecting conductor (124) located within the utility second resistor array (12).
12. A semiconductor structure comprising a resistive layout according to any one of claims 1 to 7, or prepared using said resistive layout.
CN202211163913.6A 2022-09-23 2022-09-23 Resistor layout, design method thereof and semiconductor structure Pending CN115483207A (en)

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CN202211163913.6A CN115483207A (en) 2022-09-23 2022-09-23 Resistor layout, design method thereof and semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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CN115483207A true CN115483207A (en) 2022-12-16

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