CN115483093A - Method for manufacturing metal grid - Google Patents
Method for manufacturing metal grid Download PDFInfo
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- CN115483093A CN115483093A CN202211049689.8A CN202211049689A CN115483093A CN 115483093 A CN115483093 A CN 115483093A CN 202211049689 A CN202211049689 A CN 202211049689A CN 115483093 A CN115483093 A CN 115483093A
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- 239000002184 metal Substances 0.000 title claims abstract description 162
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 342
- 229920002120 photoresistant polymer Polymers 0.000 claims description 49
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 239000011248 coating agent Substances 0.000 claims description 30
- 238000000576 coating method Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 19
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 10
- 229910010038 TiAl Inorganic materials 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- 239000007864 aqueous solution Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000243 solution Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 239000006117 anti-reflective coating Substances 0.000 description 17
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a manufacturing method of a metal gate, which comprises the following steps: and step one, completing a polycrystalline silicon pseudo gate removing process. And step two, forming a zero layer TaN layer. And step three, forming a P-type work function metal layer and a first TaN layer. And fourthly, carrying out first-time patterning etching to sequentially remove the first TaN layer and the P-type work function metal layer in the NMOS forming area. And step five, forming an N-type work function metal layer and a second TaN layer. And sixthly, carrying out second patterning etching to sequentially remove the second TaN layer and the N-type work function metal layer in the PMOS forming region. And seventhly, carrying out third patterned etching to remove the second TaN layer in the NMOS forming area. Step eight, forming a top barrier layer. And step nine, forming a metal conductive material layer to completely fill the grid groove and carrying out planarization. The invention can remove the N-type work function metal layer in the forming area of the PMOS, can simultaneously increase the barrier effect on metal diffusion in the forming area of the PMOS, and can improve the performance of the device.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a Metal Gate (MG).
Background
As shown in fig. 1, it is a schematic view of a device structure formed by a conventional metal gate manufacturing method; the manufacturing method of the existing metal gate comprises the following steps:
and step one, completing a polycrystalline silicon pseudo gate removal process and forming a gate trench, wherein the top surface of the gate trench is flush with the top surface of the zero interlayer film 105. In fig. 1, the zero-level interlayer film 105 is also denoted by ILD OX.
Usually, a gate dielectric layer is also formed between the polysilicon dummy gate and the semiconductor substrate 103. The gate dielectric layer is formed before the formation of the polysilicon dummy gate and is retained after the removal of the polysilicon dummy gate.
The semiconductor substrate 103 is typically a silicon (Si) substrate.
The gate dielectric layer is sequentially overlapped with an interface layer 106 (IL) and a high dielectric constant layer 107 (HK), and a zeroth TiN layer 108 is further formed on the surface of the high dielectric constant layer 107. The whole gate structure formed finally is a high dielectric constant metal gate, namely HKMG.
An interface layer 106 is formed between the high dielectric constant layer 107 and the semiconductor substrate 103.
In fig. 1, an NMOS and a PMOS are simultaneously integrated on the semiconductor substrate 103, where the region 101 is an NMOS formation region 101 and the region 102 is a PMOS formation region 102.
A sidewall 104 is further formed on the side surface of the polysilicon dummy gate, and the sidewall 104 is usually made of silicon nitride, so the sidewall 104 is also denoted by SIN SPW in fig. 1.
And step two, forming a zero layer TaN layer 109, wherein the zero layer TaN layer 109 covers the bottom surface and the side surface of the gate trench and the surface outside the gate trench.
The bottom barrier layer is formed by overlapping the zeroth TiN layer 108 and a subsequently formed zeroth TaN layer 109.
And step three, forming a P-type work function metal layer 110 on the surface of the zero-layer TaN layer 109.
Generally, tiN is used as the material of the P-type work function metal layer 110. In fig. 1, the P-type work function metal layer 110 is also represented by TiN.
And step four, carrying out patterned etching to remove the P-type work function metal layer 110 in the formation region 101 of the NMOS.
And step five, forming the N-type work function metal layer 111.
Generally, tiAl is used as the material of the N-type work function metal layer 111. In fig. 1, the N-type work function metal layer 111 is also represented by TiAl.
And sixthly, forming a top barrier layer, wherein the top barrier layer is formed by superposing a TiN layer 111 and a Ti layer 112.
And seventhly, forming a metal conductive material layer 114 and flattening.
Generally, al is used as the material of the metal conductive material layer 114. In fig. 1, the metallic conductive material layer 114 is also denoted by Al.
As shown in fig. 1, in the gate structure of the PMOS device, the top surface of the P-type work function metal layer 111 is the N-type work function metal layer 111 made of TiAl, and the metal conductive material layer 114 is also made of Al, so that a defect that Al diffuses into the P-type work function metal layer 111 is easily generated, and the performance of the device is finally affected.
In the conventional improvement method, even if the N-type work function metal layer 111 in the middle of the PMOS formation region 101b is removed, the adverse effect of Al diffusion of the N-type work function metal layer 111 on the P-type work function metal layer 111 cannot be completely avoided during the formation process.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for manufacturing a metal gate, which can remove an N-type work function metal layer in a forming area of a PMOS and can simultaneously increase the barrier effect of metal of a metal conductive material layer to diffusion of a P-type work function metal layer in the forming area of the PMOS, thereby improving the performance of a device.
In order to solve the above technical problem, the method for manufacturing a metal gate provided by the present invention comprises the following steps:
and step one, completing a polycrystalline silicon pseudo gate removal process and forming a gate groove, wherein the top surface of the gate groove is level to the top surface of the zero layer interlayer film.
And step two, forming a zero layer TaN layer, wherein the zero layer TaN layer covers the bottom surface and the side surface of the grid groove and the surface outside the grid groove, and the zero layer TaN layer is used as a component of the bottom barrier layer.
And step three, sequentially forming a P-type work function metal layer and a first TaN layer on the surface of the zero TaN layer.
And fourthly, carrying out first-time graphic etching to sequentially remove the first TaN layer and the P-type work function metal layer in the NMOS forming area, and reserving the first TaN layer and the P-type work function metal layer in the PMOS forming area.
In the first patterning etching, the etching of the P-type work function metal layer is stopped on the surface of the zero-layer TaN layer, and the first layer TaN layer is used for protecting the reserved P-type work function metal layer.
And step five, sequentially forming an N-type work function metal layer and a second TaN layer.
In the formation region of the NMOS, the N-type work function metal layer is formed on the surface of the zero TaN layer.
In the formation region of the PMOS, the N-type work function metal layer is formed on the surface of the first TaN layer.
And sixthly, carrying out second patterning etching to sequentially remove the second TaN layer and the N-type work function metal layer in the forming area of the PMOS, and reserving the second TaN layer and the N-type work function metal layer in the forming area of the NMOS.
In the second patterning etching, the etching of the N-type work function metal layer is stopped on the surface of the first TaN layer, and the second TaN layer is used for protecting the reserved N-type work function metal layer.
And seventhly, carrying out third patterned etching to remove the second TaN layer in the NMOS forming area.
Step eight, forming a top barrier layer.
And step nine, forming a metal conductive material layer to completely fill the grid groove and carrying out planarization.
In a further improvement, in the first step, a gate dielectric layer is further formed between the polycrystalline silicon dummy gate and the semiconductor substrate, and after the polycrystalline silicon dummy gate is removed, the bottom surface of the gate trench is the top surface of the gate dielectric layer.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the gate dielectric layer comprises a high dielectric constant layer.
A further improvement is the formation of an interface layer between the high dielectric constant layer and the semiconductor substrate.
In a further improvement, a zeroth TiN layer is further formed between the high-dielectric-constant layer and the zeroth TaN layer, and the bottom barrier layer is formed by laminating the zeroth TiN layer and the zeroth TaN layer.
In a further improvement, in the third step, the material of the P-type work function metal layer includes TiN.
In a further improvement, the first patterned etching in the fourth step includes the following sub-steps:
and 41, coating a first layer of anti-reflection coating, wherein the gate trench is completely filled and extends to the surface outside the gate trench by the first layer of anti-reflection coating.
And 42, forming a first layer of photoresist on the surface of the first layer of anti-reflection coating.
And 43, carrying out a first photoetching process to form a first layer of photoresist pattern, wherein the first layer of photoresist pattern opens the forming area of the NMOS and covers the forming area of the PMOS.
And 44, etching the first anti-reflection coating by taking the first photoresist pattern as a mask and removing the first anti-reflection coating in the opening area.
And step 45, etching the first TaN layer by taking the first photoresist pattern as a mask, and removing the first TaN layer in the opening area.
And step 46, etching the P-type work function metal layer by taking the first layer of photoresist pattern as a mask, and removing the P-type work function metal layer in the opening area.
And 47, removing the residual first photoresist pattern and the first anti-reflection coating.
In a further improvement, in step 45, the first TaN layer is etched by dry etching.
In a further improvement, in step 46, wet etching is used to etch the P-type work function metal layer and stop on the surface of the zero-layer TaN layer.
In a further improvement, in the fifth step, the material of the N-type work function metal layer includes TiAl.
In a further improvement, the second patterned etching in the sixth step includes the following sub-steps:
and 61, coating a second anti-reflection coating, wherein the second anti-reflection coating completely fills the gate trench and extends to the surface outside the gate trench.
And step 62, forming a second layer of photoresist on the surface of the second layer of anti-reflection coating.
And 63, carrying out a second photoetching process to form a second layer of photoresist pattern, wherein the second layer of photoresist pattern opens the forming area of the PMOS and covers the forming area of the NMOS.
And step 64, etching the second anti-reflection coating by taking the second photoresist pattern as a mask and removing the second anti-reflection coating in the opening area.
And step 65, etching the second TaN layer by taking the second layer of photoresist pattern as a mask, and removing the second TaN layer in the open area.
And 66, etching the N-type work function metal layer by taking the second layer of photoresist pattern as a mask and removing the N-type work function metal layer in the opening area.
And 67, removing the residual second photoresist pattern and the second anti-reflection coating.
In a further improvement, in step 65, the second TaN layer is etched by dry etching.
In a further improvement, in step 66, wet etching is used to etch the N-type work function metal layer and stop on the upper surface of the first TaN layer surface.
In a further improvement, in step 46, an aqueous solution containing hydrochloric acid and hydrogen peroxide is used for the etching solution for wet etching of the P-type work function metal layer.
In a further improvement, in step 66, an aqueous solution containing ammonia water and hydrogen peroxide is used for the etching solution for the wet etching of the N-type work function metal layer.
In a further improvement, in the eighth step, the material of the top barrier layer includes TiN.
In a further improvement, in the ninth step, the material of the metal conductive material layer includes Al.
Compared with the prior art that only one grid replacement process is carried out so that an N-type work function metal layer such as TiAl can be kept in a forming area of a PMOS (P-channel metal oxide semiconductor), the method is characterized in that a TaN layer is formed after the P-type work function metal layer and the N-type work function metal layer are formed, and then a corresponding graphical etching process is added; meanwhile, the first TaN layer on the top of the P-type work function metal layer can finally increase the barrier effect on the diffusion of metal such as Al of the metal conductive material layer to the P-type work function metal layer, so that the performance of the device can be improved.
In the invention, when the P-type work function metal layer is etched and the N-type work function metal layer is etched, the TaN layers are arranged on the P-type work function metal layer and the N-type work function metal layer outside the etching area for protection, so that the performance of the device can be further improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a device structure formed by a conventional method for manufacturing a metal gate;
FIG. 2 is a flow chart of a method of fabricating a metal gate in accordance with an embodiment of the present invention;
fig. 3A to fig. 3W are schematic device structures in steps of a method for manufacturing a metal gate according to an embodiment of the present invention.
Detailed Description
Fig. 2 is a flow chart of a method for manufacturing a metal gate according to an embodiment of the present invention; fig. 3A to 3W are schematic device structure diagrams in steps of a method for manufacturing a metal gate according to an embodiment of the present invention; the manufacturing method of the metal gate comprises the following steps:
step one, as shown in fig. 3A, the polysilicon dummy gate removal process is completed and a gate trench 208 is formed, where a top surface of the gate trench 208 is flush with a top surface of the zero interlayer film 207.
In the embodiment of the present invention, a gate dielectric layer 301 is further formed between the polysilicon dummy gate and the semiconductor substrate 203, and after the polysilicon dummy gate is removed, the bottom surface of the gate trench 208 is the top surface of the gate dielectric layer 301.
In some preferred embodiments, the semiconductor substrate 203 comprises a silicon substrate.
The gate dielectric layer 301 includes a high dielectric constant layer. The whole gate structure is a high dielectric constant metal gate, namely HKMG.
An interface layer is formed between the high dielectric constant layer and the semiconductor substrate 203.
A zeroth TiN layer is also formed between the high dielectric constant layer and the zeroth TaN layer 302. The bottom barrier layer is formed by overlapping the zeroth TiN layer and a subsequently formed zeroth TaN layer 302.
A field oxide 204 is further formed on the semiconductor substrate 203, and the field oxide 204 isolates an active region on the semiconductor substrate 203.
The NMOS and PMOS are integrated on the semiconductor substrate 203, and the semiconductor substrate 203 is further divided into a core (core) region and an input/output (IO) region. The NMOS and the PMOS which are positioned in the core area are respectively a core NMOS and a core PMOS, and the NMOS and the PMOS which are positioned in the IO area are respectively an IO NMOS and an IO PMOS. In fig. 3A, a region 201a is a region for forming a core NMOS, a region 202a is a region for forming a core PMOS, a region 201b is a region for forming an IO NMOS, and a region 202b is a region for forming an IO PMOS. The size of the IO NMOS and IO PMOS may be larger than the size of the core NMOS and core PMOS.
An embedded silicon germanium epitaxial layer 209 is also formed in the source and drain regions of the core PMOS.
And a side wall 205 is also formed on the side surface of the polycrystalline silicon pseudo gate.
A Contact Etch Stop Layer (CESL) 206 covers the top surface, the side surfaces and the outer surface of the polysilicon dummy gate, and the zeroth interlayer film 207 is formed on the surface of the contact etch stop layer 206. Before removing the polysilicon dummy gate, a chemical mechanical polishing or etching back process is required to remove both the contact etching stop layer 206 and the zero-layer interlayer film 207 on the top surface of the polysilicon dummy gate, so that the top surface of the polysilicon dummy gate is exposed and is flush with the top surfaces of the contact etching stop layer 206 and the zero-layer interlayer film 207 outside the polysilicon.
Step two, as shown in fig. 3B, a zero-layer TaN layer 302 is formed, wherein the zero-layer TaN layer 302 covers the bottom surface and the side surface of the gate trench 208 and the surface outside the gate trench 208, and the zero-layer TaN layer 302 is used as a component of the bottom barrier layer.
And step three, as shown in fig. 3C, forming a P-type work function metal layer 303 on the surface of the zero TaN layer 302.
As shown in fig. 3D, a first TaN layer 304 is formed on the surface of the P-type work function metal layer 303.
In an embodiment of the present invention, the material of the P-type work function metal layer 303 includes TiN.
And step four, as shown in fig. 3I, performing a first patterning etching to sequentially remove the first TaN layer 304 and the P-type work function metal layer 303 in the formation region of the NMOS, and leaving the first TaN layer 304 and the P-type work function metal layer 303 in the formation region of the PMOS. The NMOS formation region includes a core NMOS formation region 201a and an IO NMOS formation region 201b. The PMOS formation region includes a core PMOS formation region 202a and an IO PMOS formation region 202b.
In the first patterning etching, the etching of the P-type work function metal layer 303 is stopped on the surface of the zero-layer TaN layer 302, and the first TaN layer 304 is used for protecting the remaining P-type work function metal layer 303.
In the embodiment of the present invention, the first patterned etching in the fourth step includes the following sub-steps:
step 41, as shown in fig. 3E, a first anti-reflective coating 401 is applied, and the first anti-reflective coating 401 completely fills and extends the gate trench 208 to the surface outside the gate trench 208.
Step 42, as shown in fig. 3E, a first layer of photoresist 402 is formed on the surface of the first anti-reflective coating 401.
Step 43, as shown in fig. 3E, a first photolithography process is performed to form a first photoresist 402 pattern, where the first photoresist 402 pattern opens the NMOS formation region and covers the PMOS formation region.
Step 44, as shown in fig. 3F, the first anti-reflective coating 401 is etched by using the first photoresist 402 pattern as a mask, and the first anti-reflective coating 401 is removed in the open area.
Step 45, as shown in fig. 3G, the first TaN layer 304 is etched by using the first photoresist 402 pattern as a mask, and the first TaN layer 304 is removed in the open area.
In some preferred embodiments, the first TaN layer 304 is etched by dry etching.
Step 46, as shown in fig. 3H, the P-type work function metal layer 303 is etched by using the first photoresist 402 pattern as a mask, and the P-type work function metal layer 303 in the opening area is removed.
In some preferred embodiments, the P-type work function metal layer 303 is etched by wet etching and stops on the surface of the zero-level TaN layer 302. And adopting an aqueous solution containing hydrochloric acid and hydrogen peroxide as an etching solution for wet etching of the P-type work function metal layer 303.
Step 47, as shown in fig. 3I, the remaining first photoresist 402 pattern and the first anti-reflective coating 401 are removed. In some embodiments, the first photoresist 402 pattern and the first anti-reflective coating 401 are removed using an ashing (asher) process.
And step five, as shown in fig. 3J, forming an N-type work function metal layer 305.
As shown in fig. 3K, a second TaN layer 306 is formed on the surface of the N-type work function metal layer 305.
In the formation region of the NMOS, the N-type work function metal layer 305 is formed on the surface of the zero-layer TaN layer 302.
In the formation region of the PMOS, the N-type work function metal layer 305 is formed on the surface of the first TaN layer 304.
In an embodiment of the present invention, the material of the N-type work function metal layer 305 includes TiAl.
And sixthly, as shown in fig. 3P, performing second patterning etching to sequentially remove the second TaN layer 306 and the N-type work function metal layer 305 in the PMOS formation region, and leaving the second TaN layer 306 and the N-type work function metal layer 305 in the NMOS formation region.
In the second patterning etching, the etching of the N-type work function metal layer 305 is stopped on the surface of the first TaN layer 304, and the second TaN layer 306 is used for protecting the remaining N-type work function metal layer 305.
In the embodiment of the present invention, the second patterned etching in the sixth step includes the following sub-steps:
step 61, as shown in fig. 3L, a second anti-reflective coating 403 is applied, and the second anti-reflective coating 403 completely fills and extends the gate trench 208 to the surface outside the gate trench 208.
Step 62, as shown in fig. 3L, a second photoresist layer 404 is formed on the surface of the second anti-reflective coating 403.
Step 63, as shown in fig. 3L, a second photolithography process is performed to form a second layer of photoresist 404 pattern, where the second layer of photoresist 404 pattern opens the PMOS formation region and covers the NMOS formation region.
Step 64, as shown in fig. 3M, the second layer of anti-reflection coating 403 is etched by using the pattern of the second layer of photoresist 404 as a mask, and the second layer of anti-reflection coating 403 in the open area is removed.
Step 65, as shown in fig. 3N, the second TaN layer 306 is etched by using the second photoresist layer 404 pattern as a mask, and the second TaN layer 306 is removed in the open area.
In some preferred embodiments, the second TaN layer 306 is etched by dry etching.
Step 66, as shown in fig. 3O, etching the N-type work function metal layer 305 with the second layer of photoresist 404 pattern as a mask, and removing all the N-type work function metal layer 305 in the open area.
In some preferred embodiments, the N-type work function metal layer 305 is etched by wet etching and stops on the upper surface of the first TaN layer 304. The etching solution for wet etching of the N-type work function metal layer 305 adopts an aqueous solution containing ammonia water and hydrogen peroxide.
Step 67, as shown in fig. 3P, removing the remaining second photoresist 404 pattern and the second anti-reflective coating 403.
Seventhly, as shown in fig. 3T, a third patterned etching is performed to remove the second TaN layer 306 in the formation region of the NMOS.
In the embodiment of the present invention, the third patterned etching in the seventh step includes the following sub-steps:
step 71, as shown in fig. 3Q, a third layer of anti-reflective coating 405 is applied, and the third layer of anti-reflective coating 405 completely fills and extends the gate trench 208 to the surface outside the gate trench 208.
Step 72, as shown in fig. 3Q, a third layer of photoresist 406 is formed on the surface of the third layer of anti-reflective coating 405.
Step 73, as shown in fig. 3Q, a second photolithography process is performed to form a third layer of photoresist 406 pattern, where the third layer of photoresist 406 pattern opens the formation region of the NMOS and covers the formation region of the PMOS.
Step 74, as shown in fig. 3R, the third layer of anti-reflective coating 405 is etched by using the third layer of photoresist 406 as a mask, and the third layer of anti-reflective coating 405 is removed in the open area.
Step 75, as shown in fig. 3S, the second TaN layer 306 is etched by using the third photoresist layer 406 pattern as a mask, and the second TaN layer 306 is removed in the open area.
Step 76, as shown in FIG. 3T, the remaining third layer of photoresist 406 pattern and the third layer of anti-reflective coating 405 are removed.
Step eight, as shown in fig. 3U, a top barrier layer 307 is formed.
In an embodiment of the present invention, the material of the top barrier layer 307 comprises TiN.
Step nine, as shown in fig. 3V, a metal conductive material layer 308 is formed to completely fill the gate trench 208 and extend to the surface outside the gate trench 208.
As shown in fig. 3W, planarization is performed by using a chemical mechanical polishing process, the chemical mechanical polishing process is stopped on the zero interlayer film 207, and after planarization, the metal conductive material layer 308 is filled only in the gate trench 208 and is even with the top surface of the zero interlayer film 207.
In an embodiment of the present invention, the material of the metal conductive material layer 308 includes Al.
Different from the existing method in which only one gate replacement process is performed so that the N-type work function metal layer 305 such as TiAl remains in the formation region of the PMOS, in the embodiment of the present invention, a TaN layer is formed once after the P-type work function metal layer 303 and the N-type work function metal layer 305 are formed, and then a corresponding patterned etching process is added, the N-type work function metal layer 305 in the formation region of the PMOS can be removed by using the three patterned etching processes in the embodiment of the present invention, so that the P-type work function metal layer 303 in the formation region of the PMOS is not affected by metal diffusion of the N-type work function metal layer 305; meanwhile, the first TaN layer 304 on top of the P-type work function metal layer 303 can finally increase the barrier effect on the diffusion of the metal, such as Al, of the metal conductive material layer 308 to the P-type work function metal layer 303, so that the performance of the device can be improved.
In the embodiment of the invention, when the P-type work function metal layer 303 is etched and the N-type work function metal layer 305 is etched, the TaN layer is used for protecting the P-type work function metal layer 303 and the N-type work function metal layer 305 outside an etching area, so that the performance of a device can be further improved.
The present invention has been described in detail with reference to the specific examples, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (18)
1. A method for manufacturing a metal gate is characterized by comprising the following steps:
step one, completing a polycrystalline silicon pseudo gate removal process and forming a gate trench, wherein the top surface of the gate trench is flush with the top surface of the zero-layer interlayer film;
forming a zero-layer TaN layer, wherein the zero-layer TaN layer covers the bottom surface and the side surface of the grid groove and the surface outside the grid groove, and is used as a component of the bottom barrier layer;
sequentially forming a P-type work function metal layer and a first TaN layer on the surface of the zero TaN layer;
step four, carrying out first-time graphic etching to sequentially remove the first TaN layer and the P-type work function metal layer in the formation region of the NMOS, and reserving the first TaN layer and the P-type work function metal layer in the formation region of the PMOS;
in the first patterning etching, the etching of the P-type work function metal layer is stopped on the surface of the zero-layer TaN layer, and the first layer TaN layer is used for protecting the reserved P-type work function metal layer;
step five, forming an N-type work function metal layer and a second TaN layer in sequence;
in the formation region of the NMOS, the N-type work function metal layer is formed on the surface of the zero-layer TaN layer;
in the formation region of the PMOS, the N-type work function metal layer is formed on the surface of the first TaN layer;
sixthly, carrying out second patterning etching to sequentially remove the second TaN layer and the N-type work function metal layer in the PMOS forming area, and reserving the second TaN layer and the N-type work function metal layer in the NMOS forming area;
in the second graphical etching, the etching of the N-type work function metal layer is stopped on the surface of the first TaN layer, and the second TaN layer is used for protecting the reserved N-type work function metal layer;
seventhly, carrying out third patterned etching to remove the second TaN layer in the NMOS forming area;
step eight, forming a top barrier layer;
and step nine, forming a metal conductive material layer to completely fill the grid groove and carrying out planarization.
2. A method of manufacturing a metal gate as claimed in claim 1, wherein: in the first step, a gate dielectric layer is further formed between the polycrystalline silicon dummy gate and the semiconductor substrate, and after the polycrystalline silicon dummy gate is removed, the bottom surface of the gate groove is the top surface of the gate dielectric layer.
3. A method of manufacturing a metal gate as claimed in claim 2, wherein: the semiconductor substrate includes a silicon substrate.
4. A method of manufacturing a metal gate as claimed in claim 2, wherein: the gate dielectric layer includes a high dielectric constant layer.
5. A method of manufacturing a metal gate as claimed in claim 4, wherein: an interface layer is formed between the high dielectric constant layer and the semiconductor substrate.
6. A method of manufacturing a metal gate as claimed in claim 5, wherein: and a zero TiN layer is also formed between the high dielectric constant layer and the zero TaN layer, and the bottom barrier layer is formed by laminating the zero TiN layer and the zero TaN layer.
7. A method of manufacturing a metal gate as claimed in claim 1, wherein: in the third step, the material of the P-type work function metal layer comprises TiN.
8. A method for manufacturing a metal gate as claimed in claim 1 or 7, wherein the first patterned etching of step four comprises the sub-steps of:
step 41, coating a first layer of anti-reflection coating, wherein the gate trench is completely filled and extends to the surface outside the gate trench by the first layer of anti-reflection coating;
step 42, forming a first layer of photoresist on the surface of the first layer of anti-reflection coating;
43, carrying out a first photoetching process to form a first layer of photoresist pattern, wherein the first layer of photoresist pattern opens the forming area of the NMOS and covers the forming area of the PMOS;
step 44, etching the first anti-reflection coating by taking the first photoresist pattern as a mask and removing the first anti-reflection coating in an opening area;
step 45, etching the first TaN layer by taking the first photoresist pattern as a mask, and removing the first TaN layer in an open area;
step 46, etching the P-type work function metal layer by taking the first photoresist pattern as a mask and removing the P-type work function metal layer in an opening area;
and 47, removing the residual first photoresist pattern and the first anti-reflection coating.
9. A method of manufacturing a metal gate as claimed in claim 8, wherein: and step 45, etching the first TaN layer by adopting dry etching.
10. A method of manufacturing a metal gate as claimed in claim 8, wherein: and step 46, etching the P-type work function metal layer by adopting wet etching and stopping on the surface of the zero layer TaN layer.
11. A method of manufacturing a metal gate as claimed in claim 1, wherein: in the fifth step, the material of the N-type work function metal layer comprises TiAl.
12. A method for manufacturing a metal gate as claimed in claim 1 or 11, wherein the second patterned etching of step six comprises the sub-steps of:
step 61, coating a second layer of anti-reflection coating, wherein the second layer of anti-reflection coating completely fills the gate trench and extends to the surface outside the gate trench;
step 62, forming a second layer of photoresist on the surface of the second layer of anti-reflection coating;
step 63, carrying out a second photoetching process to form a second layer of photoresist pattern, wherein the second layer of photoresist pattern opens the forming area of the PMOS and covers the forming area of the NMOS;
step 64, etching the second anti-reflection coating by taking the second layer of photoresist pattern as a mask and removing the second anti-reflection coating in the opening area;
step 65, etching the second TaN layer by taking the second layer of photoresist pattern as a mask and removing the second TaN layer in the open area;
step 66, etching the N-type work function metal layer by taking the second layer of photoresist pattern as a mask and removing the N-type work function metal layer in an opening area;
and 67, removing the residual second photoresist pattern and the second anti-reflection coating.
13. A method of manufacturing a metal gate as claimed in claim 12, wherein: in step 65, the second TaN layer is etched by dry etching.
14. A method of manufacturing a metal gate as claimed in claim 12, wherein: and 66, etching the N-type work function metal layer by adopting wet etching and stopping on the upper surface of the first TaN layer surface.
15. A method of manufacturing a metal gate as claimed in claim 10, wherein: in step 46, an aqueous solution containing hydrochloric acid and hydrogen peroxide is used for the etching solution for wet etching of the P-type work function metal layer.
16. A method of manufacturing a metal gate as claimed in claim 14, wherein: and step 66, adopting an aqueous solution containing ammonia water and hydrogen peroxide to the etching solution for the wet etching of the N-type work function metal layer.
17. A method of manufacturing a metal gate as claimed in claim 1, wherein: in the eighth step, the material of the top barrier layer includes TiN.
18. A method of manufacturing a metal gate as claimed in claim 1, wherein: in step nine, the material of the metal conductive material layer comprises Al.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211049689.8A CN115483093A (en) | 2022-08-30 | 2022-08-30 | Method for manufacturing metal grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211049689.8A CN115483093A (en) | 2022-08-30 | 2022-08-30 | Method for manufacturing metal grid |
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| Publication Number | Publication Date |
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| CN115483093A true CN115483093A (en) | 2022-12-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211049689.8A Pending CN115483093A (en) | 2022-08-30 | 2022-08-30 | Method for manufacturing metal grid |
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| Country | Link |
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| CN (1) | CN115483093A (en) |
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- 2022-08-30 CN CN202211049689.8A patent/CN115483093A/en active Pending
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