CN115482780A - Pixel circuit, pixel driving method and display device - Google Patents

Pixel circuit, pixel driving method and display device Download PDF

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Publication number
CN115482780A
CN115482780A CN202211190607.1A CN202211190607A CN115482780A CN 115482780 A CN115482780 A CN 115482780A CN 202211190607 A CN202211190607 A CN 202211190607A CN 115482780 A CN115482780 A CN 115482780A
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CN
China
Prior art keywords
circuit
control
reset
light
driving circuit
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CN202211190607.1A
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Chinese (zh)
Inventor
李健
朱元章
田雪松
侯帅
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN202211190607.1A priority Critical patent/CN115482780A/en
Publication of CN115482780A publication Critical patent/CN115482780A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0666—Adjustment of display parameters for control of colour parameters, e.g. colour temperature

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a driving circuit, a first reset circuit and a second reset circuit; the first reset circuit supplies a first reset voltage to the first end of the drive circuit in a refresh frame and in a first time period; the second reset circuit provides a second reset voltage to the control end of the drive circuit in a second time period in a refresh frame; the first time period and the second time period are not overlapped or partially overlapped; the second reset circuit comprises a reset sub-circuit and a control sub-circuit; the reset sub-circuit provides a second reset voltage to the connection node under the control of a second reset control signal; the control sub-circuit controls the connection node to be communicated with the control end of the driving circuit under the control of the first scanning signal. The invention can improve VRR (VRR is frequency switching flicker, which shows that the brightness and the color coordinate are different before and after frequency switching).

Description

Pixel circuit, pixel driving method and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a pixel driving method, and a display device.
Background
In the related art, the negative deviation degree of Vth is greatly different after the display refresh frequency is switched, so that the problem that the brightness and the color coordinate are different before and after the display refresh frequency is switched occurs.
Disclosure of Invention
The invention mainly aims to provide a pixel circuit, a pixel driving method and a display device, and solves the problem that in the prior art, the negative deviation degree of Vth is large after the display refreshing frequency is switched, so that the brightness and the color coordinate before and after the display refreshing frequency is switched are different.
The embodiment of the invention provides a pixel circuit, which comprises a driving circuit, a first reset circuit and a second reset circuit, wherein the driving circuit comprises a first driving circuit, a second driving circuit and a first reset circuit;
the first reset circuit is respectively electrically connected with a first reset voltage end and the first end of the driving circuit and is used for providing a first reset voltage provided by the first reset voltage end to the first end of the driving circuit in a first time period in a refresh frame;
the second reset circuit is respectively electrically connected with a second reset voltage end and the control end of the driving circuit, and is used for providing a second reset voltage provided by the second reset voltage end to the control end of the driving circuit in a second time period in a refresh frame;
the first time period and the second time period are not overlapped or partially overlapped;
the second reset circuit comprises a reset sub-circuit and a control sub-circuit;
the reset sub-circuit is respectively electrically connected with a second reset control terminal, a first reset voltage terminal and a connecting node, and is used for providing a second reset voltage to the connecting node under the control of a second reset control signal provided by the second reset control terminal;
the control sub-circuit is respectively electrically connected with the first scanning end, the connection node and the control end of the driving circuit, and is used for controlling the connection node to be communicated with the control end of the driving circuit under the control of a first scanning signal provided by the first scanning end.
Optionally, the first reset circuit is further electrically connected to a first reset control terminal, and is configured to provide the first reset voltage to the first terminal of the driving circuit under the control of a first reset control signal provided by the first reset control terminal.
Optionally, in the refresh frame, the number of times that the first reset circuit supplies the first reset voltage to the first terminal of the driving circuit is greater than the number of times that the second reset circuit supplies the second reset voltage to the control terminal of the driving circuit.
Optionally, the first reset circuit includes a first transistor, the reset sub-circuit includes a second transistor, and the control sub-circuit includes a third transistor;
the control electrode of the first transistor is electrically connected with the first reset control end, the first electrode of the first transistor is electrically connected with the first reset voltage end, and the second electrode of the first transistor is electrically connected with the first end of the driving circuit;
a control electrode of the second transistor is electrically connected with the second reset control end, and a first electrode of the second transistor is electrically connected with the second reset voltage end;
a control electrode of the third transistor is electrically connected to the first scan terminal, a first electrode of the third transistor is electrically connected to a second electrode of the second transistor, and a second electrode of the third transistor is electrically connected to a control terminal of the driving circuit;
the driving circuit comprises a driving transistor;
the control electrode of the driving transistor is electrically connected with the control end of the driving circuit, the first electrode of the driving transistor is electrically connected with the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected with the second end of the driving circuit.
Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a compensation control circuit, a data writing circuit, and a tank circuit;
the compensation control circuit is respectively electrically connected with a second scanning end, the connecting node and the first end of the driving circuit and is used for controlling the connection between the connecting node and the first end of the driving circuit under the control of a second scanning signal provided by the second scanning end;
the data writing circuit is respectively electrically connected with the second scanning end, the data line and the second end of the driving circuit, and is used for writing the data voltage provided by the data line into the second end of the driving circuit under the control of the second scanning signal;
the energy storage circuit is electrically connected with the control end of the driving circuit and used for storing electric energy.
Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a light emitting element, a first light emitting control circuit, a second light emitting control circuit, and a third reset circuit;
the first light-emitting control circuit is respectively electrically connected with a light-emitting control end, a first voltage end and a second end of the driving circuit and is used for controlling the first voltage end to be communicated with the second end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end;
the second light-emitting control circuit is respectively electrically connected with the light-emitting control end, the first end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the first end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal;
the third reset circuit is electrically connected with the first reset control terminal, the third reset voltage terminal and the first pole of the light-emitting element respectively, and is used for writing a third reset voltage provided by the third reset voltage terminal into the first pole of the light-emitting element under the control of a first reset control signal provided by the first reset control terminal;
and the second pole of the light-emitting element is electrically connected with the second voltage end.
Optionally, the compensation control circuit includes a fourth transistor, and the data writing circuit includes a fifth transistor;
a control electrode of the fourth transistor is electrically connected with the second scanning end, a first electrode of the fourth transistor is electrically connected with the connection node, and a second electrode of the fourth transistor is electrically connected with the first end of the driving circuit;
a control electrode of the fifth transistor is electrically connected with the second scanning end, a first electrode of the fifth transistor is electrically connected with the data line, and a second electrode of the fifth transistor is electrically connected with the second end of the driving circuit;
the energy storage circuit comprises a first capacitor, the first light-emitting control circuit comprises a sixth transistor, the second light-emitting control circuit comprises a seventh transistor, and the third reset circuit comprises an eighth transistor;
the first end of the first capacitor is electrically connected with the control end of the driving circuit, and the second end of the first capacitor is electrically connected with the first voltage end;
a control electrode of the sixth transistor is electrically connected with the light-emitting control end, a first electrode of the sixth transistor is electrically connected with the first voltage end, and a second electrode of the sixth transistor is electrically connected with the second end of the driving circuit;
a control electrode of the seventh transistor is electrically connected to the light emission control terminal, a first electrode of the seventh transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element;
a control electrode of the eighth transistor is electrically connected to the first reset control terminal, a first electrode of the eighth transistor is electrically connected to the third reset voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.
The embodiment of the invention also provides a pixel driving method, which is applied to the pixel circuit, wherein the refresh frame comprises a first time period and a second time period; the pixel driving method includes:
the first reset circuit provides a first reset voltage provided by the first reset voltage terminal to the first terminal of the driving circuit in a first time period;
in a second time period, the reset sub-circuit provides a second reset voltage provided by a second reset voltage terminal to the connecting node under the control of a second reset control signal, and the control sub-circuit controls the connection node to be communicated with the control terminal of the driving circuit under the control of a first scanning signal so as to provide the second reset voltage to the control terminal of the driving circuit;
the first time period and the second time period are not overlapped or partially overlapped.
Optionally, the first reset circuit is further electrically connected to the first reset control terminal; the refresh frame comprises a first reset stage and a second reset stage which are arranged in sequence, and the pixel driving method comprises the following steps:
in a first reset phase, the first reset circuit provides a first reset voltage to the first end of the drive circuit under the control of a first reset control signal provided by the first reset control end;
the first time period is the first reset phase, and the second time period is the second reset phase.
Optionally, in the refresh frame, the number of times that the first reset circuit supplies the first reset voltage to the first terminal of the driving circuit is greater than the number of times that the second reset circuit supplies the second reset voltage to the control terminal of the driving circuit.
Optionally, the pixel circuit further includes a compensation control circuit, a data writing circuit, and a tank circuit; the refresh frame further comprises a charging phase arranged after the second reset phase; the pixel driving method further includes:
in a first reset phase, the compensation control circuit controls the connection between the connection node and the first end of the driving circuit under the control of a second scanning signal provided by a second scanning end, and the control sub-circuit controls the connection between the connection node and the control end of the driving circuit under the control of a first scanning signal provided by the first scanning end so as to write the first reset voltage into the control end of the driving circuit;
in a charging stage, a data line provides a data voltage, a data writing circuit writes the data voltage into a second end of the driving circuit under the control of a second scanning signal, a compensation control circuit controls the connection node to be communicated with a first end of the driving circuit under the control of the second scanning signal, and a control sub-circuit controls the connection node to be communicated with a control end of the driving circuit under the control of a first scanning signal;
when the charging phase begins, the driving circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end of the driving circuit, so that the energy storage circuit is charged through the data voltage, and the potential of the control end of the driving circuit is changed until the driving circuit controls the disconnection between the first end of the driving circuit and the second end of the driving circuit.
Optionally, the refresh frame further includes a third reset phase arranged after the charging phase; the pixel driving method includes:
in a third reset phase, the first reset circuit provides a first reset voltage to the first end of the driving circuit under the control of a first reset control signal, and the driving circuit controls the communication between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end of the driving circuit so as to provide the first reset voltage to the second end of the driving circuit.
Optionally, the refresh frame further includes a refresh light-emitting phase arranged after the third reset phase; the refresh lighting phase comprises at least one mutually independent refresh lighting time period; the pixel circuit further comprises a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit and a third reset circuit; the pixel driving method includes:
in the first reset phase and the third reset phase, the third reset circuit writes a third reset voltage provided by a third reset voltage end into the first pole of the light-emitting element under the control of the first reset control signal;
in a refreshing light-emitting time period, the first light-emitting control circuit controls the first voltage end to be communicated with the second end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end; the second light-emitting control circuit controls the communication between the first end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the driving circuit drives the light emitting element to emit light.
Optionally, the hold frame includes a fourth reset phase and a hold light-emitting phase that are sequentially set; the keeping luminous phase comprises at least one keeping luminous time period which is independent of each other; the pixel driving method includes:
in a fourth reset phase, the first reset circuit supplies a first reset voltage to the first end of the drive circuit under the control of the first reset control signal, the drive circuit controls the communication between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of the control end of the drive circuit so as to supply the first reset voltage to the second end of the drive circuit, and the third reset circuit writes a third reset voltage supplied by the third reset voltage end into the first pole of the light-emitting element under the control of the first reset control signal;
the first light-emitting control circuit controls the first voltage end to be communicated with the second end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end in a light-emitting keeping time period; the second light-emitting control circuit controls the first end of the driving circuit to be communicated with the first pole of the light-emitting element under the control of the light-emitting control signal; the driving circuit drives the light emitting element to emit light.
The embodiment of the invention also provides a display device which comprises the pixel circuit.
According to the pixel circuit, the pixel driving method and the display device, the threshold voltage Vth negative bias of the driving transistor included in the driving circuit is not too large in the refreshing frame, so that the threshold voltage Vth negative bias of the driving transistor is not too large in the refreshing frame and the maintaining frame, and VRR (VRR is frequency switching flicker, and is represented by difference between brightness and color coordinates before and after frequency switching) can be improved.
Drawings
Fig. 1A is a structural diagram of a pixel circuit according to an embodiment of the invention;
fig. 1B is a waveform diagram of Vth in a refresh frame F1 and a waveform diagram of Vth in a sustain frame F2 in the related art;
FIG. 2 is a block diagram of a pixel circuit according to at least one embodiment of the invention;
FIG. 3 is a block diagram of a pixel circuit according to at least one embodiment of the invention;
FIG. 4 is a block diagram of a pixel circuit according to at least one embodiment of the invention;
FIG. 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;
FIG. 6 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 5 according to the present invention;
FIG. 7 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 5 according to the present invention;
FIG. 8 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 5 according to the present invention;
fig. 9A is a waveform diagram of the first input signal STV1, the first clock signal CLK11, the first second clock signal CLK12, and the first reset control signal;
fig. 9B is a waveform diagram of the second input signal STV2, the second first clock signal CLK21, the second clock signal CLK22, the second third clock signal CLK23, the second fourth clock signal CLK24, and the second scan signal;
fig. 9C is a waveform diagram of the third input signal STV3, the third first clock signal CLK31, the third second clock signal CLK32, and the light-emission control signal;
fig. 9D is a waveform diagram of the fourth input signal STV4, the fourth first clock signal CLK41, the fourth second clock signal CLK42, and the first scan signal;
fig. 9E is a waveform diagram of the fifth input signal STV5, the five first clock signals CLK51, the fifth second clock signal CLK52, and the second reset control signal.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except for the gate, one of the two poles is referred to as a first pole, and the other pole is referred to as a second pole.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.
As shown in fig. 1A, a pixel circuit according to an embodiment of the present invention includes a driver circuit 10, a first reset circuit 11, and a second reset circuit 12; as shown in fig. 2, the second reset circuit 12 includes a reset sub-circuit 21 and a control sub-circuit 22;
as shown in fig. 1A, the first reset circuit 11 is electrically connected to a first reset voltage terminal VR1 and a first terminal of the driving circuit 10, respectively, and is configured to provide a first reset voltage Vinit1 provided by the first reset voltage terminal VR1 to the first terminal of the driving circuit 10 during a first period of time in a refresh frame;
the second reset circuit 12 is electrically connected to a second reset voltage terminal VR2 and the control terminal of the driving circuit 10, and is configured to, in a refresh frame and in a second time period, provide a second reset voltage Vinit2 provided by the second reset voltage terminal VR2 to the control terminal of the driving circuit 10;
the first time period and the second time period are not overlapped or partially overlapped;
as shown in fig. 2, the reset sub-circuit 21 is electrically connected to the second reset control terminal NR, the first reset voltage terminal VR2 and the connection node J1, respectively, for providing the second reset voltage Vinit2 to the connection node J1 under the control of a second reset control signal provided by the second reset control terminal NR;
the control sub-circuit 22 is electrically connected to the first scanning terminal GN, the connection node J1, and the control terminal of the driving circuit 10, and is configured to control the connection node J1 to communicate with the control terminal of the driving circuit 10 under the control of a first scanning signal provided by the first scanning terminal GN, so as to write the second reset voltage Vinit2 into the control terminal of the driving circuit 10.
In operation of the embodiment of the pixel circuit according to the present invention, in a refresh frame, in a first period, the first reset circuit 11 provides the first reset voltage Vinit1 to the first terminal of the driving circuit 10, in a second period, the second reset circuit 12 provides the second reset voltage Vint2 to the control terminal of the driving circuit 10, and the first period and the second period do not overlap or partially overlap, so that in the refresh frame, the threshold voltage Vth negative bias of the driving transistor included in the driving circuit 10 is not too large, so that in the refresh frame and the retention frame, the threshold voltage negative bias of the driving transistor is not too large, and therefore VRR (VRR is frequency switching flicker, which is represented as a difference between luminance and color coordinates before and after frequency switching) can be improved.
In at least one embodiment of the present invention, vinit1 may be a positive value, vinit2 may be a negative value, vinit1 may have a voltage value greater than or equal to 6.5V and less than or equal to 7.4V, and Vinit2 may have a voltage value greater than or equal to-4V and less than or equal to-3V, but not limited thereto.
In at least one embodiment of the present invention, the non-overlapping between the first time period and the second time period may refer to: the first time period and the second time period are independent of each other, and no overlapping time exists between the first time period and the second time period;
the partial overlap of the first time period and the second time period may refer to: there is an overlapping time between the first time period and the second time period, but the first time period and the second time period are not the same time period, and the first time period is not included in the second time period, and the second time period is not included in the first time period.
As shown in fig. 1B, in the related art, vth is negatively biased to be larger in the refresh frame F1 and smaller in the sustain frame F2, so that the threshold voltage Vth of the driving transistor is larger in the sustain frame F2 than in the refresh frame F1, thereby generating frequency switching flicker.
In at least one embodiment of the present invention, as shown in fig. 2, based on the embodiment of the pixel circuit shown in fig. 1A, the first reset circuit 11 is further electrically connected to a first reset control terminal PR, and is configured to provide the first reset voltage Vinit1 to the first terminal of the driving circuit 10 under the control of a first reset control signal provided by the first reset control terminal PR.
In operation of at least one embodiment of the pixel circuit of the present invention as shown in fig. 2, the refresh frame may include a first reset phase and a second reset phase arranged in sequence,
in the first reset phase, the first reset circuit 11 provides a first reset voltage Vinit1 to the first terminal of the driving circuit 10 under the control of the first reset control signal provided by the first reset control terminal PR;
in a second reset phase, the reset sub-circuit 21 provides a second reset voltage Vinit2 to the connection node J1 under the control of a second reset control signal provided by a second reset control terminal NR, and the control sub-circuit 22 controls the connection node J1 and the control terminal of the driving circuit 10 to communicate with each other under the control of a first scan signal provided by the first scan terminal GN;
the first time period may be the first reset phase and the second time period may be the second reset phase.
In at least one embodiment of the present invention, in the refresh frame, the number of times the first reset circuit supplies the first reset voltage to the first terminal of the driving circuit is greater than the number of times the second reset circuit supplies the second reset voltage to the control terminal of the driving circuit.
In specific implementation, the refresh frame may include a first reset stage, a second reset stage, and a third reset stage that are sequentially set;
in the first reset stage, the first reset circuit provides a first reset voltage to the first end of the drive circuit, and the first reset voltage is written into the control end of the drive circuit by matching with the compensation control circuit and the control sub-circuit so as to improve the hysteresis of a drive transistor included in the drive circuit;
in a second reset phase, the second reset circuit provides a second reset voltage to the control end of the drive circuit;
in the third reset phase, the first reset circuit provides the first reset voltage to the first end of the drive circuit, the first reset circuit and the drive circuit are matched to write the first reset voltage into the first end of the drive circuit and the second end of the drive circuit, and before the light-emitting phase is maintained in the maintaining frame, resetting of the electric potential of the first end of the drive circuit and the electric potential of the second end of the drive circuit is also carried out, so that in the refreshing frame, the negative bias degree of the drive transistor included in the drive circuit is not greatly different from that in the maintaining frame, and VRR is improved.
Optionally, the first reset circuit includes a first transistor, the reset sub-circuit includes a second transistor, and the control sub-circuit includes a third transistor;
the control electrode of the first transistor is electrically connected with the first reset control end, the first electrode of the first transistor is electrically connected with the first reset voltage end, and the second electrode of the first transistor is electrically connected with the first end of the driving circuit;
the control electrode of the second transistor is electrically connected with the second reset control end, and the first electrode of the second transistor is electrically connected with the second reset voltage end;
a control electrode of the third transistor is electrically connected to the first scan terminal, a first electrode of the third transistor is electrically connected to a second electrode of the second transistor, and a second electrode of the third transistor is electrically connected to a control terminal of the driving circuit.
As shown in fig. 3, on the basis of at least one embodiment of the pixel circuit shown in fig. 2, the pixel circuit according to at least one embodiment of the present invention further includes a compensation control circuit 31, a data writing circuit 32, and a tank circuit 33;
the compensation control circuit 31 is electrically connected to the second scan terminal GP, the connection node J1 and the first terminal of the driving circuit 10, respectively, and is configured to control the connection node J1 and the first terminal of the driving circuit 10 to communicate with each other under the control of a second scan signal provided by the second scan terminal GP;
the Data writing circuit 32 is electrically connected to the second scanning terminal GP, the Data line Data, and the second terminal of the driving circuit 10, and is configured to write the Data voltage Vdata provided by the Data line Data into the second terminal of the driving circuit 10 under the control of the second scanning signal;
the energy storage circuit 33 is electrically connected to the control terminal of the driving circuit 10, and is configured to store electric energy.
In operation of at least one embodiment of the pixel circuit shown in fig. 3 of the present invention, the refresh frame further comprises a charging phase disposed after the second reset phase;
in the first reset phase, the compensation control circuit 31 controls the connection between the connection node J1 and the first terminal of the driving circuit 10 under the control of the second scan signal provided by the second scan terminal GP, and the control sub-circuit 22 controls the connection between the connection node J1 and the control terminal of the driving circuit 10 under the control of the first scan signal provided by the first scan terminal GN, so as to write the first reset voltage Vinit1 into the control terminal of the driving circuit 10, so as to eliminate hysteresis of the driving transistor included in the driving circuit 10;
in the charging phase, a Data voltage Vdata is provided by the Data line Data, the Data writing circuit 32 writes the Data voltage Vdata into the second end of the driving circuit 10 under the control of a second scanning signal, the compensation control circuit 31 controls the connection between the connection node J1 and the first end of the driving circuit 10 to be communicated under the control of the second scanning signal, and the control sub-circuit 22 controls the connection between the connection node J1 and the control end of the driving circuit 10 to be communicated under the control of a first scanning signal;
at the beginning of the charging phase, the driving circuit 10 controls the connection between the first end of the driving circuit 10 and the second end of the driving circuit 10 under the control of the potential of the control end thereof, so as to charge the energy storage circuit 33 by the data voltage Vdata, and changes the potential of the control end of the driving circuit 10 until the driving circuit 10 controls the disconnection between the first end of the driving circuit 10 and the second end of the driving circuit 10, at this time, the potential of the control end of the driving circuit 10 is Vdata + Vth, so as to perform threshold voltage compensation, where Vth is the threshold voltage of the driving transistor included in the driving circuit 10.
In specific implementation, the refresh frame further includes a third reset phase arranged after the charging phase;
in a third reset phase, the first reset circuit 11 provides a first reset voltage Vinit1 to the first terminal of the driving circuit 10 under the control of a first reset control signal, and the driving circuit 10 controls the communication between the first terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of the potential of the control terminal thereof, so as to provide the first reset voltage Vinit1 to the second terminal of the driving circuit 10.
In actual operation, after the charging phase, a third reset phase is further included in the refresh frame, and in the third reset phase, the first reset circuit 11 and the driving circuit 10 cooperate to write the first reset voltage Vinit1 into the first terminal of the driving circuit 10 and the second terminal of the driving circuit, and before the holding frame and the light-emitting phase, resetting the potential of the first terminal of the driving circuit 10 and the potential of the second terminal of the driving circuit 10 is also performed, so that the negative bias degree of the driving transistor included in the driving circuit 10 in the refresh frame is not much different from the negative bias degree of the driving transistor included in the driving circuit 10 in the holding frame, so as to improve VRR.
As shown in fig. 4, on the basis of at least one embodiment of the pixel circuit shown in fig. 3, the pixel circuit according to at least one embodiment of the present invention further includes a light emitting element E0, a first light emitting control circuit 41, a second light emitting control circuit 42, and a third reset circuit 43;
the first light-emitting control circuit 41 is electrically connected to a light-emitting control end EM, a first voltage end V1 and a second end of the driving circuit 10, and is configured to control the first voltage end V1 to be communicated with the second end of the driving circuit 10 under the control of a light-emitting control signal provided by the light-emitting control end EM;
the second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the first terminal of the driving circuit 10, and the first pole of the light-emitting element E0, respectively, and is configured to control the communication between the first terminal of the driving circuit 10 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal;
the third reset circuit 43 is electrically connected to the first reset control terminal PR, the third reset voltage terminal VR3 and the first pole of the light emitting element E0, respectively, and configured to write the third reset voltage Vinit3 provided by the third reset voltage terminal VR3 into the first pole of the light emitting element E0 under the control of the first reset control signal provided by the first reset control terminal PR, so as to control the light emitting element E0 not to emit light and clear the charges remaining in the first pole of the light emitting element E0;
the second pole of the light emitting element E0 is electrically connected to the second voltage terminal V2.
In at least one embodiment of the present invention, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal, but not limited thereto;
the light emitting element may be an organic light emitting diode, the first pole of the light emitting element may be an anode, and the second pole of the light emitting element may be a cathode, but not limited thereto.
In at least one embodiment of the present invention, the voltage value of Vinit3 may be greater than or equal to-3V and less than or equal to-1.8V, but not limited thereto.
In operation of at least one embodiment of the pixel circuit shown in fig. 4 of the present invention, the refresh frame further includes a refresh light-emitting phase disposed after the third reset phase; the refresh lighting phase comprises at least one mutually independent refresh lighting time period;
in the first reset phase and the third reset phase, the third reset circuit 43 writes the third reset voltage Vinit3 supplied from the third reset voltage terminal VR3 into the first pole of the light emitting element E0 under the control of the first reset control signal;
in the refresh light-emitting period, the first light-emitting control circuit 41 controls the first voltage end V1 to be communicated with the second end of the driving circuit 10 under the control of the light-emitting control signal provided by the light-emitting control end EM; the second light-emitting control circuit 42 controls the communication between the first end of the driving circuit 10 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the driving circuit 10 drives the light emitting element E0 to emit light.
In operation of at least one embodiment of the pixel circuit shown in fig. 4, the hold frame includes a fourth reset phase and a hold emission phase that may be set in sequence; the keeping luminous phase comprises at least one keeping luminous time period which is independent of each other;
in a fourth reset phase, the first reset circuit 11 provides a first reset voltage Vinit1 to the first terminal of the driving circuit 10 under the control of a first reset control signal, the driving circuit 10 controls the communication between the first terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of the potential of the control terminal thereof, so as to provide the first reset voltage Vinit1 to the second terminal of the driving circuit 10, and the third reset circuit 43 writes a third reset voltage Vinit3 provided by a third reset voltage terminal VR3 into the first pole of the light emitting element E0 under the control of the first reset control signal;
in the light-emitting maintaining time period, the first light-emitting control circuit 41 controls the communication between the first voltage end V1 and the second end of the driving circuit 10 under the control of the light-emitting control signal provided by the light-emitting control end EM; the second light-emitting control circuit 42 controls the communication between the first end of the driving circuit 10 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the driving circuit 10 drives the light emitting element E0 to emit light.
In actual operation, before the light-emitting period of the holding frame, resetting the electric potential of the first terminal of the driving circuit 10 and the electric potential of the second terminal of the driving circuit 10 is performed, and after the charging period, a third reset period is further included, and during the third reset period, the first reset circuit 11 and the driving circuit 10 cooperate to write the first reset voltage Vinit1 into the first terminal of the driving circuit 10 and the second terminal of the driving circuit, so that during the refreshing frame, the negative bias degree of the driving transistor included in the driving circuit 10 is not much different from that during the holding frame, so as to improve VRR.
In the related art, the negative deviation degree of Vth is greatly different after the display refresh frequency is switched, so that the problem that the brightness and the color coordinate are different before and after the display refresh frequency is switched is caused. Taking the display refresh frequency as an example of switching from 120Hz to 10Hz, when the display refresh frequency is 120Hz, the Vth (Vth is the threshold voltage of the driving transistor) is controlled to be negatively biased in each frame time, and when the display refresh frequency is 10Hz, the Vth is negatively biased in the refresh frame and tends to be stable in the holding frame; based on this, in at least one embodiment of the present invention, after the refresh frame and the charge phase, the second node N2 and the third node N3 are reset by Vinit1 (Vinit 1 is a positive voltage), and in the hold frame and the fourth reset phase, the second node N2 and the third node N3 are also reset by Vinit1, so that the negative bias of Vth is not greatly different between the refresh frame and the hold frame, and the display luminance is not greatly different between the refresh frame and the hold frame, thereby improving VRR.
Optionally, the compensation control circuit includes a fourth transistor, and the data writing circuit includes a fifth transistor;
a control electrode of the fourth transistor is electrically connected with the second scanning end, a first electrode of the fourth transistor is electrically connected with the connection node, and a second electrode of the fourth transistor is electrically connected with the first end of the driving circuit;
a control electrode of the fifth transistor is electrically connected with the second scanning end, a first electrode of the fifth transistor is electrically connected with the data line, and a second electrode of the fifth transistor is electrically connected with the second end of the driving circuit.
Optionally, the energy storage circuit includes a first capacitor, the first light emission control circuit includes a sixth transistor, the second light emission control circuit includes a seventh transistor, and the third reset circuit includes an eighth transistor;
the first end of the first capacitor is electrically connected with the control end of the driving circuit, and the second end of the first capacitor is electrically connected with the first voltage end;
a control electrode of the sixth transistor is electrically connected with the light-emitting control end, a first electrode of the sixth transistor is electrically connected with the first voltage end, and a second electrode of the sixth transistor is electrically connected with the second end of the driving circuit;
a control electrode of the seventh transistor is electrically connected to the light emission control terminal, a first electrode of the seventh transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element;
a control electrode of the eighth transistor is electrically connected to the first reset control terminal, a first electrode of the eighth transistor is electrically connected to the third reset voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.
Optionally, the driving circuit comprises a driving transistor;
the control electrode of the driving transistor is electrically connected with the control end of the driving circuit, the first electrode of the driving transistor is electrically connected with the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected with the second end of the driving circuit.
As shown in fig. 5, on the basis of at least one embodiment of the pixel circuit shown in fig. 4, the first reset circuit 11 includes a first transistor T1, the reset sub-circuit 21 includes a second transistor T2, and the control sub-circuit 22 includes a third transistor T3; the driving circuit 10 includes a driving transistor T0; the light-emitting element is an organic light-emitting diode O1;
the gate of the first transistor T1 is electrically connected to the first reset control terminal PR, the source of the first transistor T1 is electrically connected to the first reset voltage terminal VR1, and the drain of the first transistor T1 is electrically connected to the drain of the driving transistor T0;
a gate of the second transistor T2 is electrically connected to the second reset control terminal NR, and a source of the second transistor T2 is electrically connected to the second reset voltage terminal VR 2;
a gate electrode of the third transistor T3 is electrically connected to the first scan terminal GN, a source electrode of the third transistor T3 is electrically connected to a drain electrode of the second transistor T2, and a drain electrode of the third transistor T3 is electrically connected to a gate electrode of the driving transistor T0;
the compensation control circuit 31 includes a fourth transistor T4, and the data write circuit 32 includes a fifth transistor T5;
a gate of the fourth transistor T4 is electrically connected to the second scan terminal GP, a source of the fourth transistor T4 is electrically connected to the connection node J1, and a drain of the fourth transistor T4 is electrically connected to the source of the driving transistor;
a gate of the fifth transistor T5 is electrically connected to the second scan terminal GP, a source of the fifth transistor T5 is electrically connected to the Data line Data, and a drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;
the energy storage circuit 33 includes a first capacitor C1, the first light-emitting control circuit 41 includes a sixth transistor T6, the second light-emitting control circuit 42 includes a seventh transistor T7, and the third reset circuit 43 includes an eighth transistor T8;
a first end of the first capacitor C1 is electrically connected to the gate of the driving transistor T0, and a second end of the first capacitor C1 is electrically connected to a high voltage end VDD;
a gate of the sixth transistor T6 is electrically connected to the emission control terminal EM, a source of the sixth transistor T6 is electrically connected to the high voltage terminal VDD, and a drain of the sixth transistor T6 is electrically connected to the source of the driving transistor T0;
a gate electrode of the seventh transistor T7 is electrically connected to the emission control terminal EM, a source electrode of the seventh transistor T7 is electrically connected to a drain electrode of the driving transistor T0, and a drain electrode of the seventh transistor T7 is electrically connected to an anode electrode of the organic light emitting diode O1;
a gate of the eighth transistor T8 is electrically connected to the first reset control terminal PR, a source of the eighth transistor T8 is electrically connected to the third reset voltage terminal VR3, and a drain of the eighth transistor T8 is electrically connected to an anode of the organic light emitting diode O1;
the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.
In at least one embodiment of the pixel circuit shown in fig. 5, T2 and T3 are n-type transistors, and T1, T4, T5, T6, T7, T8 and T0 are p-type transistors, but not limited thereto.
In at least one embodiment shown in fig. 5, a first node N1 is electrically connected to the gate of T0, a second node N2 is electrically connected to the source of T0, and a third node N3 is electrically connected to the drain of T0.
When the pixel circuit shown in fig. 5 of the present invention is in operation, as shown in fig. 6, the refresh frame F1 may include a first reset stage S11, a second reset stage S12, a charging stage S13, a third reset stage S14, and a refresh light-emitting stage S10, which are sequentially disposed; the refresh light-emitting period S10 includes a first refresh light-emitting period S101, a second refresh light-emitting period S102, a third refresh light-emitting period S103, and a fourth refresh light-emitting period S104, which are independent of each other;
in a first reset phase S11, PR provides a low voltage signal, GP provides a low voltage signal, GN provides a high voltage signal, NR provides a low voltage signal, T1 is turned on to write Vinit1 provided by VR1 to the third node N3, and both T3 and T4 are turned on to write Vinit1 to the first node N1; t8 is turned on to write Vinit3 provided by VR3 into the anode of O1, so that O1 does not emit light and the residual charge of the anode of O1 is removed;
in a second reset phase S12, PR provides a high voltage signal, GP provides a high voltage signal, GN provides a high voltage signal, NR provides a high voltage signal, and T2 and T3 are both turned on to write a second reset voltage Vinit2 provided by VR2 into the first node N1, reset the potential of the first node N1, and enable T0 to be turned on at the beginning of the charging phase S13;
in the charging stage S13, PR provides a high voltage signal, GP provides a low voltage signal, GN provides a high voltage signal, NR provides a low voltage signal, T4 is turned on, T5 is turned on, T3 is turned on, and Data provides a Data voltage Vdata;
when the charging phase S13 starts, T0 is turned on to charge C1 through Vdata, and the potential of the gate of T0 is raised until T0 is turned off, where the potential of the gate of T0 is Vdata + Vth, and Vth is a threshold voltage of T0;
in a third reset phase S14, PR provides a low voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, NR provides a low voltage signal, T1 is turned on, and T0 is turned on to write Vinit1 provided by VR1 into the second node N2 and the third node N3; t8 is turned on to write Vinit3 provided by VR3 into the anode of O1, so that O1 does not emit light and the residual charge of the anode of O1 is removed;
in the first refresh light-emitting period S101, the second refresh light-emitting period S102, the third refresh light-emitting period S103, and the fourth refresh light-emitting period S104, EM provides a low voltage signal, PR provides a high voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, NR provides a low voltage signal, T6 and T7 are all turned on, and T0 drives O1 to emit light.
In operation of at least one embodiment of the pixel circuit shown in fig. 5 of the present invention, as shown in fig. 7, the first reset phase S1 and the reset phase S2 may partially overlap, and the purpose of reducing the negative Vth offset in the refresh frame may also be achieved.
In operation of at least one embodiment of the pixel circuit shown in fig. 5 of the present invention, as shown in fig. 8, the hold frame F2 may include a fourth reset phase S24 and a hold light-emitting phase S20, which are sequentially arranged; the maintaining light-emitting period S20 includes a first maintaining light-emitting period S201, a second maintaining light-emitting period S202, a third maintaining light-emitting period S203, and a fourth maintaining light-emitting period S204 independent of each other;
in a fourth reset phase S24, PR provides a low voltage signal, T1 is turned on to write Vinit1 into the third node N3, T0 is turned on to write Vinit1 into the second node N2; t8 is turned on to write Vinit3 into the anode of O1 to control O1 not to emit light and to clear residual charges of the anode of O1;
in the first, second, third and fourth sustain light emitting periods S201, S202, S203 and S204, EM provides a low voltage signal, PR provides a high voltage signal, GP provides a high voltage signal, GN provides a low voltage signal, NR provides a low voltage signal, T6 and T7 are all turned on, and T0 drives O1 to emit light.
In fig. 9A, reference numeral STV1 is a first input signal, reference numeral CLK11 is a first clock signal, reference numeral CLK12 is a first second clock signal, corresponding to reference numeral PR is a waveform of a first reset control signal, STV1 is an input signal supplied to a driving circuit which generates the first reset control signal, and CK11 and CLK12 are clock signals supplied to the driving circuit which generates the first reset control signal;
in fig. 9B, a second input signal denoted by STV2, a second first clock signal denoted by CLK21, a second clock signal denoted by CLK22, a second third clock signal denoted by CLK23, a second fourth clock signal denoted by CLK24, a waveform of the second scan signal corresponding to reference GP, STV2 being an input signal supplied to the driving circuit for generating the second scan signal, and CK21, CLK22, CLK23, and CLK24 being clock signals supplied to the driving circuit for generating the second scan signal;
in fig. 9C, a third input signal denoted by STV3, a third first clock signal denoted by CLK31, a third second clock signal denoted by CLK32, and a waveform of the emission control signal corresponding to the reference EM, the STV3 is an input signal supplied to the driving circuit for generating the emission control signal, and the CK31 and the CLK32 are clock signals supplied to the driving circuit for generating the emission control signal;
in fig. 9D, a fourth input signal denoted by STV4, a fourth first clock signal denoted by CLK41, a fourth second clock signal denoted by CLK42, and a waveform of the first scan signal corresponding to the reference sign GN, the STV4 is an input signal supplied to a driving circuit for the first scan signal, and the CK41 and the CLK42 are clock signals supplied to the driving circuit for the first scan signal;
in fig. 9E, reference numeral STV5 is a fifth input signal, reference numeral CLK51 is a fifth first clock signal, reference numeral CLK52 is a fifth second clock signal, corresponding to reference numeral NR is a waveform of the second reset control signal, STV5 is an input signal supplied to the driving circuit generating the second reset control signal, and CK51 and CLK52 are clock signals supplied to the driving circuit generating the second reset control signal.
The pixel driving method provided by the embodiment of the invention is applied to the pixel circuit, and the refresh frame comprises a first time period and a second time period; the pixel driving method includes:
the first reset circuit provides a first reset voltage provided by the first reset voltage terminal to the first terminal of the driving circuit in a first time period;
in a second time period, the reset sub-circuit provides a second reset voltage provided by a second reset voltage terminal to the connecting node under the control of a second reset control signal, and the control sub-circuit controls the connection node to be communicated with the control terminal of the driving circuit under the control of a first scanning signal so as to provide the second reset voltage to the control terminal of the driving circuit;
the first time period and the second time period are not overlapped or partially overlapped.
In the pixel driving method according to the embodiment of the invention, in the refresh frame, in the first period, the first reset circuit supplies the first reset voltage to the first terminal of the driving circuit, in the second period, the second reset circuit supplies the second reset voltage to the control terminal of the driving circuit, and the first period and the second period do not overlap or partially overlap, so that in the refresh frame, the threshold voltage Vth of the driving transistor included in the driving circuit is negatively biased not to be too large, so that in the refresh frame and the hold frame, the threshold voltage negative bias of the driving transistor is not too large, and VRR (VRR is frequency switching flicker, which is represented by a difference between luminance and color coordinates before and after frequency switching) can be improved.
In at least one embodiment of the present invention, the first reset circuit is further electrically connected to a first reset control terminal; the refresh frame comprises a first reset stage and a second reset stage which are arranged in sequence, and the pixel driving method comprises the following steps:
in a first reset phase, the first reset circuit provides a first reset voltage to the first end of the drive circuit under the control of a first reset control signal provided by the first reset control end;
the first time period is the first reset phase, and the second time period is the second reset phase.
In at least one embodiment of the present invention, in the refresh frame, the number of times the first reset circuit supplies the first reset voltage to the first terminal of the driving circuit is greater than the number of times the second reset circuit supplies the second reset voltage to the control terminal of the driving circuit.
Optionally, the pixel circuit further includes a compensation control circuit, a data writing circuit, and a tank circuit; the refresh frame further comprises a charging phase arranged after the second reset phase; the pixel driving method further includes:
in a first reset phase, the compensation control circuit controls the connection between the connection node and the first end of the driving circuit under the control of a second scanning signal provided by a second scanning end, and the control sub-circuit controls the connection between the connection node and the control end of the driving circuit under the control of a first scanning signal provided by the first scanning end so as to write the first reset voltage into the control end of the driving circuit;
in a charging stage, a data line provides a data voltage, a data writing circuit writes the data voltage into a second end of the driving circuit under the control of a second scanning signal, a compensation control circuit controls the connection node to be communicated with a first end of the driving circuit under the control of the second scanning signal, and a control sub-circuit controls the connection node to be communicated with a control end of the driving circuit under the control of a first scanning signal;
when the charging stage begins, the driving circuit controls the first end of the driving circuit to be communicated with the second end of the driving circuit under the control of the potential of the control end of the driving circuit, so that the energy storage circuit is charged through the data voltage, and the potential of the control end of the driving circuit is changed until the driving circuit controls the first end of the driving circuit to be disconnected with the second end of the driving circuit.
In specific implementation, the refresh frame further includes a third reset phase arranged after the charging phase; the pixel driving method includes:
in a third reset phase, the first reset circuit provides a first reset voltage to the first end of the drive circuit under the control of a first reset control signal, and the drive circuit controls the communication between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of the control end of the drive circuit so as to provide the first reset voltage to the second end of the drive circuit.
In at least one embodiment of the present invention, the refresh frame further includes a refresh light-emitting phase disposed after the third reset phase; the pixel circuit further comprises a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit and a third reset circuit; the pixel driving method includes:
in the first reset phase and the third reset phase, the third reset circuit writes a third reset voltage provided by a third reset voltage end into the first pole of the light-emitting element under the control of the first reset control signal;
in a refreshing light-emitting stage, the first light-emitting control circuit controls the first voltage end to be communicated with the second end of the driving circuit under the control of a light-emitting control signal provided by a light-emitting control end; the second light-emitting control circuit controls the communication between the first end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the driving circuit drives the light emitting element to emit light.
In at least one embodiment of the present invention, the hold frame includes a fourth reset phase and a hold light-emitting phase that are sequentially set; the pixel driving method includes:
in a fourth reset phase, the first reset circuit supplies a first reset voltage to the first end of the drive circuit under the control of the first reset control signal, the drive circuit controls the communication between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of the control end of the drive circuit so as to supply the first reset voltage to the second end of the drive circuit, and the third reset circuit writes a third reset voltage supplied by the third reset voltage end into the first pole of the light-emitting element under the control of the first reset control signal;
in the stage of keeping light emitting, the first light emitting control circuit controls the first voltage end to be communicated with the second end of the driving circuit under the control of a light emitting control signal provided by the light emitting control end; the second light-emitting control circuit controls the first end of the driving circuit to be communicated with the first pole of the light-emitting element under the control of the light-emitting control signal; the driving circuit drives the light emitting element to emit light.
The display device according to the embodiment of the invention comprises the pixel circuit.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A pixel circuit is characterized by comprising a driving circuit, a first reset circuit and a second reset circuit;
the first reset circuit is respectively electrically connected with a first reset voltage end and the first end of the driving circuit and is used for providing a first reset voltage provided by the first reset voltage end to the first end of the driving circuit in a first time period in a refresh frame;
the second reset circuit is respectively electrically connected with a second reset voltage end and the control end of the driving circuit, and is used for providing a second reset voltage provided by the second reset voltage end to the control end of the driving circuit in a second time period in a refresh frame;
the first time period and the second time period are not overlapped or partially overlapped;
the second reset circuit comprises a reset sub-circuit and a control sub-circuit;
the reset sub-circuit is respectively electrically connected with a second reset control terminal, a first reset voltage terminal and a connecting node, and is used for providing a second reset voltage to the connecting node under the control of a second reset control signal provided by the second reset control terminal;
the control sub-circuit is respectively electrically connected with the first scanning end, the connection node and the control end of the driving circuit, and is used for controlling the connection node to be communicated with the control end of the driving circuit under the control of a first scanning signal provided by the first scanning end.
2. The pixel circuit according to claim 1, wherein the first reset circuit is further electrically connected to a first reset control terminal for providing the first reset voltage to the first terminal of the driving circuit under control of a first reset control signal provided by the first reset control terminal.
3. The pixel circuit according to claim 1, wherein a number of times the first reset circuit supplies the first reset voltage to the first terminal of the driver circuit is greater than a number of times the second reset circuit supplies the second reset voltage to the control terminal of the driver circuit in the refresh frame.
4. The pixel circuit according to claim 2, wherein the first reset circuit comprises a first transistor, the reset sub-circuit comprises a second transistor, and the control sub-circuit comprises a third transistor;
the control electrode of the first transistor is electrically connected with the first reset control end, the first electrode of the first transistor is electrically connected with the first reset voltage end, and the second electrode of the first transistor is electrically connected with the first end of the driving circuit;
a control electrode of the second transistor is electrically connected with the second reset control end, and a first electrode of the second transistor is electrically connected with the second reset voltage end;
a control electrode of the third transistor is electrically connected with the first scanning end, a first electrode of the third transistor is electrically connected with a second electrode of the second transistor, and a second electrode of the third transistor is electrically connected with a control end of the driving circuit;
the driving circuit comprises a driving transistor;
the control electrode of the driving transistor is electrically connected with the control end of the driving circuit, the first electrode of the driving transistor is electrically connected with the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected with the second end of the driving circuit.
5. The pixel circuit according to claim 2, further comprising a compensation control circuit, a data writing circuit, and a tank circuit;
the compensation control circuit is respectively electrically connected with the second scanning end, the connecting node and the first end of the driving circuit and is used for controlling the connection between the connecting node and the first end of the driving circuit under the control of a second scanning signal provided by the second scanning end;
the data writing circuit is respectively electrically connected with the second scanning end, the data line and the second end of the driving circuit, and is used for writing the data voltage provided by the data line into the second end of the driving circuit under the control of the second scanning signal;
the energy storage circuit is electrically connected with the control end of the driving circuit and used for storing electric energy.
6. The pixel circuit according to claim 5, further comprising a light emitting element, a first light emission control circuit, a second light emission control circuit, and a third reset circuit;
the first light-emitting control circuit is respectively electrically connected with a light-emitting control end, a first voltage end and a second end of the driving circuit and is used for controlling the first voltage end to be communicated with the second end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end;
the second light-emitting control circuit is respectively electrically connected with the light-emitting control end, the first end of the driving circuit and the first pole of the light-emitting element and is used for controlling the communication between the first end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal;
the third reset circuit is electrically connected with the first reset control terminal, the third reset voltage terminal and the first pole of the light-emitting element respectively, and is used for writing a third reset voltage provided by the third reset voltage terminal into the first pole of the light-emitting element under the control of a first reset control signal provided by the first reset control terminal;
and the second pole of the light-emitting element is electrically connected with the second voltage end.
7. The pixel circuit according to claim 6, wherein the compensation control circuit includes a fourth transistor, and the data writing circuit includes a fifth transistor;
a control electrode of the fourth transistor is electrically connected with the second scanning end, a first electrode of the fourth transistor is electrically connected with the connection node, and a second electrode of the fourth transistor is electrically connected with the first end of the driving circuit;
a control electrode of the fifth transistor is electrically connected with the second scanning end, a first electrode of the fifth transistor is electrically connected with the data line, and a second electrode of the fifth transistor is electrically connected with a second end of the driving circuit;
the energy storage circuit comprises a first capacitor, the first light-emitting control circuit comprises a sixth transistor, the second light-emitting control circuit comprises a seventh transistor, and the third reset circuit comprises an eighth transistor;
the first end of the first capacitor is electrically connected with the control end of the driving circuit, and the second end of the first capacitor is electrically connected with the first voltage end;
a control electrode of the sixth transistor is electrically connected with the light-emitting control end, a first electrode of the sixth transistor is electrically connected with the first voltage end, and a second electrode of the sixth transistor is electrically connected with the second end of the driving circuit;
a control electrode of the seventh transistor is electrically connected to the light emission control terminal, a first electrode of the seventh transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element;
a control electrode of the eighth transistor is electrically connected to the first reset control terminal, a first electrode of the eighth transistor is electrically connected to the third reset voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.
8. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 7, wherein the refresh frame includes a first period and a second period; the pixel driving method includes:
the first reset circuit provides a first reset voltage provided by the first reset voltage terminal to the first terminal of the driving circuit in a first time period;
in a second time period, the reset sub-circuit provides a second reset voltage provided by a second reset voltage terminal to the connecting node under the control of a second reset control signal, and the control sub-circuit controls the connection node to be communicated with the control terminal of the driving circuit under the control of a first scanning signal so as to provide the second reset voltage to the control terminal of the driving circuit;
the first time period and the second time period are not overlapped or partially overlapped.
9. The pixel driving method according to claim 8, wherein the first reset circuit is further electrically connected to a first reset control terminal; the refresh frame comprises a first reset stage and a second reset stage which are arranged in sequence, and the pixel driving method comprises the following steps:
in a first reset phase, the first reset circuit provides a first reset voltage to the first end of the drive circuit under the control of a first reset control signal provided by the first reset control end;
the first time period is the first reset phase, and the second time period is the second reset phase.
10. The pixel driving method according to claim 8 or 9, wherein the number of times the first reset circuit supplies the first reset voltage to the first terminal of the driving circuit is greater than the number of times the second reset circuit supplies the second reset voltage to the control terminal of the driving circuit in the refresh frame.
11. The pixel driving method according to claim 9, wherein the pixel circuit further includes a compensation control circuit, a data writing circuit, and a tank circuit; the refresh frame further comprises a charging phase arranged after the second reset phase; the pixel driving method further includes:
in a first reset phase, the compensation control circuit controls the connection node to be communicated with the first end of the drive circuit under the control of a second scanning signal provided by a second scanning end, and the control sub-circuit controls the connection node to be communicated with the control end of the drive circuit under the control of a first scanning signal provided by a first scanning end so as to write the first reset voltage into the control end of the drive circuit;
in a charging stage, a data line provides a data voltage, a data writing circuit writes the data voltage into a second end of the driving circuit under the control of a second scanning signal, a compensation control circuit controls the connection node to be communicated with a first end of the driving circuit under the control of the second scanning signal, and a control sub-circuit controls the connection node to be communicated with a control end of the driving circuit under the control of a first scanning signal;
when the charging phase begins, the driving circuit controls the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end of the driving circuit, so that the energy storage circuit is charged through the data voltage, and the potential of the control end of the driving circuit is changed until the driving circuit controls the disconnection between the first end of the driving circuit and the second end of the driving circuit.
12. The pixel driving method according to claim 11, wherein the refresh frame further includes a third reset phase provided after the charge phase; the pixel driving method includes:
in a third reset phase, the first reset circuit provides a first reset voltage to the first end of the driving circuit under the control of a first reset control signal, and the driving circuit controls the communication between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end of the driving circuit so as to provide the first reset voltage to the second end of the driving circuit.
13. The pixel driving method according to claim 12, wherein the refresh frame further includes a refresh light emission phase provided after the third reset phase; the refresh lighting phase comprises at least one mutually independent refresh lighting time period; the pixel circuit further comprises a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit and a third reset circuit; the pixel driving method includes:
in the first reset phase and the third reset phase, the third reset circuit writes a third reset voltage provided by a third reset voltage end into the first pole of the light-emitting element under the control of the first reset control signal;
in the refreshing light-emitting time period, the first light-emitting control circuit controls the first voltage end to be communicated with the second end of the driving circuit under the control of a light-emitting control signal provided by a light-emitting control end; the second light-emitting control circuit controls the first end of the driving circuit to be communicated with the first pole of the light-emitting element under the control of the light-emitting control signal; the driving circuit drives the light emitting element to emit light.
14. The pixel driving method according to claim 13, wherein the hold frame includes a fourth reset phase and a hold light emission phase that are set one after another; the keeping luminous phase comprises at least one keeping luminous time period which is independent of each other; the pixel driving method includes:
in a fourth reset phase, the first reset circuit supplies a first reset voltage to the first end of the drive circuit under the control of the first reset control signal, the drive circuit controls the communication between the first end of the drive circuit and the second end of the drive circuit under the control of the potential of the control end of the drive circuit so as to supply the first reset voltage to the second end of the drive circuit, and the third reset circuit writes a third reset voltage supplied by the third reset voltage end into the first pole of the light-emitting element under the control of the first reset control signal;
in the light-emitting maintaining time period, the first light-emitting control circuit controls the communication between the first voltage end and the second end of the driving circuit under the control of a light-emitting control signal provided by a light-emitting control end; the second light-emitting control circuit controls the first end of the driving circuit to be communicated with the first pole of the light-emitting element under the control of the light-emitting control signal; the driving circuit drives the light emitting element to emit light.
15. A display device comprising the pixel circuit according to any one of claims 1 to 7.
CN202211190607.1A 2022-09-28 2022-09-28 Pixel circuit, pixel driving method and display device Pending CN115482780A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024130491A1 (en) * 2022-12-19 2024-06-27 京东方科技集团股份有限公司 Driving circuit, driving method, driving module, and display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024130491A1 (en) * 2022-12-19 2024-06-27 京东方科技集团股份有限公司 Driving circuit, driving method, driving module, and display device

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