CN115472561A - Manufacturing method of array substrate for converting a-Si into IGZO with Top com structure - Google Patents

Manufacturing method of array substrate for converting a-Si into IGZO with Top com structure Download PDF

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Publication number
CN115472561A
CN115472561A CN202211069732.7A CN202211069732A CN115472561A CN 115472561 A CN115472561 A CN 115472561A CN 202211069732 A CN202211069732 A CN 202211069732A CN 115472561 A CN115472561 A CN 115472561A
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layer
igzo
photoresist
negative
array substrate
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陈伟
陈鑫
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CPT Technology Group Co Ltd
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CPT Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

A manufacturing method of an array substrate of a-Si to IGZO of a Topcom structure comprises the following steps: forming GE, PEITO, GI and SEIGZO on Glass in sequence; a DC photomask is adopted, and a DC hole is dry-etched, so that the SD and the PE can be conveniently lapped; coating a layer of negative photoresist PR on the IGZO and GI layers; exposing the negative photoresist PR by using the photomask of SD; developing the negative photoresist PR which is not illuminated; depositing a layer of SD on the negative PR and the IGZO by adopting a PVD mode; coating a layer of positive photoresist PR on the SD, and exposing by using the original photomask of the SD; developing the irradiated positive photoresist PR; etching away the metal layer which is not protected by the photoresist PR by adopting a wet etching mode; performing a film stripping process to remove the positive and negative photoresists to form SD; depositing a layer of CH; the common electrode layer UCITO is formed. The invention solves the problem of effective conversion of the semiconductor layer a-Si and the IGZO between the existing products.

Description

Manufacturing method of array substrate for converting a-Si into IGZO with Top com structure
Technical Field
The invention belongs to the technical field of manufacturing of display devices, and particularly relates to a manufacturing method of an a-Si-to-IGZO array substrate with a Top com structure.
Background
IGZO is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge-discharge rate of a TFT to a pixel electrode can be greatly improved, the response speed of the pixel is improved, the panel refreshing frequency is higher, and the ultrahigh-resolution TFT-LCD can be realized. Meanwhile, the existing amorphous silicon production line can be compatible with the IGZO process only by slightly changing, so that the cost is more competitive than that of low-temperature polycrystalline silicon (LTPS).
The Array process currently applied to TFT substrates mainly focuses on the 8Mask add-on model, the 9Mask Top-com TIC model (common electrode on the pixel electrode), and the 10Mask Mid-com TIC model (common electrode between the OC and the pixel electrode). In order to save cost, the existing a-Si model also synchronously develops the Top-com plug-in model of 7Mask, thereby not only shortening Cycle time, but also simplifying process flow and effectively improving benefit. Because the IGZO process has good compatibility with the existing a-Si production line, the direct conversion between the a-Si model and the IGZO model can be realized under the condition of not increasing the existing Mask. For this reason, a low cost advantage of the design based on the 7Mask model is expected to directly realize the a-Si to IGZO conversion. However, the substrate design and the process have been combined to find that, since the 7Mask design omits the PV insulating film layer and the organic planarization layer OC on the conventional TFT device, the pixel electrode PE-ITO is designed to be coplanar with the a-Si, the conventional a-sipotten process uses a dry etching method, and the pixel electrode PE-ITO is wet etched by oxalic acid. If the IGZO etching mode is also oxalic acid wet etching after the a-Si is converted into IGZO, it is inevitable that Damage is caused to the Pattern of the other film layer no matter the Pattern IGZO or the ITO is in sequence, and thus the normal display of the pixel is affected, as shown in fig. 1.
Disclosure of Invention
The invention aims to provide a manufacturing method of an array substrate of a-Si-to-IGZO of a Topcom structure, which effectively avoids the problem of damage caused by mutual etching between the IGZO and a pixel electrode and also improves the electrical uniformity and stability of a TFT.
The invention is realized in the following way:
a manufacturing method of an array substrate of a-Si to IGZO with a Top com structure comprises the following steps:
the first step is as follows: sequentially forming a gate metal layer GE on the Pattern on the Glass;
the second step: pattern forms a pixel electrode layer PE ITO;
the third step: depositing a gate insulation layer GI;
the fourth step: pattern one layer active layer SE IGZO;
the fifth step: a DC photomask is adopted, and a DC hole is dry-etched, so that the SD and the PE can be conveniently lapped;
and a sixth step: coating a negative photoresist PR on the active layer SE IGZO and the GI layer;
the seventh step: exposing the negative photoresist PR by using the photomask of SD;
eighth step: developing the negative photoresist PR which is not illuminated;
the ninth step: depositing a metal layer SD on the negative PR and the IGZO by adopting a PVD mode;
the tenth step: coating a positive photoresist PR on the metal layer SD, and exposing by using the original photomask of SD;
the eleventh step: developing off the irradiated positive photoresist PR;
the twelfth step: etching away the metal layer which is not protected by the photoresist PR by adopting a wet etching mode;
the thirteenth step: performing a film stripping process to remove the positive and negative photoresists and Pattern to form a metal layer SD;
the fourteenth step is that: depositing an insulating layer CH;
the fifteenth step: pattern forms the common electrode layer UC ITO.
Further, the gate metal layer GE in the first step is Ti/AI/Ti.
Further, the gate insulating layer GI in the third step is SiOx.
Further, the metal layer SD in the ninth step is Mo/AI/Mo.
Further, the insulating layer CH in the fourteenth step is SiOx.
The invention has the advantages that: in order to solve the effective conversion of a semiconductor layer a-Si and IGZO between the existing products, the invention changes the film forming sequence of the pixel electrode on the basis of not changing the number of masks of 7 masks, designs the pixel electrode on the same plane with the grid electrode, changes the opening position of the existing DC Mask, realizes the normal overlapping between the source drain electrode SD and the pixel electrode, and utilizes the characteristic of negative PR to coat a layer of negative PR on the active layer, thereby protecting the active layer from being damaged by acid liquid or plasma in the SDPattern process, not only effectively avoiding the damage problem of mutual etching between the IGZO and the pixel electrode, but also improving the electrical uniformity and stability of the TFT.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art structure of an array substrate of a-Si to IGZO conversion of Topcom structure.
FIG. 2 is a schematic diagram of the first step of the present invention.
FIG. 3 is a second step of the present invention.
Fig. 4 is a schematic diagram of a third step of the present invention.
FIG. 5 is a schematic diagram of a fourth step of the present invention.
Fig. 6 is a schematic diagram of a fifth step structure of the present invention.
Fig. 7 is a sixth step of the present invention.
Fig. 8 is a seventh step structure diagram of the present invention.
Fig. 9 is a schematic diagram of an eighth step structure of the present invention.
FIG. 10 is a schematic diagram of the ninth step of the present invention.
Fig. 11 is a schematic diagram of the tenth step of the present invention.
Fig. 12 is a schematic diagram of the eleventh step of the present invention.
FIG. 13 is a twelfth step of the present invention.
Fig. 14 is a schematic structural view of the thirteenth step of the present invention.
FIG. 15 is a schematic diagram of a fourteenth step of the present invention.
Fig. 16 is a schematic diagram of a fifteenth step of the present invention.
Detailed Description
Referring to fig. 2 to 16, a method for manufacturing an array substrate of a-Si to IGZO with Top com structure includes the following steps:
the first step is as follows: sequentially forming a gate metal layer GE-1 (Ti/AI/Ti) on the Pattern on the Glass;
the second step is that: pattern forms a pixel electrode layer PE-2ITO;
the third step: depositing a gate insulation layer GI-3SiOx;
the fourth step: pattern one active layer SE-4IGZO;
the fifth step: a DC photomask is adopted to dry-etch a DC hole, so that the source drain electrode SD is conveniently lapped with the PE;
and a sixth step: coating a layer of negative photoresist PR (the negative photoresist is characterized in that the negative photoresist is not dissolved in a developing solution after being exposed to light) on the active layer SE IGZO and the GI layer;
the seventh step: exposing the negative photoresist PR by using the photomask of SD;
eighth step: developing off the negative photoresist PR which is not irradiated by light;
the ninth step: depositing a metal layer SD-5 (Mo/AI/Mo) on the negative PR and the IGZO by adopting a PVD mode;
the tenth step: coating a positive photoresist PR (the positive photoresist is characterized in that the positive photoresist PR is dissolved in a developing solution after being exposed to light) on the metal layer SD, and exposing by using an original photomask of the SD;
the eleventh step: developing the irradiated positive photoresist PR;
a twelfth step: etching away the metal layer which is not protected by the photoresist PR by wet etching;
the thirteenth step: performing a film stripping process to remove the positive and negative photoresists, and forming a metal layer SD by Pattern;
the fourteenth step is that: depositing an insulating layer CH-6SiOx;
the fifteenth step: pattern forms the common electrode layer UC-7ITO.
Description of the terms and symbols:
pattern: patterning, the main process of Array is film formation/exposure/development/etching/stripping. The photoresist will form the corresponding pattern after developing, the etching process will etch the film without photoresist protection, will keep the pattern designed finally after stripping the film finally;
GE: a grid electrode, a Metal1 Metal layer, wherein Ti/AI/Ti is selected;
PE: a pixel electrode layer ITO;
GI: the grid insulating layer has an insulating layer with a larger dielectric constant, and SiOx can be selected in the scheme;
and SE: the TFT device comprises an active layer, a TFT device semiconductor layer and MOx, wherein IGZO is selected in the scheme;
SD: a source electrode, a drain electrode and a Metal 2 Metal layer, wherein Ti/AI/Ti or Mo/AI/Mo is selected;
CH: the insulating layer has a larger dielectric constant, and SiOx can be selected in the scheme;
UC: the scheme is designed for a Top com structure and is a common electrode layer ITO.
According to the invention, on the basis of not changing the number of masks of 7 masks, the film forming sequence of the pixel electrode is changed, the pixel electrode is designed to be coplanar with the grid electrode, the opening position of the existing DC Mask is changed, the normal lapping between the source drain electrode SD and the pixel electrode is realized, and the active layer is coated with a layer of negative PR by utilizing the characteristic of the negative PR, so that the active layer is protected from being damaged by acid liquor or plasma in the SDPattern process, the problem of mutual etching dam between the IGZO and the pixel electrode is effectively avoided, and the electrical uniformity and stability of the TFT are also improved.
The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications thereof by one of ordinary skill in the art should be considered as not departing from the scope of the present invention.

Claims (5)

1. A manufacturing method of an array substrate of a-Si to IGZO of a Top com structure is characterized in that: the method comprises the following steps:
the first step is as follows: sequentially forming a gate metal layer GE on the Pattern on the Glass;
the second step is that: patterning forms a pixel electrode layer PE ITO;
the third step: depositing a gate insulation layer GI;
the fourth step: pattern one layer active layer SE IGZO;
the fifth step: a DC photomask is adopted, and a DC hole is dry-etched, so that the SD and the PE can be conveniently lapped;
and a sixth step: coating a negative photoresist PR on the active layer SEIGZO and the gate insulating layer GI layer;
the seventh step: exposing the negative photoresist PR by using a photomask of SD;
eighth step: developing off the negative photoresist PR which is not irradiated by light;
the ninth step: depositing a metal layer SD on the negative PR and the IGZO by adopting a PVD mode;
the tenth step: coating a layer of positive photoresist PR on the metal layer SD, and exposing by using the original photomask of the SD;
the eleventh step: developing the irradiated positive photoresist PR;
the twelfth step: etching away the metal layer which is not protected by the photoresist PR by wet etching;
the thirteenth step: performing a film stripping process to remove the positive and negative photoresists, and forming a metal layer SD by Pattern;
the fourteenth step is that: depositing an insulating layer CH;
the fifteenth step: pattern forms the common electrode layer UC ITO.
2. The method for fabricating an array substrate of Top com structure a-Si to IGZO as claimed in claim 1, wherein: and the GE of the gate metal layer in the first step is Ti/AI/Ti.
3. The method for fabricating an array substrate of Top com structure a-Si to IGZO as claimed in claim 1, wherein: and the gate insulating layer GI in the third step is SiOx.
4. The method as claimed in claim 1, wherein the method for fabricating an array substrate of a-Si to IGZO with Top com structure comprises: and in the ninth step, the metal layer SD is Ti/AI/Ti or Mo/AI/Mo.
5. The method as claimed in claim 1, wherein the method for fabricating an array substrate of a-Si to IGZO with Top com structure comprises: in the fourteenth step, the insulating layer CH is SiOx.
CN202211069732.7A 2022-09-02 2022-09-02 Manufacturing method of array substrate for converting a-Si into IGZO with Top com structure Pending CN115472561A (en)

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CN202211069732.7A CN115472561A (en) 2022-09-02 2022-09-02 Manufacturing method of array substrate for converting a-Si into IGZO with Top com structure

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