CN203659865U - Array substrate and display device - Google Patents

Abstract

The utility model provides an array substrate and a display device. The array substrate comprises a grid electrode, a grid line, a grid insulation layer, an active layer, a source electrode, a drain electrode, a data line a first passivation layer, a pixel electrode, a second passivation layer and a common electrode; the grid electrode and the grid line are successively formed on a base substrate; and the source electrode, the drain electrode, the data line and first passivation layer via holes are formed in the same time of the composition process. A protecting layer is omitted in the array substrate, so the preparation process is optimized, the production period is shortened, the defect of bad chamfering is prevented, the transmittance of the first passivation layer is improved, image brightness is improved, usage power consumption of the display device is further reduced, cost is lowered at the same time, and batch production is improved.

Description

Array substrate and display device

Technical Field

The utility model relates to a liquid crystal display technology, concretely relates to array substrate and display device.

Background

In the field of the preparation of Thin Film Transistor Liquid crystal displays (TFT-LCDs), the basic structure of an array substrate is as follows in sequence: the pixel structure comprises a substrate, a grid electrode, a grid line, a grid insulating layer, an active layer, a source electrode, a drain electrode, a protective layer, a first passivation layer, a pixel electrode, a second passivation layer and a common electrode.

The preparation process of the array substrate in the prior art generally comprises the following steps:

a. manufacturing a grid and a grid line: as shown in fig. 1, a metal thin film is deposited on a substrate 1, and a gate electrode 3 and a gate line 2 are formed through a first patterning process. The patterning process comprises the following steps: depositing a film, masking, etching and stripping. In the present patterning process, the metals used include copper (Cu), molybdenum aluminum niobium (AlNd/Mo), aluminum molybdenum (Al/Mo), and the like.

b. Manufacturing a gate insulating layer and an active layer: as shown in fig. 2, a gate insulating layer 4, a silicon nitride/oxide film 5, and a doped silicon film 6 are sequentially deposited on the substrate after step a, and an active layer, i.e., a silicon island pattern, is formed from the amorphous silicon film 5 and the doped silicon film 6 by a second patterning process.

c. Manufacturing a gate insulating layer via hole: as shown in fig. 3, a third patterning process is performed on the substrate after step b, and a gate insulating layer via hole is formed above the gate line 2 of the substrate, so as to complete the fabrication of a gate insulating layer via hole of a row driver on array (GOA) functional unit of the array substrate.

d. Manufacturing a source electrode, a drain electrode and a channel: as shown in fig. 4, a metal film is deposited on the substrate after step c, a source electrode 7 and a drain electrode 10 are formed on the deposited metal film above the gate electrode 3 by a fourth patterning process, and a data line 8 is formed on the gate line 2, wherein the etching used in the current patterning process is wet etching. And etching off the doped silicon film of the active layer at the middle position of the source electrode 7 and the drain electrode 10.

e. Manufacturing a protective layer: as shown in fig. 5, on the substrate where step d is completed, a protective layer film is deposited to form a protective layer 14.

f. Manufacturing a first passivation layer and a first passivation layer through hole: as shown in fig. 6, a photosensitive resin material is coated on the substrate after step e, and a fifth patterning process is performed to obtain a first passivation layer 9, and a first passivation layer via hole is formed above the drain electrode 10.

g. Manufacturing a protective layer through hole: as shown in fig. 7, on the substrate after step f, etching is performed on the protective layer 14 at a position corresponding to the first passivation layer 9 via hole to form a protective layer via hole.

h. Manufacturing a pixel electrode: as shown in fig. 8, on the substrate after step g, a first indium tin oxide transparent film is deposited, and a transparent pixel electrode 11 is obtained through a sixth patterning process.

i. Manufacturing a second passivation layer and a second passivation layer through hole: as shown in fig. 9, a second passivation layer 12 film is deposited on the substrate after step h, and a second passivation layer via hole is formed on the second passivation layer 12 at a position corresponding to the gate insulating layer via hole through a seventh patterning process.

j. Manufacturing a common electrode: as shown in fig. 10, on the substrate where step i is completed, an indium tin oxide film is deposited, and the common electrode 13 is fabricated through an eighth patterning process.

In the above, the manufacturing of the array substrate is finally completed through eight times of composition processes. According to the array substrate prepared by the method, the protective layer is made of the silicon nitride material, the first passivation layer is made of the photosensitive resin material, and due to the difference of the two layers of materials, the problem of different transverse etching rates exists during the preparation of the via hole, so that poor chamfering of the via hole is easily caused, and the problems of abnormal display, dark corners and the like of a display screen due to poor line contact are caused. SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention is directed to an array substrate and a display device, so as to improve the performance of the array substrate.

In order to achieve the above purpose, the technical solution of the present invention is realized as follows:

one aspect of the present invention is to provide an array substrate, which includes a substrate base plate; a source electrode, a drain electrode and a data line are arranged on the substrate base plate, and the source electrode, the drain electrode and the data line are positioned on the first metal layer; a first passivation layer covers the first metal layer, and a first passivation layer through hole is formed in the first passivation layer.

Further, the array substrate further comprises an active layer disposed under the first metal layer.

Further, the active layer is a thin film made of amorphous silicon or a metal oxide semiconductor material, or comprises a double-layer thin film made of an amorphous silicon thin film and a doped silicon thin film material, or comprises a double-layer thin film made of a metal oxide semiconductor thin film and a doped silicon thin film material.

Further, the method also comprises the following steps:

the second metal layer covers the substrate;

the gate insulating layer is covered on the second metal layer and is positioned below the active layer;

a pixel electrode over the first passivation layer;

a second passivation layer of a second passivation layer via hole, the second passivation layer overlying the first passivation layer and the pixel electrode;

a common electrode on the second passivation layer;

the gate insulating layer via hole is used for connecting a gate line and a data line of the first metal layer; and the second passivation layer through hole is used for completing a lead of the pixel electrode.

Another aspect of the present invention is to provide a display device, including the above-mentioned embodiment of the array substrate.

The utility model provides an array substrate has saved the protective layer, the effectual active layer that has protected channel department simultaneously has shortened production cycle, has promoted the volume production.

The utility model saves the manufacture of the protective layer in the preparation process, does not relate to two different materials of the protective layer and the passivation layer in the etching process, only has one etching speed on the passivation layer, avoids the defect of bad chamfer angle and improves the display effect of the display device; meanwhile, the preparation process is optimized, the production period is shortened, and the cost is reduced.

Drawings

Fig. 1 is a schematic cross-sectional view of an array substrate formed with a gate electrode and a gate line;

FIG. 2 is a schematic cross-sectional view of an array substrate formed with a gate insulating layer and an active layer;

FIG. 3 is a cross-sectional view of an array substrate formed with a gate insulator via;

FIG. 4 is a cross-sectional view of a prior art array substrate with source and drain electrodes formed thereon;

FIG. 5 is a schematic cross-sectional view illustrating a protective layer formed on an array substrate according to the prior art;

FIG. 6 is a schematic cross-sectional view illustrating a prior art array substrate with a first passivation layer and a first passivation layer via hole formed therein;

FIG. 7 is a schematic cross-sectional view illustrating a protective layer via hole formed in an array substrate according to the prior art;

fig. 8 is a schematic cross-sectional view illustrating a pixel electrode formed on an array substrate according to the prior art;

FIG. 9 is a schematic cross-sectional view illustrating a second passivation layer and a second passivation layer via hole formed on an array substrate according to the prior art;

fig. 10 is a schematic cross-sectional view illustrating a common electrode formed on an array substrate according to the related art;

fig. 11a is a schematic cross-sectional view illustrating a second metal layer formed on an array substrate according to a first embodiment of the present invention;

fig. 11b is a top view of the array substrate with the second metal layer according to the first embodiment of the present invention;

fig. 12a is a schematic cross-sectional view illustrating a first passivation layer formed on an array substrate according to a first embodiment of the present invention;

fig. 12b is a schematic cross-sectional view of the array substrate with source and drain electrodes and a first passivation layer via hole formed thereon according to the first embodiment of the present invention;

fig. 12c is a top view of the array substrate with the source and drain electrodes and the first passivation layer via hole formed according to the first embodiment of the present invention;

fig. 13a is a schematic cross-sectional view illustrating a pixel electrode formed on an array substrate according to a first embodiment of the present invention;

fig. 13b is a top view of the array substrate with pixel electrodes according to the first embodiment of the present invention;

fig. 14 is a schematic cross-sectional view illustrating a second passivation layer and a second passivation layer via hole formed on the array substrate according to the first embodiment of the present invention;

fig. 15 is a schematic cross-sectional view illustrating a common electrode formed on an array substrate according to a first embodiment of the present invention;

fig. 16a is a schematic cross-sectional view illustrating a first passivation layer formed on an array substrate according to a second embodiment of the present invention;

fig. 16b is a schematic cross-sectional view of an array substrate with source and drain electrodes and a first passivation layer via hole formed thereon according to a second embodiment of the present invention;

fig. 16c is a top view of the array substrate with the source electrode, the drain electrode and the first passivation layer via hole according to the second embodiment of the present invention.

Description of reference numerals:

the pixel structure comprises a substrate 1, a grid line 2, a grid electrode 3, a grid insulating layer 4, an amorphous silicon film 5, a doped silicon film 6, a source electrode 7, a data line 8, a first passivation layer 9, a drain electrode 10, a pixel electrode 11, a second passivation layer 12, a common electrode 13, a protective layer 14 and a photoresist 15.

Detailed Description

The invention is further described with reference to the following drawings and specific embodiments.

The embodiment of the utility model provides an array substrate, its preparation method includes:

and sequentially forming a first metal layer and a first passivation layer, forming a source electrode, a drain electrode and a data line on the first metal layer through a first composition process, and simultaneously forming a first passivation layer through hole on the first passivation layer. The metal used for the first metal layer comprises copper, molybdenum aluminum molybdenum or aluminum molybdenum. The first passivation layer via hole is used for connecting the data line of the first metal layer and the pixel electrode.

And forming an active layer through a second composition process before forming the first metal layer and the first passivation layer.

The active layer is an amorphous silicon film or a metal oxide semiconductor film or a double-layer film comprising an amorphous silicon film and a doped silicon film or a double-layer film comprising a metal oxide semiconductor film and a doped silicon film; the amorphous silicon may be a-Si, the metal oxide semiconductor may be Indium Gallium Zinc Oxide (IGZO), and the doped silicon may be n + Si.

Specifically, the first passivation layer may be a photosensitive resin or silicon nitride.

When the first passivation layer is formed using a photosensitive resin material:

forming a source electrode, a drain electrode and a data line on the first metal layer through a first composition process, and simultaneously forming a first passivation layer through hole on the first passivation layer comprises: coating photoresist on the first passivation layer, carrying out exposure and development after masking, and simultaneously etching the first passivation layer and the first metal layer to form a source electrode, a drain electrode, a data line and a first passivation layer through hole; in addition, when the active layer is a double-layer film including an amorphous silicon film and a doped silicon film or a double-layer film including a metal oxide semiconductor film and a doped silicon film, in the first patterning process, in the process of simultaneously etching the first passivation layer and the first metal layer, etching is simultaneously performed on a position of the doped silicon film corresponding to a channel between the source electrode and the drain electrode.

Compared with the prior art, the embodiment of the utility model saves the manufacture of the protective layer in the preparation process, optimizes the preparation process and shortens the production period; meanwhile, as the process step of manufacturing the protective layer is omitted, only the first passivation layer made of photosensitive resin is provided, and as the resin material has the characteristics of high light transmittance, low dielectric constant and easy coating flatness compared with protective layer materials such as silicon nitride and silicon oxide, the high light transmittance can enable more light to pass through the substrate, so that the power is saved, the capacitance can be reduced by the low dielectric constant, the stored charge amount is less, the logic power consumption is low, and the transmittance of the first passivation layer is improved; in addition, different materials are not involved in the etching process, and only the same etching speed exists, so that the defect of poor chamfering is avoided.

When the first passivation layer is formed of a silicon nitride material:

the forming a source electrode, a drain electrode and a data line on the first metal layer through a first composition process, and forming a first passivation layer through hole on the first passivation layer comprises: coating photoresist on the first passivation layer, carrying out exposure and development after masking, and simultaneously etching the first passivation layer and the first metal layer to form a source electrode and a drain electrode; ashing the photoresist to expose the silicon nitride at the position of the first passivation layer via hole; etching the silicon nitride at the position of the first passivation layer through hole;

or,

coating photoresist on the first passivation layer, carrying out exposure and development after masking, and etching the first passivation layer to form a first passivation layer through hole and expose the first metal layer; etching the first metal layer to form a source electrode and a drain electrode; ashing the photoresist to expose the silicon nitride at the position of the first passivation layer via hole; etching the silicon nitride at the position of the first passivation layer through hole;

in addition, when the active layer is a double-layer film comprising an amorphous silicon film and a doped silicon film or a double-layer film comprising a metal oxide semiconductor film and a doped silicon film, in a first composition process, the position corresponding to a channel between the doped silicon film and the source electrode and the drain electrode is etched while the silicon nitride at the position of the first passivation layer via hole is etched.

Further, the preparation method further comprises the following steps:

forming a second metal layer on the substrate, and forming a grid electrode and a grid line through a third composition process, wherein the metal adopted by the second metal layer comprises copper, molybdenum, aluminum molybdenum or aluminum molybdenum;

forming a gate insulating layer on the second metal layer before forming the active layer, and forming a gate insulating layer via hole on the gate insulating layer at a position corresponding to the gate line at the position of the driving thin film transistor at the periphery of the substrate by a fourth patterning process; the gate insulating layer can be made of SiNx, SiOx, SiNx/SiOx and the like; the gate insulating layer via hole is used for connecting the gate line and the data line of the first metal layer.

Forming a pixel electrode on the substrate on which the second metal layer, the gate insulating layer, the active layer, the first metal layer and the first passivation layer are formed through a fifth composition process; the material of the pixel electrode may be indium tin oxide.

Forming a second passivation layer on the first passivation layer and the pixel electrode, and forming a second passivation layer through hole on the second passivation layer at a position corresponding to the first passivation layer through hole through a sixth composition process; the second passivation layer is a silicon nitride film, a silicon oxide film or a double-layer film of silicon nitride and silicon oxide, and the second passivation layer through hole is used for completing a lead of the pixel electrode.

Forming a common electrode on the substrate on which the second passivation layer is formed through a seventh patterning process; wherein, the material of the common electrode may be indium tin oxide.

The first embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic cross-sectional view of an array substrate formed with a gate electrode and a gate line. As shown in fig. 1, an AlNd/Mo metal thin film is deposited on a substrate 1, and a gate electrode 3 and a gate line 2 are formed through a third patterning process.

Fig. 2 is a schematic cross-sectional view of an array substrate formed with a gate insulating layer and an active layer. As shown in fig. 2, silicon nitride is sequentially deposited on the gate electrode 3 and the gate line 2 to form a gate insulating layer 4, an amorphous silicon (a-Si) thin film 5, and a doped silicon (n + Si) thin film 6, and an active layer is formed on the a-Si thin film and the n + Si thin film through a second patterning process.

Fig. 3 is a schematic cross-sectional view of the array substrate with a gate insulating layer via hole formed therein. As shown in fig. 3, a Gate insulating layer via hole is formed through a fourth patterning process, so as to complete the fabrication of a Gate insulating layer via hole of a Gate Driver on Array (GOA) functional unit of an Array substrate.

Fig. 11a is a schematic cross-sectional view illustrating an array substrate having a first metal layer according to a first embodiment of the present invention. As shown in fig. 11a, an Al/Mo metal layer is deposited on the active layer, and at this time, the a-Si thin film of the active layer at the channel is covered by the metal layer, so that the active layer at the channel can be well protected and temporarily functions as a protective layer; fig. 11b is a top view of the array substrate with the first metal layer according to the first embodiment of the present invention. As shown in fig. 11a and 11b, the Al/Mo metal layer is etched, and the etched Al/Mo metal layer includes a metal layer portion for forming the source electrode 7, the drain electrode 10, and the data line 8, and also includes a metal layer portion covering over the channel. At this time, the source electrode 7, the drain electrode 10 and the data line 8 are not manufactured, and the first metal layer temporarily plays a good role in protecting the active layer.

Compared with the prior art, the utility model discloses in the first embodiment array substrate's preparation method saved the preparation of protective layer, consequently, further the cost is reduced, and the active layer of channel department has not only been avoided simultaneously receives the influence of photosensitive resin material, has also avoided the bad problem of grid insulating layer via hole chamfer that forms moreover, has promoted the transmittance of light, reduces the consumption of backlight, has shortened the preparation cycle, has promoted the volume production.

Fig. 12a is a schematic cross-sectional view illustrating an array substrate having a first passivation layer according to a first embodiment of the present invention. As shown in fig. 12a, a photoresist 15 is coated on the first passivation layer 9, and after masking, exposure and development are performed. Fig. 12b is a schematic cross-sectional view illustrating the array substrate according to the first embodiment of the present invention having a source electrode, a drain electrode, a data line and a first passivation layer via hole, and fig. 12c is a top view illustrating the array substrate according to the first embodiment of the present invention having a source electrode, a drain electrode and a first passivation layer via hole. As shown in fig. 12b and 12c, the first passivation layer 9 and the first metal layer are simultaneously etched through the first patterning process to form the source electrode 7, the drain electrode 10, the data line 8 and the first passivation layer via hole, and the n-Si thin film corresponding to the position of the channel region is simultaneously etched. At this time, on the premise of protecting the drain electrode 7, the source electrode 7, the drain electrode 10 and the data line 8 are formed, and the manufacturing of the first passivation layer via hole at the corresponding position of the drain electrode 7 and the gate insulating layer via hole is also completed.

Fig. 13a is a schematic cross-sectional view illustrating the array substrate according to the first embodiment of the present invention formed with a pixel electrode, and fig. 13b is a top view illustrating the array substrate according to the first embodiment of the present invention formed with a pixel electrode. As shown in fig. 13a and 13b, an indium tin oxide film is first deposited, and a pixel electrode 11 is obtained through a fifth patterning process, i.e., mask post exposure, development, and etching. The difference from the prior art is that when the ITO layer corresponding to the position of the channel is etched, the selection ratio of the etching liquid to the Al/Mo metal layer and the ITO layer is adjusted, so that only the ITO layer is etched without etching the Al/Mo metal layer, and therefore the source electrode 7 and the drain electrode 10 can be well protected, and poor contact is avoided.

Fig. 14 is a schematic cross-sectional view illustrating the array substrate according to the first embodiment of the present invention having a second passivation layer and a second passivation layer via hole formed therein. As shown in fig. 14, on the substrate after the foregoing steps, a SiNx film is deposited as a second passivation layer 12, and a sixth patterning process, i.e., post-mask exposure, development, and etching, is performed to form a second passivation layer via hole at the periphery of the array substrate, thereby completing the lead.

Fig. 15 is a schematic cross-sectional view of the array substrate according to the first embodiment of the present invention, in which a common electrode is formed. As shown in fig. 15, on the substrate on which the foregoing steps are completed, an indium tin oxide film is deposited, and post-exposure, development, and etching are performed through a seventh patterning process, i.e., a mask, thereby obtaining the common electrode 13.

In the second embodiment, the basic steps are the same as those of the first embodiment, except that the first passivation layer is made of a silicon nitride material. Fig. 16a, 16b and 16c show the fabrication of the first passivation layer made of silicon nitride, which requires mask adjustment compared to the prior art.

Fig. 16a is a schematic cross-sectional view of a second embodiment of the present invention, in which an array substrate is formed with a first passivation layer, fig. 16b is a schematic cross-sectional view of a second embodiment of the present invention, in which an array substrate is formed with a source electrode, a drain electrode and a first passivation layer via hole, and fig. 16c is a top view of a second embodiment of the present invention, in which an array substrate is formed with a source electrode, a drain electrode and a first passivation layer via hole. As shown in fig. 16a, 16b and 16c, the source, the drain and the first passivation layer via holes are formed in the array substrate using silicon nitride as the first passivation layer 9, and the following two schemes can be adopted:

according to the first scheme, photoresist 15 is coated on a first passivation layer 9, exposure and development are carried out after masking, and the first passivation layer 9 and a first metal layer are etched simultaneously to form a source electrode 7 and a drain electrode 10; ashing the photoresist to expose the silicon nitride at the position of the through hole of the first passivation layer; etching the silicon nitride at the position of the doped silicon film corresponding to the channel and the position of the first passivation layer through hole, and adjusting the etching selection ratio of the n-Si to the silicon nitride to be 1: 7, thereby ensuring that the n-Si film and the silicon nitride are effectively etched;

or,

coating photoresist 15 on the first passivation layer 9, performing exposure and development after masking, etching the first passivation layer 9 to form a first passivation layer through hole, and exposing the first metal layer; etching the first metal layer to form a source electrode and a drain electrode; ashing the photoresist to expose the silicon nitride at the position of the through hole of the first passivation layer; and etching the silicon nitride at the position of the doped silicon film corresponding to the channel and the position of the first passivation layer through hole. Adjusting the etching selection ratio of n-Si to silicon nitride to be 1: 7, thereby ensuring effective etching of the n-Si film and the silicon nitride.

At this time, on the premise of protecting the drain electrode 7, the source electrode 7, the drain electrode 10 and the data line 8 are formed, and the manufacturing of the first passivation layer via hole at the corresponding position of the drain electrode 7 and the gate insulating layer via hole is also completed.

In the third embodiment, the basic steps are the same as those in the first embodiment, except that the second patterning process for forming the active layer and the fourth patterning process for forming the gate insulating layer via hole are combined into a single patterning process, the photoresist is ashed by using a slit exposure technique or a half mask technique, so that the active layer region is exposed, and the active layer and the gate insulating layer via hole are fabricated at one time by the second patterning process.

The embodiment of the utility model provides an array substrate includes: a substrate base plate; a source electrode, a drain electrode and a data line are arranged on the substrate base plate, and the source electrode, the drain electrode and the data line are positioned on the first metal layer; a first passivation layer covers the first metal layer, and a first passivation layer through hole is formed in the first passivation layer.

The active layer is arranged below the first metal layer and is an amorphous silicon film or a metal oxide semiconductor film or a double-layer film comprising an amorphous silicon film and a doped silicon film or a double-layer film comprising a metal oxide semiconductor film and a doped silicon film;

further comprising:

the second metal layer covers the substrate;

the gate insulating layer is covered on the second metal layer and is positioned below the active layer;

a pixel electrode over the first passivation layer;

a second passivation layer of a second passivation layer via hole, the second passivation layer overlying the first passivation layer and the pixel electrode;

a common electrode on the second passivation layer;

the gate insulating layer via hole is used for connecting a gate line and a data line of the first metal layer; and the second passivation layer through hole is used for completing a lead of the pixel electrode.

The embodiment of the utility model provides a still provide one kind and include array substrate's display device. According to the display device, the array substrate omits a protective layer, the image quality brightness is improved, the use power consumption is further reduced, meanwhile, the process step of manufacturing the protective layer is omitted, the source electrode, the drain electrode, the data line and the first passivation layer through hole are completed in the same step, the cost is reduced, and the mass production is promoted.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (5)

1. The array substrate is characterized by comprising a substrate base plate; a source electrode, a drain electrode and a data line are arranged on the substrate base plate, and the source electrode, the drain electrode and the data line are positioned on the first metal layer; a first passivation layer covers the first metal layer, and a first passivation layer through hole is formed in the first passivation layer.

2. The array substrate of claim 1, further comprising an active layer disposed below the first metal layer.

3. The array substrate of claim 2, wherein the active layer is a thin film made of amorphous silicon or a metal oxide semiconductor material or comprises a double-layer thin film made of an amorphous silicon thin film and a doped silicon thin film material or comprises a double-layer thin film made of a metal oxide semiconductor thin film and a doped silicon thin film material.

4. The array substrate of any one of claims 1 to 3, further comprising:

the second metal layer covers the substrate;

the gate insulating layer is covered on the second metal layer and is positioned below the active layer;

a pixel electrode over the first passivation layer;

a second passivation layer of a second passivation layer via hole, the second passivation layer overlying the first passivation layer and the pixel electrode;

a common electrode on the second passivation layer;

the gate insulating layer via hole is used for connecting a gate line and a data line of the first metal layer; and the second passivation layer through hole is used for completing a lead of the pixel electrode.

5. A display device comprising the array substrate according to any one of claims 1 to 4.

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