CN203659865U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203659865U CN203659865U CN201320845061.9U CN201320845061U CN203659865U CN 203659865 U CN203659865 U CN 203659865U CN 201320845061 U CN201320845061 U CN 201320845061U CN 203659865 U CN203659865 U CN 203659865U
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- passivation layer
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- base palte
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- 239000000758 substrate Substances 0.000 title claims abstract description 35
- 238000002161 passivation Methods 0.000 claims abstract description 129
- 238000009413 insulation Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims description 61
- 239000002184 metal Substances 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 229910044991 metal oxide Inorganic materials 0.000 claims description 11
- 150000004706 metal oxides Chemical class 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000012528 membrane Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 abstract description 41
- 238000002360 preparation method Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 3
- 238000010923 batch production Methods 0.000 abstract 1
- 238000002834 transmittance Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 211
- 239000010408 film Substances 0.000 description 61
- 238000005530 etching Methods 0.000 description 38
- 229910052581 Si3N4 Inorganic materials 0.000 description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 24
- 239000011241 protective layer Substances 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000000151 deposition Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 6
- ZXTFQUMXDQLMBY-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo] ZXTFQUMXDQLMBY-UHFFFAOYSA-N 0.000 description 5
- 238000004380 ashing Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- PEQFPKIXNHTCSJ-UHFFFAOYSA-N alumane;niobium Chemical compound [AlH3].[Nb] PEQFPKIXNHTCSJ-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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Abstract
The utility model provides an array substrate and a display device. The array substrate comprises a grid electrode, a grid line, a grid insulation layer, an active layer, a source electrode, a drain electrode, a data line a first passivation layer, a pixel electrode, a second passivation layer and a common electrode; the grid electrode and the grid line are successively formed on a base substrate; and the source electrode, the drain electrode, the data line and first passivation layer via holes are formed in the same time of the composition process. A protecting layer is omitted in the array substrate, so the preparation process is optimized, the production period is shortened, the defect of bad chamfering is prevented, the transmittance of the first passivation layer is improved, image brightness is improved, usage power consumption of the display device is further reduced, cost is lowered at the same time, and batch production is improved.
Description
Technical field
The utility model relates to lcd technology, is specifically related to a kind of array base palte and display unit.
Background technology
At Thin Film Transistor-LCD (TFT-LCD; Thin Film Transistor Liquid Crystal Display) preparation field, the basic structure of array base palte is followed successively by: substrate, grid and grid line, gate insulation layer, active layer, source electrode, drain electrode, protective layer, the first passivation layer, pixel electrode, the second passivation layer, public electrode.
Array base palte preparation process of the prior art generally comprises following steps:
A, make grid and grid line: as shown in Figure 1, depositing metal films on substrate 1, forms grid 3 and grid line 2 by composition technique for the first time.Wherein, composition technique comprises the steps: deposit film, mask, etching, peels off.In this composition technique, the metal adopting comprises copper (Cu), molybdenum aluminium niobium (AlNd/Mo), aluminium molybdenum (Al/Mo) etc.
B, making gate insulation layer and active layer: as shown in Figure 2, on the substrate of completing steps a, deposit successively gate insulation layer 4 films, silicon nitride/silicon oxide film 5, doped silicon film 6, form active layer by amorphous silicon membrane 5, doped silicon film 6, i.e. silicon island pattern by composition technique for the second time.
C, making grid insulating layer through hole: as shown in Figure 3, on the substrate of completing steps b, pass through composition technique for the third time, above the grid line 2 of substrate, form grid insulating layer through hole, complete the capable driving of array base palte (Gate driver on array, be called for short GOA) making of the grid insulating layer through hole of functional unit.
D, making source electrode, drain electrode, raceway groove: as shown in Figure 4, depositing metal films on the substrate of completing steps c, on deposited metallic film, above grid 3, make source electrode 7, drain electrode 10 by the 4th composition technique, above grid line 2, make data wire 8 simultaneously, wherein, the etching that this composition technique adopts is wet etching.Again the doped silicon film of the active layer at the centre position place of source electrode 7, drain electrode 10 is etched away.
E, making protective layer: as shown in Figure 5, on the substrate of completing steps d, deposition protective layer film, forms protective layer 14.
F, making the first passivation layer and the first passivation layer via hole: as shown in Figure 6, on the substrate of completing steps e, apply photosensitive resin material, through the 5th composition technique, obtain the first passivation layer 9, above drain electrode 10, make the first passivation layer via hole simultaneously.
G, making protective layer via hole: as shown in Figure 7, on the substrate of completing steps f, on protective layer 14, etching making protective layer via hole is carried out in the position corresponding with the first passivation layer 9 via holes.
H, making pixel electrode: as shown in Figure 8, on the substrate of completing steps g, deposition the first indium tin oxide transparent film, obtains transparent pixel electrode 11 by the 6th composition technique.
I, making the second passivation layer and the second passivation layer via hole: as shown in Figure 9, on the substrate of completing steps h, deposit the second passivation layer 12 films, on the second passivation layer 12, the position corresponding with grid insulating layer through hole make the second passivation layer via hole by the 7th composition technique.
J, making public electrode: as shown in figure 10, on the substrate of completing steps i, deposition indium tin oxide films, makes public electrode 13 by the 8th composition technique.
Above, need, through eight composition techniques, finally complete the making of array base palte altogether.The array base palte of preparation thus; protective layer material is silicon nitride material; the first passivation material is photosensitive resin material; the difference of materials at two layers makes the problem that exists lateral etching speed different in the time preparing via hole; be easy to cause the chamfering of via hole bad, thereby cause line loose contact and bring the problems such as the abnormal and corner obfuscation of the demonstration of display screen.Utility model content
In view of this, main purpose of the present utility model is to provide a kind of array base palte and display unit, to improve array base palte performance.
In order to achieve the above object, the technical solution of the utility model is achieved in that
The utility model provides a kind of array base palte on the one hand, comprises underlay substrate; On described underlay substrate, be provided with source electrode, drain electrode and data wire, described source electrode, drain electrode and data line bit are on the first metal layer; On described the first metal layer, be coated with the first passivation layer, on described the first passivation layer, be provided with the first passivation layer via hole.
Further, described array base palte also comprises active layer, and described active layer is arranged under described the first metal layer.
Further, described active layer is adopt the film that amorphous silicon or metal oxide semiconductor material make or comprise and adopt the bilayer film that amorphous silicon membrane and doped silicon film material make or comprise the bilayer film that adopts metal oxide semiconductor films and doped silicon film material to make.
Further, also comprise:
The second metal level of grid and grid line, described the second metal level is covered on described underlay substrate;
The gate insulation layer of grid insulating layer through hole, described gate insulation layer is covered on described the second metal level and is positioned under described active layer;
Pixel electrode, described pixel electrode is positioned on described the first passivation layer;
The second passivation layer of the second passivation layer via hole, described the second passivation layer is covered on described the first passivation layer and described pixel electrode;
Public electrode, described public electrode is positioned on the second passivation layer;
Wherein, described grid insulating layer through hole is for connecting the data wire of grid line and the first metal layer; Described the second passivation layer via hole has been used for the lead-in wire of pixel electrode.
The utility model provides a kind of display unit on the other hand, comprises the array base palte described in above-described embodiment.
A kind of array base palte provided by the utility model, has saved protective layer, has effectively protected the active layer at raceway groove place simultaneously, has shortened the production cycle, has promoted volume production.
The utility model has saved the making of protective layer in preparation technology, in etching process, do not relate to two kinds of different materials of protective layer and passivation layer, only there is an etching speed on passivation layer, avoided the bad defect of chamfering, improved the display effect of display unit; Optimize preparation technology simultaneously, shortened the production cycle, reduced cost.
Brief description of the drawings
Fig. 1 is the schematic cross-section that array base palte is formed with grid and grid line;
Fig. 2 is the schematic cross-section that array base palte is formed with gate insulation layer and active layer;
Fig. 3 is the sectional view that array base palte is formed with grid insulating layer through hole;
Fig. 4 is the schematic cross-section that in prior art, array base palte is formed with source electrode, drain electrode;
Fig. 5 is the schematic cross-section that in prior art, array base palte is formed with protective layer;
Fig. 6 is the schematic cross-section that in prior art, array base palte is formed with the first passivation layer and the first passivation layer via hole;
Fig. 7 is the schematic cross-section that in prior art, array base palte is formed with protective layer via hole;
Fig. 8 is the schematic cross-section that in prior art, array base palte is formed with pixel electrode;
Fig. 9 is the schematic cross-section that in prior art, array base palte is formed with the second passivation layer and the second passivation layer via hole;
Figure 10 is the schematic cross-section that in prior art, array base palte is formed with public electrode;
Figure 11 a is the schematic cross-section that the utility model the first embodiment array base palte is formed with the second metal level;
Figure 11 b is the vertical view that the utility model the first embodiment array base palte is formed with the second metal level;
Figure 12 a is the schematic cross-section that the utility model the first embodiment array base palte is formed with the first passivation layer;
Figure 12 b is the schematic cross-section that the utility model the first embodiment array base palte is formed with source electrode, drain electrode and the first passivation layer via hole;
Figure 12 c is the vertical view that the utility model the first embodiment array base palte is formed with source electrode, drain electrode and the first passivation layer via hole;
Figure 13 a is the schematic cross-section that the utility model the first embodiment array base palte is formed with pixel electrode;
Figure 13 b is the vertical view that the utility model the first embodiment array base palte is formed with pixel electrode;
Figure 14 is the schematic cross-section that the utility model the first embodiment array base palte is formed with the second passivation layer and the second passivation layer via hole;
Figure 15 is the schematic cross-section that the utility model the first embodiment array base palte is formed with public electrode;
Figure 16 a is the schematic cross-section that the utility model the second embodiment array base palte is formed with the first passivation layer;
Figure 16 b is the schematic cross-section that the utility model the second embodiment array base palte is formed with source electrode, drain electrode and the first passivation layer via hole;
Figure 16 c is the vertical view that the utility model the second embodiment array base palte is formed with source electrode, drain electrode and the first passivation layer via hole.
Description of reference numerals:
1 substrate, 2 grid lines, 3 grids, 4 gate insulation layers, 5 amorphous silicon membranes, 6 doped silicon films, 7 source electrodes, 8 data wires, 9 first passivation layers, 10 drain electrodes, 11 pixel electrodes, 12 second passivation layers, 13 public electrodes, 14 protective layers, 15 photoresists.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described further.
The utility model embodiment provides a kind of array base palte, and its preparation method comprises:
Form successively the first metal layer, the first passivation layer, on the first metal layer, form source electrode, drain electrode and data wire by the first composition technique, and on the first passivation layer, form the first passivation layer via hole simultaneously.The metal that the first metal layer adopts comprises copper, molybdenum aluminium molybdenum or aluminium molybdenum.The first passivation layer via hole is for connecting data wire and the pixel electrode of the first metal layer.
Before described formation the first metal layer, the first passivation layer, form active layer by the second composition technique.
Described active layer is amorphous silicon membrane or metal oxide semiconductor films or comprises amorphous silicon membrane and the bilayer film of doped silicon film or comprise metal oxide semiconductor films and the bilayer film of doped silicon film; Wherein, amorphous silicon can be a-Si, and metal-oxide semiconductor (MOS) can be indium gallium zinc oxide (IGZO), and doped silicon can be n+Si.
Concrete, the first passivation layer can be photosensitive resin or silicon nitride.
In the time that described the first passivation layer adopts photosensitive resin material to form:
On the first metal layer, form source electrode, drain electrode, data wire by the first composition technique, and simultaneously on the first passivation layer, form the first passivation layer via hole and comprise: on described the first passivation layer, apply photoresist, after mask, expose, develop, described the first passivation layer and the first metal layer are carried out to etching simultaneously, form source electrode, drain electrode, data wire and the first passivation layer via hole; In addition, when described active layer is to comprise the bilayer film of amorphous silicon membrane and doped silicon film or comprise metal oxide semiconductor films and when the bilayer film of doped silicon film, in the first composition technique, described, the first passivation layer and the first metal layer are carried out in the process of etching simultaneously, to described doped silicon film, etching is carried out in the corresponding position of the raceway groove with source electrode and between draining simultaneously.
Compared with prior art, the utility model embodiment has saved the making of protective layer in preparation technology, has optimized preparation technology, has shortened the production cycle; Simultaneously, owing to having saved the processing step of making protective layer, only there is the first passivation layer being formed by photosensitive resin, because resin material itself is compared with the protective layer material such as silicon nitride, silica, there is high transmission rate, low-k, easily apply smooth characteristic, thereby high transmission rate can makes more light through substrate power saving, low-k can reduce electric capacity, the quantity of electric charge of storage is few, and logic power consumption is just little, thereby has promoted the transmitance of the first passivation layer; In addition, in etching process, do not relate to different materials, only have same etching speed, avoided the bad defect of chamfering.
In the time that described the first passivation layer adopts silicon nitride material to form:
The described first composition technique of passing through forms source electrode, drain electrode, data wire on the first metal layer, and on the first passivation layer, form the first passivation layer via hole and comprise: on described the first passivation layer, apply photoresist, after mask, expose, develop, described the first passivation layer and the first metal layer are carried out to etching simultaneously, form source electrode, drain electrode; Then described photoresist is carried out to ashing, expose the silicon nitride of the first passivation layer via hole position; Again the silicon nitride of described the first passivation layer via hole position is carried out to etching;
Or,
On described the first passivation layer, apply photoresist, after mask, expose, develop, described the first passivation layer is carried out to etching, form the first passivation layer via hole, expose the first metal layer; Again described the first metal layer is carried out to etching, form source electrode, drain electrode; Then described photoresist is carried out to ashing, expose the silicon nitride of the first passivation layer via hole position; Again the silicon nitride of described the first passivation layer via hole position is carried out to etching;
In addition, when described active layer is to comprise the bilayer film of amorphous silicon membrane and doped silicon film or comprise metal oxide semiconductor films and when the bilayer film of doped silicon film, in the first composition technique, described the silicon nitride of the first passivation layer via hole position is carried out to etching in, etching is carried out in the corresponding position of raceway groove between described doped silicon film and source electrode and drain electrode.
Further, above-mentioned preparation method also comprises:
On underlay substrate, form the second metal level, form grid and grid line by the 3rd composition technique, wherein, the metal that the second metal level adopts comprises copper, molybdenum aluminium molybdenum or aluminium molybdenum;
On the second metal level, form gate insulation layer forming before active layer, by the 4th composition technique position formation grid insulating layer through hole corresponding with the described grid line of driving thin-film transistor position that is positioned at substrate periphery on described gate insulation layer; Wherein, the material that gate insulation layer adopts can be SiNx, SiOx, SiNx/SiOx etc.; Grid insulating layer through hole is for connecting the data wire of grid line and the first metal layer.
On the substrate that is formed with described the second metal level, gate insulation layer, active layer, the first metal layer and the first passivation layer, form pixel electrode by the 5th composition technique; Wherein, the material of pixel electrode can be tin indium oxide.
On the first passivation layer and pixel electrode, form the second passivation layer, and the position corresponding with the first passivation layer via hole forms the second passivation layer via hole by the 6th composition technique on described the second passivation layer; Wherein, the second passivation layer is the bilayer film of silicon nitride film, silicon oxide film or silicon nitride and silica, and described the second passivation layer via hole has been used for the lead-in wire of pixel electrode.
On the substrate that is formed with described the second passivation layer, form public electrode by the 7th composition technique; Wherein, the material of public electrode can be tin indium oxide.
Illustrate the first embodiment of the present utility model below in conjunction with accompanying drawing.
Fig. 1 is the schematic cross-section that array base palte is formed with grid and grid line.As shown in Figure 1, depositing Al Nd/Mo metallic film on substrate 1, forms grid 3 and grid line 2 by the 3rd composition technique.
Fig. 2 is the schematic cross-section that array base palte is formed with gate insulation layer and active layer.As shown in Figure 2, on grid 3 and grid line 2, deposited silicon nitride forms gate insulation layer 4, amorphous silicon (a-Si) film 5, doped silicon (n+Si) film 6 successively, on a-Si film, n+Si film, forms active layer by the second composition technique.
Fig. 3 is the schematic cross-section that array base palte is formed with grid insulating layer through hole.As shown in Figure 3, form grid insulating layer through hole by the 4th composition technique, complete the making of the grid insulating layer through hole of the capable driving of array base palte (Gate Driver on Array is called for short GOA) functional unit.
Figure 11 a is the schematic cross-section that the array base palte of the utility model the first embodiment is formed with the first metal layer.As shown in Figure 11 a, depositing Al/Mo metal level on active layer, now, the a-Si film of raceway groove place active layer is covered by metal level, thereby can well protect the active layer at raceway groove place, temporarily plays the effect of protective layer; Figure 11 b is the vertical view that the array base palte of the utility model the first embodiment is formed with the first metal layer.As shown in Figure 11 a and 11b, Al/Mo metal level is carried out to etching, the Al/Mo metal level after etching comprises the metal level part that is used to form source electrode 7, drain electrode 10 and data wire 8, comprises the metal level part that covers raceway groove top simultaneously.Now do not carry out the making of source electrode 7, drain electrode 10, data wire 8, the first metal layer temporarily plays a very good protection to active layer.
Compared with prior art; the making that in the utility model the first embodiment, the preparation method of array base palte has saved protective layer; therefore; further reduce cost, not only avoided the active layer at raceway groove place to be subject to the impact of photosensitive resin material, and avoided the bad problem of grid insulating layer through hole chamfering forming simultaneously; promote the transmitance of light; the power consumption that reduces backlight, has shortened fabrication cycle, has promoted volume production.
Figure 12 a is the schematic cross-section that the array base palte of the utility model the first embodiment is formed with the first passivation layer.As shown in Figure 12 a, on the first passivation layer 9, apply photoresist 15, after mask, expose, develop.Figure 12 b is the schematic cross-section that the array base palte of the utility model the first embodiment is formed with source electrode, drain electrode, data wire and the first passivation layer via hole, and Figure 12 c is the vertical view that the array base palte of the utility model the first embodiment is formed with source electrode, drain electrode and the first passivation layer via hole.As shown in Figure 12 b and Figure 12 c, by the first composition technique, the first passivation layer 9 and the first metal layer are carried out to etching simultaneously, form source electrode 7, drain electrode 10, data wire 8 and the first passivation layer via hole, the n-Si film corresponding with the position of channel region carried out to etching simultaneously.Now, under the prerequisite of protection drain electrode 7, form source electrode 7, drain electrode 10 and data wire 8, also completed and drained 7 and the making of the first passivation layer via hole of grid insulating layer through hole opposite position.
Figure 13 a is the schematic cross-section that the array base palte of the utility model the first embodiment is formed with pixel electrode, and Figure 13 b is the vertical view that the array base palte of the utility model the first embodiment is formed with pixel electrode.As shown in Figure 13 a and Figure 13 b, first deposit indium tin oxide films, be mask post-exposure, development, etching by the 5th composition technique, obtain pixel electrode 11.Wherein, be with existing technique difference; when the indium tin oxide layer corresponding with raceway groove position carried out to etching; adjust the selection ratio of etching liquid to Al/Mo metal level and indium tin oxide layer; make an etching oxidation indium tin layer and non-etching Al/Mo metal level; therefore, can well protect source electrode 7, drain electrode 10, can not cause loose contact.
Figure 14 is the schematic cross-section that the array base palte of the utility model the first embodiment is formed with the second passivation layer and the second passivation layer via hole.As shown in figure 14, on the substrate that completes abovementioned steps, deposition SiNx film, as the second passivation layer 12, is mask post-exposure, development, etching by the 6th composition technique, makes the second passivation layer via hole at the periphery of array base palte, completes lead-in wire.
Figure 15 is the schematic cross-section that the array base palte of the utility model the first embodiment is formed with public electrode.As Figure 15 shows, on the substrate that completes abovementioned steps, deposition indium tin oxide films, is mask post-exposure, development, etching by the 7th composition technique, thereby obtains public electrode 13.
In a second embodiment, basic step is identical with the first embodiment, and its difference is, the first passivation layer employing silicon nitride material.Figure 16 a, Figure 16 b, Figure 16 c are depicted as the making of the first passivation layer taking silicon nitride as material, now, compared with prior art, need to adjust mask process.
Figure 16 a is the schematic cross-section that the utility model the second embodiment array base palte is formed with the first passivation layer, Figure 16 b is the schematic cross-section that the utility model the second embodiment array base palte is formed with source electrode, drain electrode and the first passivation layer via hole, and Figure 16 c is the vertical view that the utility model the second embodiment array base palte is formed with source electrode, drain electrode and the first passivation layer via hole.As shown in Figure 16 a, 16b and 16c, the array base palte taking silicon nitride as the first passivation layer 9 is carried out to the making of source electrode, drain electrode and the first passivation layer via hole, can adopt following two schemes:
Scheme one, on the first passivation layer 9, apply photoresist 15, after mask, expose, develop, the first passivation layer 9 and the first metal layer are carried out to etching simultaneously, form source electrode 7, drain electrode 10; Then photoresist is carried out to ashing, expose the silicon nitride of the first passivation layer via hole position; Again the silicon nitride of the doped silicon film position corresponding with raceway groove and the first passivation layer via hole position is carried out to etching, the etching selection ratio of adjusting n-Si and silicon nitride is 1:7, thereby ensures effective etching n-Si film and silicon nitride;
Or,
On the first passivation layer 9, apply photoresist 15, after mask, expose, develop, the first passivation layer 9 is carried out to etching, form the first passivation layer via hole, expose the first metal layer; Again the first metal layer is carried out to etching, form source electrode, drain electrode; Then photoresist is carried out to ashing, expose the silicon nitride of the first passivation layer via hole position; Again the silicon nitride of the doped silicon film position corresponding with raceway groove and the first passivation layer via hole position is carried out to etching.The etching selection ratio of adjusting n-Si and silicon nitride is 1:7, thereby ensures effective etching n-Si film and silicon nitride.
Now, under the prerequisite of protection drain electrode 7, form source electrode 7, drain electrode 10 and data wire 8, also completed and drained 7 and the making of the first passivation layer via hole of grid insulating layer through hole opposite position.
In the 3rd embodiment, basic step is identical with the first embodiment, its difference is, the the second composition technique that forms active layer is merged into composition technique one time with the 4th composition technique that forms grid insulating layer through hole, adopt slit exposure technology or half mask technique, photoresist is carried out to ashing, thereby expose active layer region, by the disposable making that completes active layer and grid insulating layer through hole of the second composition technique.
The array base palte that the utility model embodiment provides comprises: underlay substrate; On described underlay substrate, be provided with source electrode, drain electrode and data wire, described source electrode, drain electrode and data line bit are on the first metal layer; On described the first metal layer, be coated with the first passivation layer, on described the first passivation layer, be provided with the first passivation layer via hole.
Also comprise active layer, active layer is arranged under described the first metal layer, and described active layer is amorphous silicon membrane or metal oxide semiconductor films or comprises amorphous silicon membrane and the bilayer film of doped silicon film or comprise metal oxide semiconductor films and the bilayer film of doped silicon film;
Also comprise:
The second metal level of grid and grid line, described the second metal level is covered on described underlay substrate;
The gate insulation layer of grid insulating layer through hole, described gate insulation layer is covered on described the second metal level and is positioned under active layer;
Pixel electrode, described pixel electrode is positioned on described the first passivation layer;
The second passivation layer of the second passivation layer via hole, described the second passivation layer is covered on described the first passivation layer and described pixel electrode;
Public electrode, described public electrode is positioned on the second passivation layer;
Wherein, described grid insulating layer through hole is for connecting the data wire of grid line and the first metal layer; Described the second passivation layer via hole has been used for the lead-in wire of pixel electrode.
The utility model embodiment also provides a kind of display unit that comprises described array base palte.Described display unit; its array base palte has saved protective layer; improve image quality brightness; further reduce use power consumption; saved the processing step of making protective layer simultaneously; source electrode, drain electrode, data wire and the first passivation layer via hole complete in same step simultaneously, have reduced cost, have promoted volume production.
The above, be only preferred embodiment of the present utility model, is not intended to limit protection range of the present utility model.
Claims (5)
1. an array base palte, is characterized in that, comprises underlay substrate; On described underlay substrate, be provided with source electrode, drain electrode and data wire, described source electrode, drain electrode and data line bit are on the first metal layer; On described the first metal layer, be coated with the first passivation layer, on described the first passivation layer, be provided with the first passivation layer via hole.
2. array base palte as claimed in claim 1, is characterized in that, also comprises active layer, and described active layer is arranged under described the first metal layer.
3. array base palte as claimed in claim 2, it is characterized in that, described active layer is adopt the film that amorphous silicon or metal oxide semiconductor material make or comprise and adopt the bilayer film that amorphous silicon membrane and doped silicon film material make or comprise the bilayer film that adopts metal oxide semiconductor films and doped silicon film material to make.
4. the array base palte as described in claims 1 to 3 any one, is characterized in that, also comprises:
The second metal level of grid and grid line, described the second metal level is covered on described underlay substrate;
The gate insulation layer of grid insulating layer through hole, described gate insulation layer is covered on described the second metal level and is positioned under described active layer;
Pixel electrode, described pixel electrode is positioned on described the first passivation layer;
The second passivation layer of the second passivation layer via hole, described the second passivation layer is covered on described the first passivation layer and described pixel electrode;
Public electrode, described public electrode is positioned on the second passivation layer;
Wherein, described grid insulating layer through hole is for connecting the data wire of grid line and the first metal layer; Described the second passivation layer via hole has been used for the lead-in wire of pixel electrode.
5. a display unit, is characterized in that, comprises the array base palte described in claim 1 to 4 any one.
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| CN201320845061.9U CN203659865U (en) | 2013-12-19 | 2013-12-19 | Array substrate and display device |
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| CN201320845061.9U CN203659865U (en) | 2013-12-19 | 2013-12-19 | Array substrate and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576526A (en) * | 2013-12-19 | 2015-04-29 | 北京京东方光电科技有限公司 | Array substrate and preparation method thereof as well as display device |
| WO2016206163A1 (en) * | 2015-06-26 | 2016-12-29 | 深圳市华星光电技术有限公司 | Thin film transistor, array substrate and liquid crystal display panel |
-
2013
- 2013-12-19 CN CN201320845061.9U patent/CN203659865U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576526A (en) * | 2013-12-19 | 2015-04-29 | 北京京东方光电科技有限公司 | Array substrate and preparation method thereof as well as display device |
| CN104576526B (en) * | 2013-12-19 | 2018-07-17 | 北京京东方光电科技有限公司 | A kind of array substrate and preparation method thereof and display device |
| WO2016206163A1 (en) * | 2015-06-26 | 2016-12-29 | 深圳市华星光电技术有限公司 | Thin film transistor, array substrate and liquid crystal display panel |
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