CN115469702A - Power supply circuit, corresponding device and method - Google Patents

Abstract

Embodiments of the present disclosure relate to power supply circuits, corresponding devices and methods. A voltage regulator coupled between a first node and a second node includes a first (full power) regulator circuit and a second (low power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit not activated) when the voltage at the first node is the battery voltage, and the voltage regulator remains deactivated when the voltage at the first node is the ground voltage. In a second mode: the first regulator circuit is active (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuit is active (with the first regulator circuit inactive) regardless of whether the voltage at the first node is at the battery voltage or the ground voltage.

Description

Power supply circuit, corresponding device and method

Cross Reference to Related Applications

The present application claims priority to italian patent application No. 102021000015176 filed on 10/6/2021, the contents of which are incorporated by reference herein in their entirety to the maximum extent allowed by law.

Technical Field

The present description relates to power supply circuits.

One or more embodiments may be applied to a variety of products, such as, for example, industrial electronics applications, mass market applications (e.g., in the internet of things or internet of things environments), various embedded applications, and so forth.

Background

In operation, voltage regulators configured to support "high voltage" capability (e.g., at 4.5V), such as Low Dropout (LDO) regulators, may cause significant junction temperature increases that in some cases make the use of such regulators nearly infeasible.

It is further noted that in certain circumstances, such high pressure capability of the regulator may not be necessary and may therefore be redundant.

Thus, increased flexibility in configuring a device power scheme according to specific application requirements represents a desirable feature.

Therefore, there is a need in the art for a solution to the above-mentioned problems.

Disclosure of Invention

One or more embodiments relate to a circuit.

One or more embodiments relate to a corresponding system. A microcontroller unit (MCU) with an associated (external) memory, e.g. a flash memory, may be an example of such a device.

One or more embodiments may relate to a corresponding method.

One or more embodiments provide the possibility to select whether a voltage regulator (e.g. an embedded LDO regulator) needs to be activated at power-on and becomes available for controllably switching off in common with an associated control circuit in order to save power.

One or more embodiments provide the possibility to select a desired power supply scheme based on application requirements in terms of e.g. power consumption, battery power range and thermal performance, and reduce power consumption and semiconductor area costs.

One or more embodiments may provide a flexible provisioning scheme that allows for various operating conditions, such as: a single power supply at 4.5V with an external load (such as an external memory) supplied by a supply voltage in the range of 1.8V-3.3V; a dual power supply at 4.5V/3.6V with an external load supplied by a supply voltage in the range of 1.8V-3.6V; and a single power supply at 3.6V with an external load supplied by a supply voltage of 2.5V-3.6V.

The number diagrams given above are purely exemplary and do not limit the embodiments.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a general block diagram of a circuit;

FIGS. 2 and 3 are exemplary block diagrams of conventional arrangements employed in connection with the circuit shown in FIG. 1;

FIG. 4 is a block diagram illustrating certain heat dissipation issues that may arise in a power supply circuit including an embedded voltage regulator;

FIGS. 5, 6, and 7 are examples of different operating conditions supported by embodiments of the present description;

FIG. 8 is an exemplary block diagram of an embodiment of the present description; and

fig. 9 is an exemplary diagram of possible modes of operation of an embodiment.

Detailed Description

Corresponding numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated.

The drawings are drawn for clarity of illustrating relevant aspects of the embodiments and are not necessarily to scale.

Edges of features drawn in the figures do not necessarily indicate the end of the range of the feature.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various examples according to the described embodiments. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to not obscure aspects of the embodiments.

Reference to "an embodiment" or "one embodiment" within the framework of the description is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment," "in one embodiment," and the like that may be present in various points of the present description do not necessarily refer to one embodiment and the same embodiment with certainty. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The headings/references used herein are provided for convenience only and thus do not define the scope of protection or the scope of the embodiments.

For the sake of brevity and simplicity, the same names (e.g., VBAT, VDDIO, etc.) may be used below to designate both a certain circuit node or a certain line and signals (e.g., voltage signals) present at that node or line.

Fig. 1 is a simplified representation of a circuit 10, such as, for example, a microcontroller unit or MCU, powered by a power source such as a battery LB.

A (rechargeable) lithium ion battery may be an example of the battery LB. Those skilled in the art will appreciate that the embodiments are not limited to the presence of such a battery, which is a different element from the embodiments. For example, the battery LB may be a battery intended to be coupled ("plugged in") to the circuit 10 only by an end user and/or for a limited period of time.

A battery such as LB is representative of a power supply configured to apply a supply voltage between the "hot" node VDD and ground GND to the circuit 10.

As mentioned above, although batteries such as modern rechargeable lithium ion batteries have operating voltages up to 4.5V and (slightly) higher charging voltages, most commercial technologies do not include devices capable/required to operate above 3.6V.

Reaching higher voltages involves the use of "high voltage" circuits, which can be quite complex and increase semiconductor area occupancy, cost, and power consumption.

Fig. 2 is an example of one such conventional approach, in which an (external) voltage Regulator (REG) 12 is provided between the battery LB and a node VDD in the circuit 10, with a coupling capacitor 14 provided between the node VDD and ground GND.

The arrangement shown in fig. 2 presents the problem of additional components that negatively impact the bill of materials (BoM) as size, complexity and cost increase.

A further disadvantage relates to increased power consumption in the active mode as well as in the low power (quiescent) mode.

All of the above makes the solution illustrated in fig. 2 hardly attractive for applications such as internet of things (IoT) applications where it is desirable to reduce consumption in low power mode.

Another conventional approach, as shown in fig. 3, is based on a system-on-a-chip (SoC) architecture, in which a regulator 12 is "embedded" in a circuit 10, wherein input/output (I/O) analog circuitry 16 is provided that is similarly embedded in the circuit 10. The decoupling capacitor 14 may be arranged between the ground GND and a node intermediate the embedded regulator 12 and the circuit arrangement 16.

Although providing somewhat better performance, the arrangement shown in fig. 3 has essentially the same disadvantages as discussed in connection with fig. 2.

One or more embodiments described below address the shortcomings discussed above in connection with fig. 2 for the embedded layout illustrated in fig. 3.

For this reason, unless the context indicates otherwise, the general disclosure provided above in connection with fig. 1-3 also applies to the other figures, and for the sake of brevity will not be repeated in connection with the figures preceding fig. 4.

The Regulator (REG) 100 may be a Low Dropout (LDO) regulator.

As described below (e.g., in conjunction with fig. 8), the regulator 100 may include a High Drive (HD) LDO circuit arrangement designated 102, and a Low Power (LP) LDO circuit arrangement designated 104.

LDOs are an acronym for "low drop out" and specify a DC linear voltage regulator architecture that is configured to regulate its output voltage (even) when the voltage provided to it is very close to the output voltage.

The use of embedded voltage regulators, such as LDO regulators, may result in an increase in (junction) temperature in operation, which may trade-off such regulators in certain extreme cases.

In this regard, reference may be made to the diagram of fig. 4, wherein portions of elements corresponding to portions or elements already discussed in connection with the previous diagram are designated with corresponding reference numerals unless context indicates otherwise.

As shown in fig. 4, the regulator 100 is configured to operate between: the first node VBAT is configured to have applied to it a voltage from a power source (e.g., 4.5V from a battery), and the second node IOVDD is configured to supply power to an external device designated ED via line 180.

Decoupling capacitor 14 may be disposed between node IOVDD (line 180) and ground.

Another node designated VDDIO is coupled to line 180, where nodes IOVDD and VDDIO are arranged "upstream" and "downstream" of capacitor 14.

The node VDDIO may be intended to provide a voltage supply for a circuit arrangement such as 16 included in the circuit 10.

For example, VDDIO may be the primary power supply node for the entire circuit 10 (e.g., microcontroller) except for the subsystems that are directly connected to VBAT.

The device ED designated "external" emphasizes that this may represent a different element from the circuit 10. A memory, such as a flash memory, coupled to an MCU, such as 10, may be an example of such an external device ED.

For the sake of illustration, it may be assumed that the circuit 10 is configured to cooperate with an external device ED via a set of I/O nodes (pins) 18.

Thus, the LDO regulator 100 receives a voltage, e.g., a voltage of 4.5V, at node VBAT. This is a voltage that may be provided from a battery coupled between node VBAT and ground GND.

The (regulated) supply voltage applied to external device ED (via line 180) and to node VDDIO would be expected to be low, in the range of 1.8V-3.3V.

In fig. 4, reference numeral 16 designates a circuit arrangement of an analog type, such as an RF (radio frequency) circuit arrangement, for example.

It should further be understood that the particular characteristics and mode of operation of the circuit arrangement 16 and the particular characteristics and mode of operation of the external device ED coupled to the circuit 10 are not relevant to the embodiments.

Thus, embodiments may be considered substantially "transparent" to certain characteristics and mode operations of the circuit arrangement 16 and/or certain characteristics and mode operations of the external device ED.

As discussed, the use of an embedded voltage regulator such as LDO regulator 100 shown in fig. 4 may result in an increase in (junction) temperature in operation, which may be traded off against the use of such a regulator in certain extreme cases.

For example, if the battery voltage VBAT input to the regulator 100 reaches 4.5V and the regulated voltage at node IOVDD at the output of the regulator (when provided to the circuit ED) is set to 1.8V, the dissipated power H1 may be about 540mW: this is of course a pure example, since the actual dissipated power depends on the current, i.e. on the load.

Assuming a conventional value for package thermal resistance of about 35 ℃/W (as for current semiconductor device packages), this dissipated power may result in a corresponding temperature increase of about 19 ℃.

Possible heat dissipation H2 from circuit 16 (and other portions of circuit 10) may increase heat dissipation H1 from regulator 100.

For example, for the highest consumption mode of operation of a circuit such as circuit 16, the heat dissipation H2 from circuit 16 may be from a few mW up to 800mW.

The actual situation may depend on factors such as the voltage drop across regulator 100, the characteristics of the load (device ED), the heat generated by circuit arrangement 16, and so on.

As discussed, these factors are hardly feasible with voltage regulators such as embedded LDO regulators in contexts such as the one illustrated in fig. 4.

On the other hand, in some applications, the 4.5V supply may not be considered, and thus, in the end, voltage regulators such as regulator 100 may end up being redundant.

One or more embodiments contemplate the possibility of (virtually) "removing" (i.e., deactivating) an embedded voltage regulator such as regulator 100.

Fig. 5-7 illustrate various desired operating configurations for a circuit such as circuit 10.

Fig. 5 relates to a first "single supply" operating condition in which a supply voltage VBAT (e.g., 4.5V from battery LB) is applied to voltage regulator 100.

In this first operating condition, the voltage regulator 100 operates at an output node designated as IOVDD and provides a regulated supply voltage for an external device (e.g., memory) ED coupled via line 180, where the supply voltage provided by the regulator 100 is regulated within a range between, for example, 1.8V-3.3V. The same voltage may be applied to node VDDIO.

Fig. 6 and 7 relate to possible situations where voltage regulator 100 may be "removed" (i.e., deactivated).

In the "dual supply" operating condition of fig. 6 and 7, the external load ED (and node VDDIO) may be supplied: in the case shown in fig. 6, at a voltage of, for example, 1.8V-3.6V provided by an external (e.g., PCB-mounted) voltage regulator 12 (see also fig. 2), or in the case shown in fig. 7, at a voltage of, for example, 2.5V-3.6V derived from the battery LB.

Fig. 6 relates to a situation where a battery (e.g. up to 4.5V) such as a lithium ion battery is used and an embedded LDO such as LDO100 cannot be used for "hot" reasons (junction temperature is too high).

In this case, the external LDO12 is used to generate a voltage compatible with VDDIO (e.g., from 1.8V to 3.3V/3.6V) and a voltage compatible with an external device (e.g., ED).

Fig. 7 relates to the (application-dependent) case where the lithium-ion battery is not used and the voltage VBAT is in the range of 2.5V-3.3V/3.6V (these are only examples, not subject to hard limitations of the specifications of the circuits involved).

In this case, the same VBAT power supply can be used to power all circuits involved, i.e. all circuits and (RF) circuit arrangements 16 which are powered via the node VDDIO (e.g. microcontroller) plus External Devices (ED).

This case assumes, of course, that the power supply of the external circuit ED is compatible with the VBAT voltage range.

In summary, in FIG. 7, the voltage of 2.5-3.6V comes directly from the primary power source (e.g., battery).

It is again recalled that the numerical figures presented above are purely exemplary and not limiting on the embodiments.

The general idea is to provide the user with the possibility to adapt the configuration according to the specific application requirements, thereby allowing to obtain the desired cost/performance trade-off.

One or more embodiments address the problem of supporting different usage conditions, as illustrated in fig. 5, 6, and 7, while facilitating desired low power operation and performance.

To this end, the connection state of the circuit 10, corresponding for example to the RF circuit arrangement 16 being "OFF" (OFF state, i.e. all internal circuits in the circuit 10 are deactivated) and "on" (RUN state, i.e. all internal circuits in the circuit 10 are activated and running), is complemented by two new states, namely:

a first "off LDO" state, wherein, to support the operating conditions shown in fig. 5, the regulator 100 remains activated ("on") wherein a high drive mode and a low power mode may be supported (see high drive circuitry 102 and low power circuitry 104 in fig. 8) to obtain an optimized low power mode for the entire circuit, e.g., in the condition that circuitry 16 is deactivated, and

a second "run LDO" state in which circuit arrangement 16 runs with regulator 100 active, such that the entire circuit 10 (including regulator 100) is active.

In this way, even if, for example, RF circuitry 16 is in an off state, there is a possibility to activate LDO100, so that the rest of the system can be powered.

Accordingly, the circuit configurations shown in fig. 5 to 7 can be represented by the following tables.

Table I-Single Power supply (e.g., VBAT@4.5V and line 180/node VDDIO@1.8-3.3V-FIG. 5)

Table II-Dual supply (e.g., regulator 100 "remove", line 180/node VDDIO@1.8-3.6V-FIG. 6 or @ 2.5-3.6V-FIG. 7)

That is, in the single power mode of fig. 5 and table I above, the regulator 100 is activated in a startup state, e.g., in response to the battery LB being inserted.

In this state/condition, the voltage at node IOVDD gradually increases from zero to avoid damaging circuit ED. Further details in this regard can be gleaned from italian patent applications filed on the same day and assigned in part to the assignee of the present application.

In the dual power mode of fig. 6 and 7 and table II above, the regulator 100 may be (remain) off or deactivated in response to a control signal ctrl from a (always-on) control feature in the circuit arrangement 16, which may also enable the low power mode to reduce consumption.

In dual supply mode, LDO100 may remain permanently off. This can be achieved by grounding pin vbatlldo (see fig. 8).

In one or more embodiments, when the LDO regulator 100 is switched from a low power mode (circuit device 104 activated and circuit device 102 inactivated) to a high drive mode (circuit device 104 inactivated and circuit device 102 activated), corresponding information is available in the voltage domain with the signal LDO _ rdy from the control feature 16 asserted.

As shown in FIG. 8, the possibility that one or more embodiments provide whether to select an embedded regulator 100 would be:

START UP at power on (START UP, as described above) and become available for possible shutdown, with the signal Ido rdy asserted, indicating that the embedded regulator 100 is ready for high drive operation (high drive circuitry 102 activated and low power circuitry 104 deactivated), or

"removed" from the circuit 10 (i.e., remaining inactive-both the high-drive circuit means 102 and the low-power circuit means 104), in which case the power supply for the circuit 10 and the power supply for the external device ED may be provided by the external power source ES, as previously discussed.

As shown in fig. 8, a switch 22 (e.g., an electronic switch such as a MOSFET transistor) is provided and controlled by a signal LDO _ enable generated in a manner known per se to those skilled in the art to selectively disconnect the circuitry controlling the embedded regulator 100 (supplied via the low voltage regulator 24). In this way, further power savings may be obtained when the circuit is operated in a low power mode.

In fig. 8, AOVDD represents an internally generated power supply that facilitates control of LDO100 and other circuitry. If LDO is not needed, the power supply node/line AOVDD can be turned off in the low power mode in order to further reduce power consumption.

Fig. 8 also shows the possibility of coupling the node vbattldo of the regulator 100 to the (general) supply voltage VBAT (battery voltage at 4.5V, see e.g. the line designated IOVBAT in fig. 8) or to ground GND, so that the regulator 100 can be activated or "removed" from the circuit 10.

These options may be software controlled by the controller unit 10 itself, or take the form of wired logic.

The arrangement discussed herein may relate to a voltage regulator 100, the voltage regulator 100 including a high drive circuit arrangement 102, the high drive circuit arrangement 102 capable of generating 200mA at a voltage of 1.84V +/-6%, and a current energy of about 2mA for a low power circuit arrangement 104, wherein the regulated output voltage at the output node IOVDD is programmable (e.g., via software) in steps of 300mV over a range of, for example, 1.8V-3.3V.

Thus, the following operating conditions may occur as illustrated in blocks 1000, 1002, 1003, and 1004 in the graph of fig. 9.

Block 1000 (behavior at power-on, e.g. battery LB providing voltage VBAT is inserted into the circuit):

block 1002 (behavior when circuitry 16 is in the "run" state):

block 1003 (behavior when circuitry 16 is in an off (deactivated) state):

VBAT LDO = VBAT wherein the signal LDO _ enable is asserted (e.g., transition)

) (ii) a Switch with a switch body22 are closed and voltage regulator 100 switches to the low power mode (circuit device 102 is deactivated and circuit device 104 is activated).

Vbattlo = GND wherein the LDO _ enable signal is deasserted (e.g., transitioned)

) (ii) a Switch 22 is open with regulator 100 deactivated at both 102 and 104.

Block 1004 (behavior on exit from disconnected state):

wherein the circuit 16 asserts a corresponding signal Ido _ rdy, e.g., with transitions

The solution as previously discussed provides flexibility in configuring the device power scheme according to the particular application requirements and conditions of use.

For example, by noting that a "high voltage" power supply at 4.5V may be undesirable, one or more of the solutions discussed herein may take an "aggressive" approach to facilitating low power operation, thereby configuring the circuit for single supply operation at, for example, 3.6V.

Where a "high voltage" power supply at 4.5V is desired, either option can be selectively employed, by taking into account possible thermal issues, such as a single power supply at 4.5V (thermal issues are not expected) or dual power supplies at 4.5/3.6V (thermal issues are expected).

One or more embodiments facilitate control of an embedded voltage regulator, such as an LDO voltage regulator, to facilitate power settings when the regulator is disabled by resorting to an isolation approach when high voltage operation is not desired.

One or more embodiments facilitate selection of an appropriate power scheme based on specific application requirements in terms of power consumption, battery power range, and thermal performance.

The solution discussed herein helps achieve the goal of having reduced power consumption and reduced semiconductor area occupancy.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described purely by way of example, without thereby departing from the scope of protection.

The scope of protection is determined by the appended claims.

Claims (11)

1. A circuit, comprising:

a first node;

a second node configured to provide a supply of electrical power to an electrically powered device;

a voltage regulator coupled to the first node and configured to provide a regulated voltage to the second node, the voltage regulator including first regulator circuitry configured to provide full power operation of the voltage regulator and second regulator circuitry configured to provide low power operation of the voltage regulator;

wherein the circuitry is configured to:

i) Operating in a first mode of operation wherein: the first regulator circuit in the voltage regulator is active when the voltage at the first node is at a first voltage level, wherein the second regulator circuit is inactive, and the voltage regulator is held inactive when the voltage at the first node is at a second voltage level;

ii) operating in a second mode of operation, wherein: the first regulator circuit in the voltage regulator is active when the voltage at the first node is at the first voltage level, wherein the second regulator circuit is inactive, and the voltage regulator is inactive when the voltage at the first node is at the second voltage level, wherein both the first and second regulator circuits are inactive; and

iii) Operating in a third mode of operation, the second regulator circuit in the voltage regulator is active and the first regulator circuit is inactive regardless of whether the voltage at the first node is at the first voltage level or the second voltage level.

2. The circuit of claim 1, wherein the circuit is configured to switch from the third mode of operation to the second mode of operation in response to the voltage at the first node changing from the second voltage level to the first voltage level.

3. The circuit of claim 1, further comprising a control circuit for the voltage regulator, the control circuit configured to be turned off in response to the voltage regulator not being activated.

4. The circuit of claim 1, wherein the circuit is configured to issue a ready signal indicating that it is possible to switch from the second mode of operation to the third mode of operation in response to receiving a signal indicating a request for low power operation.

5. The circuit of claim 1, further comprising a power supply node configured to be coupled to the electrically powered device, wherein the power supply node is configured to be coupled to a power supply selected from the group consisting of: another voltage regulator external to the circuit and a voltage source at the first voltage level, the other voltage regulator coupled to the voltage source at the first voltage level.

6. The circuit of claim 1, wherein the first one of the voltage regulators is activated to the first mode of operation in response to a power supply coupled to the first node applying the first voltage level to the first node.

7. The circuit of claim 1, wherein:

the voltage regulator comprises a Low Dropout (LDO) regulator; and

the circuit comprises a microcontroller unit.

8. The circuit of claim 1, wherein the first voltage level is a battery voltage and the second voltage level is a ground voltage.

9. A system, comprising:

the circuit of claim 1, and

an electrically powered device coupled to the second node.

10. The system of claim 9, wherein the electrically powered device coupled to the second node comprises a memory.

11. A method of operating the circuit of claim 1, comprising:

coupling an electrically powered device to the second node; and

a power source is coupled to the first node.

Images