CN115454747A - Clock configuration test method, device, medium and electronic equipment - Google Patents
Clock configuration test method, device, medium and electronic equipment Download PDFInfo
- Publication number
- CN115454747A CN115454747A CN202211127836.9A CN202211127836A CN115454747A CN 115454747 A CN115454747 A CN 115454747A CN 202211127836 A CN202211127836 A CN 202211127836A CN 115454747 A CN115454747 A CN 115454747A
- Authority
- CN
- China
- Prior art keywords
- clock
- register
- value
- frequency
- configuration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a clock configuration test method, a clock configuration test device, a clock configuration test medium and electronic equipment. The test method comprises the following steps: acquiring a clock driving configuration file, wherein the clock driving configuration file comprises information of control registers of all clock channels in a chip; analyzing the clock driving configuration file to obtain clock identifications of all clocks, clock frequency parameters corresponding to each clock identification and configuration parameters of a control register; and testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to each clock identification are correct or not to obtain a test result. The testing method, the device, the medium and the electronic equipment which adopt the testing method can realize the item-by-item testing of the clock configuration parameters, and the verification of the integrity and the correctness of the clock configuration.
Description
Technical Field
The present invention relates to the field of terminal testing technologies, and in particular, to a method, an apparatus, a medium, and an electronic device for testing clock configuration.
Background
The development platform provides a clock interface for other drivers to obtain clock frequency, set clock frequency, enable clock and the like. The drivers that implement the clock interface are called clock drivers. The implementation principle of setting the frequency interface is to input the reference according to the input clock to be configured and the target frequency of the clock, convert the frequency value into a corresponding multi-path selection value and a frequency division value by combining a chip register manual, and then write the multi-path selection value and the frequency division value into a register corresponding to the clock. The frequency acquisition interface is realized by acquiring a multipath selection value and a frequency division value of the clock register according to the input parameters of the transmitted clock to be acquired, converting the frequency value into a corresponding clock frequency by combining a chip register manual, and returning the clock frequency to a caller. The enabling interface is realized by setting an enabling register of a clock according to an input parameter of the clock to be configured, so that a path switch of a clock path can be switched on or off according to needs. It can be seen that the configuration of a clock relates to the clock to which the multiplexer register address and to which one or more bits are allocated and which clock frequencies are supported; a divide register address and corresponding one or more bits; the register address and corresponding bit are enabled.
The clock path typically includes an optional variety of clock sources, a frequency divider, and a path switch. Specifically, the phase-locked loop generates a high frequency signal and, in turn, divides the clock of various frequencies for use by the module options as needed. The multi-way selection switch selects a clock with a certain frequency to be applied according to requirements. The frequency divider is used to divide the selected clock source to a smaller frequency according to the requirements. The path switch is used for controlling the output of the clock path to be applied.
The clock paths supported by current device chips, similar to the above paths, are hundreds and thousands of clock paths. The clock driver needs to package many clocks supported by the chip into an interface for other drivers to call. And the provided clocks are only interfaces, and the clock drivers are not called by themselves and are only called by other drivers. Each clock is involved with a number of information, including: the conditions of the multi-path selection register, the frequency division register, the enabling register and the supported frequencies, how to judge whether the information configuration related to the clock configured by the clock driver is correct or not and whether the information configuration has missing configuration or not are very important. However, the existing detection means only detects whether the clock driver is loaded successfully or not, the terminal cannot be started normally, the default frequency is read after the terminal is started or the current frequency of a certain clock is read manually, and there is no effective means for testing whether the information configured by the clock is correct or not or whether the information is omitted.
Disclosure of Invention
The invention aims to provide a method, a device, a medium and an electronic device for testing clock configuration, which are used for improving the problems of the integrity and the correctness of the clock configuration which are difficult to judge.
In a first aspect, the method for testing the clock configuration provided by the present invention includes: acquiring a clock driving configuration file, wherein the clock driving configuration file comprises information of control registers of all clock paths in a chip; analyzing the clock drive configuration file to obtain clock identifications of the clocks, clock frequency parameters corresponding to the clock identifications and configuration parameters of the control register; and testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to each clock identification are correct or not to obtain a test result.
The method provided by the invention has the beneficial effects that: the clock configuration can be tested by adopting a preset test flow, whether each item of parameter information of each clock to be tested is wrong or not is judged one by one according to the information in the configuration file, mismatching and missing matching conditions of the clock configuration are discovered in time, and the clock configuration can be debugged in time, so that the completeness and the correctness of the clock configuration are effectively realized.
In a possible embodiment, the obtaining a clock driving profile includes: obtaining a release version file of a chip, wherein the release version file comprises information of control registers of all clock paths in the chip;
and converting the release version file of the chip into a clock driving configuration file in an extensible markup language format.
The control register comprises a GATE register, a MUX register and a DIV register, and the configuration parameters of the control register comprise: register offset, occupied bit width, register address and clock enable interface;
in another possible embodiment, testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to the clock identifier of each clock are correct includes:
firstly, detecting whether the configuration parameters of the GATE register corresponding to the clock identification are correct or not;
then detecting whether the clock frequency parameter corresponding to the clock identification is correct or not;
and finally, detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct or not.
Detecting whether the configuration parameters of the GATE register corresponding to the clock identifier are correct, including:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock enabling interface of the target clock according to the clock handle to open the target clock;
calling an acquisition register interface to acquire an enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 1 or not;
calling a clock enabling interface of the target clock according to the clock handle to carry out closing operation on the target clock;
and calling an acquisition register interface to acquire the enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 0 or not.
In other possible embodiments, the detecting whether the clock frequency parameter corresponding to the clock identifier is correct includes:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifier;
and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
The detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct includes:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock frequency setting interface to set clock frequency according to the clock handle and the corresponding clock frequency value in the configuration file;
acquiring the value of a MUX register and the value of a DIV register by calling an acquisition register interface;
and judging whether the acquired value of the MUX register and the acquired value of the DIV register are consistent with the value of the MUX register and the value of the DIV register in the clock driving configuration file.
In a second aspect, the present invention also provides a clock configuration testing apparatus, including:
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a clock driving configuration file which comprises information of control registers of all clock paths in a chip;
the analysis unit is used for analyzing the clock drive configuration file to obtain clock identifications of all clocks, clock frequency parameters corresponding to each clock identification and configuration parameters of the control register;
and the test unit is used for testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to each clock identifier are correct or not to obtain a test result.
The device provided by the invention has the beneficial effects that: the clock configuration parameters can be tested item by item, so that the accuracy and the integrity of the clock configuration can be verified. The mismatching and missing matching conditions of the clock configuration can be found in time, and the clock configuration can be debugged in time conveniently.
The acquiring unit acquires a clock driving configuration file, and is specifically configured to:
acquiring a release version file of a chip, wherein the release version file comprises information of control registers of all clock paths in the chip;
and converting the release version file of the chip into a clock driving configuration file in an extensible markup language format.
The control register comprises a GATE register, a MUX register and a DIV register, and the configuration parameters of the control register comprise: register offset, occupied bit width, register address and clock enable interface;
the test unit tests whether the configuration parameter and the clock frequency parameter of the control register corresponding to each clock identifier are correct, and is specifically configured to:
firstly, detecting whether the configuration parameters of the GATE register corresponding to the clock identification are correct or not;
then detecting whether the clock frequency parameter corresponding to the clock identification is correct or not;
and finally, detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct or not.
The test unit detects whether the configuration parameter of the GATE register corresponding to the clock identifier is correct, and is specifically configured to:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock enabling interface of the target clock according to the clock handle to open the target clock;
calling an acquisition register interface to acquire an enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 1;
calling a clock enabling interface of the target clock according to the clock handle to close the target clock;
and calling an acquisition register interface to acquire the enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 0.
The test unit detects whether the clock frequency parameter corresponding to the clock identifier is correct, and is specifically configured to:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifier;
and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
The test unit detects whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct, and is specifically configured to:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock frequency setting interface to set clock frequency according to the clock handle and the corresponding clock frequency value in the configuration file;
acquiring the value of a MUX register and the value of a DIV register by calling an acquisition register interface;
and judging whether the acquired value of the MUX register and the acquired value of the DIV register are consistent with the value of the MUX register and the value of the DIV register in the clock driving configuration file.
In a third aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the method for testing the clock configuration.
In a fourth aspect, the present invention further provides an electronic device, including: a processor and a memory; the memory is used for storing a computer program; the processor is used for executing the computer program stored in the memory so as to enable the electronic equipment to execute the testing method of the clock configuration.
As for the advantageous effects of the above second to fourth aspects, reference may be made to the description of the above first aspect.
Drawings
Fig. 1 is a schematic flowchart of a method for testing clock configuration according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating another clock configuration testing method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock configuration testing apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, embodiments of the present invention provide a method, an apparatus, a medium, and an electronic device for testing clock configuration.
Example 1
The embodiment provides a test method of clock configuration. Referring to the attached figure 1 of the specification, the method comprises the following steps:
s101, obtaining a clock driving configuration file, wherein the clock driving configuration file comprises information of control registers of all clock paths in a chip.
The specific manner of obtaining the clock driving configuration file may include: acquiring a release version file of the chip, wherein the release version file comprises information of control registers of all clock paths in the chip; and converting the release version file of the chip into a clock driving configuration file in an extensible markup language format.
S102, analyzing the clock driving configuration file to obtain clock identifications of the clocks, clock frequency parameters corresponding to the clock identifications and configuration parameters of the control register.
S103, testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to each clock identification are correct or not to obtain a test result.
In S103, in a possible embodiment, testing whether the configuration parameter and the clock frequency parameter of the control register corresponding to each clock identifier are correct specifically includes: firstly, detecting whether the configuration parameters of a GATE register (enabling register) corresponding to a clock identifier are correct or not; then detecting whether the clock frequency parameter corresponding to the clock identification is correct or not; and finally, detecting whether the configuration parameters of the MUX register (multi-path selection register) and the DIV register (frequency division register) corresponding to the clock identification are correct or not.
In a specific embodiment, the information of the control register of each clock path included in the chip in the release version file is generally stored in the form of a table, and a corresponding identifier needs to be set in the table and the file in the xml format so that the table supports conversion into a specific xml file. In this embodiment, converting the release version file of the chip into the clock driving configuration file in the xml format includes: and presetting a specific extensible markup language format structuralization processing code in the terminal to realize the extensible markup language format structuralization processing of the table, so that the table is converted into a file in a specific extensible markup language format.
In the present embodiment, the extensible markup language (XML) format is as follows:
TABLE 1
Therefore, the clock parameter after the structured processing of the extensible markup language format supports the item name differentiation and the configuration of each subsystem (such as sub-modules of GPU, camera, CPU and the like).
In this embodiment, after the xml format structuring process:
clk config is used to configure a specific clock, including the clock name, such as name = "gpu _ core".
clock _ id: xml is mapped with the respective clock associations of the code configuration and clock id. The format occupies 4 bytes, the upper 2 bytes are sys identifiers, and the lower 2 bytes are clock identifiers under specific sys. Such as 0x00010005:0001 represents a sys;0005 represents a certain clock of the sys.
The enable switch corresponds to the gate register address and control bit, e.g., bit3 at 0x8000000 address is used to control switch enable, then gate _ reg =0x8000000, bit_eb =3.
mux register address and control bit, where shift is the bit offset and width is the bit width (number of bits). If 3 bits in total are used to control the mux _ reg =0x8000004, mux _shift =0, mux _width =3, for bit [2 ] of the 0x80000004 address.
div register address and control bit, where shift is the bit offset and width is the bit width (number of bits). If bit [4 ] of the address 0x80000004 is used to control mux selection, mux _ reg =0x8000004, mux _shift =3, mux _width =2.
Freq is the output frequency of various supported clock sources and div frequency division combination, and is also generated by table direct conversion. For a multi-channel clock source, a certain channel is selected by a multi-channel selection switch (setting the value of a MUX register), and frequency division is carried out by a frequency division coefficient (setting the value of a DIV register). The specific format is the output frequency and the corresponding values of the MUX register and DIV register. If the gpu _ core outputs 256M, according to freq = mux _ clk/(div + 1), mux is required to select 512M clock source, div =1; then freq =512000000, mux =2, div =1.
The clock driving configuration file is information acquired in advance, and when a device/terminal is tested for clock configuration, the clock driving configuration file comprises the following steps: the device/terminal is started, the clock driver is initialized, and the clock test module is initialized.
And then, analyzing the clock driving configuration file to obtain the clock identification of each clock, the clock frequency parameter corresponding to each clock identification and the configuration parameter of the control register. The control register comprises a GATE register, a MUX register and a DIV register, and the configuration parameters of the control register comprise: register offset, occupied bit width, register address and clock enable interface.
In another possible embodiment, detecting whether the configuration parameter of the GATE register corresponding to the clock identifier is correct includes: calling a clock enabling interface of the target clock according to the clock handle to open the target clock; calling an acquisition register interface to acquire an enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 1; calling a clock enabling interface of the target clock according to the clock handle to carry out closing operation on the target clock; and calling an acquisition register interface to acquire the enable bit of the GATE register according to the register address and the enable bit of the GATE register, and judging whether the value of the acquired enable bit is 0 or not.
In a possible embodiment, the determining whether the configuration parameter of the GATE register corresponding to the clock identifier is correct specifically includes: and according to whether the value of the corresponding bit of the target clock is 1 when the target clock is on and whether the value of the corresponding bit of the target clock is 0 when the target clock is off, calling an enabling interface of the target clock to carry out switching operation on the target clock, and determining whether the configuration parameters of the GATE register corresponding to the clock identification are correct when the target clock is on and off and the values of the corresponding bit of the target clock are correct respectively.
In the invention, a clock can support various frequencies, and when the clock frequency parameter corresponding to the clock identification is detected to be correct, the various supported frequencies corresponding to the clock identification need to be detected one by one. Specifically, whether one supporting frequency corresponding to a clock identifier is correct is detected, and then whether the supporting frequency corresponding to the clock identifier which is not detected exists is judged; if the judgment result is yes, detecting a supporting frequency corresponding to the clock identifier which is not detected, and if the judgment result is no, ending the operation of detecting whether the clock frequency parameter corresponding to the clock identifier is correct or not.
Detecting whether a supported frequency corresponding to the clock identifier is correct comprises: acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier; setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifier; and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
In a possible embodiment, detecting whether a supported frequency corresponding to the clock identifier is correct may further include: acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier; and calling a clock frequency setting interface to set the clock frequency according to the clock handle, calling a clock frequency acquiring interface to read the frequency, and confirming whether the set value is consistent with the acquired return value. If the supported frequency parameters corresponding to the clock identifications are not correct, if the supported frequency parameters are consistent, setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifications; and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
And when detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct, group-by-group detection needs to be carried out on the values of the MUX register and the DIV register corresponding to the clock frequency. Detecting whether a group of values of a MUX register and a DIV register corresponding to the clock frequency are correct or not, and then judging whether the MUX register and the DIV register which are not detected and correspond to the clock frequency exist or not; if the judgment result is yes, detecting the values of a group of MUX registers and DIV registers which are not detected and correspond to the clock frequency, and if the judgment result is no, finishing the operation of detecting whether the configuration parameters of the MUX registers and the DIV registers corresponding to the clock identifiers are correct or not.
In one possible embodiment, detecting whether a set of MUX register values and DIV register values corresponding to the clock frequency are correct comprises: acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier; calling a clock frequency setting interface to set the clock frequency according to the clock handle and the corresponding clock frequency value in the configuration file; acquiring the value of a MUX register and the value of a DIV register by calling an acquisition register interface; and judging whether the acquired value of the MUX register and the acquired value of the DIV register are consistent with the value of the MUX register and the value of the DIV register in the configuration file. And after the detection is finished, the test result of the clock configuration parameters is stored, and the result is used for program debugging analysis or test acceptance.
The chip may include a plurality of clocks, and after the configuration parameters and the clock frequency parameters of the control register corresponding to the clock identifier of one clock are correctly tested, it is determined whether clocks which are not tested for the configuration parameters exist in the configuration file. If the judgment result is yes, testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to the clock identification of the clock which is not tested are correct; if the judgment result is negative, the clock configuration test is finished.
In a possible embodiment, the test result is that a mismatch or a mismatch exists, the error position can be found according to the test result, the clock configuration code can be corrected through manual intervention, and the corrected clock configuration can be tested again by adopting the extensible markup language file until the clock configuration is complete and correct.
For a more systematic description of the test flow of the clock configuration, the present invention further describes the method in conjunction with the method embodiment shown in fig. 2.
S201, acquiring a clock driving configuration file to perform clock driving initialization, wherein the clock driving configuration file comprises information of control registers of each clock channel in the chip.
S202, analyzing the clock driving configuration file to obtain clock identifications of the clocks, clock frequency parameters corresponding to the clock identifications and configuration parameters of the control register.
And S203, according to the clock identification of each clock, performing traversal test on the test clocks one by one according to S204 to S207 until the last clock.
S204, detecting whether the configuration parameters of the GATE register corresponding to the clock identification are correct.
Specific detection methods refer to the above examples.
S205, detecting whether the clock frequency parameter corresponding to the clock identification is correct.
Specific detection methods refer to the above examples.
S206, detecting whether the configuration parameters of the MUX register and DIV register corresponding to the clock identification are correct.
Specific detection methods refer to the above examples.
And S207, storing the test result.
The clock configuration testing method can test the clock configuration by storing the clock parameter information in a specific extensible markup language format for calling the clock configuration parameter information in the clock configuration testing process, judge whether each parameter information of each clock is wrong one by one, find the mismatching and missing condition of the clock configuration in time and debug the clock configuration in time, thereby effectively realizing the integrity and the correctness of the clock configuration. Furthermore, the conditions that the development progress, the labor input and the like of other related modules are influenced by the error or the missing of the clock configuration can be avoided, the development efficiency and the project progress are improved, and the project cost is reduced. The clock configuration testing method can be used for testing the clock configuration supported by the chip of the terminal product such as a mobile phone, a tablet, a pos machine, an adult watch, a vehicle-mounted system and the like.
Example 2
Referring to the description of fig. 3, the present embodiment provides a clock configuration test apparatus, which is used for implementing the method described in embodiment 1. The device includes:
an obtaining unit 301, configured to obtain a clock driving configuration file, where the clock driving configuration file includes information of control registers of each clock path in the chip.
The obtaining unit 301 obtains the clock driving configuration file, specifically for: obtaining a release version file of the chip, wherein the release version file comprises information of control registers of all clock paths in the chip; and converting the release version file of the chip into a clock driving configuration file in an extensible markup language format.
The parsing unit 302 is configured to parse the clock driving configuration file to obtain the clock identifier of each clock, the clock frequency parameter corresponding to each clock identifier, and the configuration parameter of the control register. The control register comprises a GATE register, a MUX register and a DIV register, and the configuration parameters of the control register comprise: register offset, occupied bit width, register address and clock enable interface;
the test unit 303 is configured to test whether the configuration parameter and the clock frequency parameter of the control register corresponding to each clock identifier are correct, so as to obtain a test result.
The testing unit 303 tests whether the configuration parameter and the clock frequency parameter of the control register corresponding to each clock identifier are correct, and is specifically configured to: firstly, detecting whether the configuration parameters of the GATE register corresponding to the clock identification are correct or not; then detecting whether the clock frequency parameter corresponding to the clock identification is correct; and finally, detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct or not.
The test unit 303 detects whether the configuration parameter of the GATE register corresponding to the clock identifier is correct, and is specifically configured to: acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier; calling a clock enabling interface of the target clock according to the clock handle to open the target clock; calling an acquisition register interface to acquire an enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 1 or not; calling a clock enabling interface of the target clock according to the clock handle to carry out closing operation on the target clock; and calling an acquisition register interface to acquire the enable bit of the GATE register according to the register address and the enable bit of the GATE register, and judging whether the value of the acquired enable bit is 0 or not.
When the test unit 303 detects whether the clock frequency parameter corresponding to the clock identifier is correct, the test unit detects multiple support frequencies corresponding to the clock identifier one by one, and is specifically configured to: acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier; setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifier; and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
When the test unit 303 detects whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct, the test unit performs group-by-group detection on multiple groups of values of the MUX register and the DIV register corresponding to the clock frequency, and is specifically configured to: acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier; calling a clock frequency setting interface to set clock frequency according to the clock handle and the corresponding clock frequency value in the configuration file; acquiring the value of a MUX register and the value of a DIV register by calling an acquisition register interface; and judging whether the acquired value of the MUX register and the acquired value of the DIV register are consistent with the value of the MUX register and the value of the DIV register in the configuration file. All relevant contents of the steps related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.
In other embodiments of the present application, an embodiment of the present application discloses an electronic device, which may include, as shown in fig. 4: one or more processors 401; a memory 402; a display 403; one or more applications (not shown); and one or more computer programs 404, which may be connected via one or more communication buses 405. Wherein the one or more computer programs 404 are stored in the memory 402 and configured to be executed by the one or more processors 401, the one or more computer programs 404 comprising instructions that can be used to perform the steps as in fig. 1, fig. 2 and the corresponding embodiments.
Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.
Each functional unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application, in essence or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard drive, read only memory, random access memory, magnetic or optical disk, and the like.
The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
Claims (14)
1. A method of testing a clock configuration, the method comprising:
acquiring a clock driving configuration file, wherein the clock driving configuration file comprises information of control registers of all clock paths in a chip;
analyzing the clock drive configuration file to obtain clock identifications of the clocks, clock frequency parameters corresponding to the clock identifications and configuration parameters of the control register;
and testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to each clock identification are correct or not to obtain a test result.
2. The method of claim 1, wherein obtaining the clock driving profile comprises:
obtaining a release version file of a chip, wherein the release version file comprises information of control registers of all clock paths in the chip;
and converting the release version file of the chip into a clock drive configuration file in an extensible markup language format.
3. The method of claim 1, wherein the control registers include a GATE register, a MUX register, and a DIV register, and wherein the configuration parameters of the control registers include: register offset, occupied bit width, register address and clock enable interface;
testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to the clock identification of each clock are correct or not, wherein the testing comprises the following steps:
firstly, detecting whether the configuration parameters of the GATE register corresponding to the clock identification are correct or not;
then detecting whether the clock frequency parameter corresponding to the clock identification is correct or not;
and finally, detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct or not.
4. The method of claim 3, wherein detecting whether the configuration parameters of the GATE register corresponding to the clock identifier are correct comprises:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock enabling interface of the target clock according to the clock handle to open the target clock;
calling an acquisition register interface to acquire an enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 1;
calling a clock enabling interface of the target clock according to the clock handle to close the target clock;
and calling an acquisition register interface to acquire the enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 0.
5. The method of claim 3, wherein the detecting whether the clock frequency parameter corresponding to the clock identifier is correct comprises:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifier;
and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
6. The method of claim 3, wherein the detecting whether the configuration parameters of the MUX register and DIV register corresponding to the clock identifier are correct comprises:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock frequency setting interface to set clock frequency according to the clock handle and the corresponding clock frequency value in the configuration file;
acquiring the value of a MUX register and the value of a DIV register by calling an acquisition register interface;
and judging whether the acquired value of the MUX register and the acquired value of the DIV register are consistent with the value of the MUX register and the value of the DIV register in the clock driving configuration file.
7. An apparatus for testing a clock configuration, the apparatus comprising:
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a clock driving configuration file which comprises information of control registers of all clock paths in a chip;
the analysis unit is used for analyzing the clock drive configuration file to obtain clock identifications of all clocks, clock frequency parameters corresponding to each clock identification and configuration parameters of the control register;
and the test unit is used for testing whether the configuration parameters and the clock frequency parameters of the control register corresponding to each clock identifier are correct or not to obtain a test result.
8. The apparatus according to claim 7, wherein the obtaining unit obtains the clock driving configuration file, and is specifically configured to:
acquiring a release version file of a chip, wherein the release version file comprises information of control registers of all clock paths in the chip;
and converting the release version file of the chip into a clock driving configuration file in an extensible markup language format.
9. The apparatus of claim 7, wherein the control registers comprise a GATE register, a MUX register, and a DIV register, and wherein the configuration parameters of the control registers comprise: register offset, occupied bit width, register address and clock enable interface;
the test unit tests whether the configuration parameter and the clock frequency parameter of the control register corresponding to each clock identifier are correct, and is specifically configured to:
firstly, detecting whether the configuration parameters of the GATE register corresponding to the clock identification are correct or not;
then detecting whether the clock frequency parameter corresponding to the clock identification is correct or not;
and finally, detecting whether the configuration parameters of the MUX register and the DIV register corresponding to the clock identification are correct or not.
10. The apparatus according to claim 7, wherein the test unit detects whether the configuration parameter of the GATE register corresponding to the clock identifier is correct, and is specifically configured to:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock enabling interface of the target clock according to the clock handle to open the target clock;
calling an acquisition register interface to acquire an enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 1;
calling a clock enabling interface of the target clock according to the clock handle to close the target clock;
and calling an acquisition register interface to acquire the enabling bit of the GATE register according to the register address and the enabling bit of the GATE register, and judging whether the value of the acquired enabling bit is 0.
11. The apparatus of claim 7, wherein the test unit detects whether the clock frequency parameter corresponding to the clock identifier is correct, and is specifically configured to:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
setting the value of the MUX register and the value of the DIV register by calling a setting register interface according to the configuration parameters of the MUX register and the DIV register corresponding to the frequency of the clock identifier;
and calling a clock acquisition frequency interface to read the clock frequency according to the clock handle, and judging whether the acquired frequency value is consistent with the frequency value in the clock drive configuration file.
12. The apparatus of claim 7, wherein the test unit detects whether configuration parameters of the MUX register and the DIV register corresponding to the clock identifier are correct, and is specifically configured to:
acquiring a clock handle of a target clock corresponding to the clock identifier according to the clock identifier;
calling a clock frequency setting interface to set the clock frequency according to the clock handle and the corresponding clock frequency value in the configuration file;
acquiring the value of a MUX register and the value of a DIV register by calling an acquisition register interface;
and judging whether the acquired value of the MUX register and the acquired value of the DIV register are consistent with the value of the MUX register and the value of the DIV register in the clock driving configuration file.
13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a method of testing a clock configuration according to any one of claims 1 to 6.
14. An electronic device, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the memory-stored computer program to cause the electronic device to perform the method of testing the clock configuration of any of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211127836.9A CN115454747A (en) | 2022-09-16 | 2022-09-16 | Clock configuration test method, device, medium and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211127836.9A CN115454747A (en) | 2022-09-16 | 2022-09-16 | Clock configuration test method, device, medium and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115454747A true CN115454747A (en) | 2022-12-09 |
Family
ID=84305787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211127836.9A Pending CN115454747A (en) | 2022-09-16 | 2022-09-16 | Clock configuration test method, device, medium and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115454747A (en) |
-
2022
- 2022-09-16 CN CN202211127836.9A patent/CN115454747A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7707473B2 (en) | Integrated testing apparatus, systems, and methods | |
| US7926012B1 (en) | Design-For-testability planner | |
| US8943377B2 (en) | On-chip detection of types of operations tested by an LBIST | |
| KR20180082600A (en) | Front-end module for automated test equipment | |
| US10354031B2 (en) | Information processing by interpenetrating signal transmission channel in design for testability of chip | |
| JP2014532914A (en) | Programmable test equipment | |
| JP2015526700A (en) | System and method for executing a user-defined instrument command sequence using multiple hardware and analysis modules | |
| CN115656786B (en) | Chip detection method and device | |
| CN106201850A (en) | A kind of compatibility test method and device | |
| CN117787155B (en) | Chip testability code dynamic simulation test system and test method | |
| CN110134598B (en) | Batch processing method, device and system | |
| US20170277613A1 (en) | Multiple mode testing in a vector memory restricted test environment | |
| CN107861049B (en) | Automatic circuit board adjusting and testing method and system based on LabVIEW and spectrometer complete machine platform | |
| CN114356820A (en) | Acceleration method and device based on ATE equipment chip test and test machine system | |
| US20230367936A1 (en) | Verification method, electronic device and storage medium | |
| CN115454747A (en) | Clock configuration test method, device, medium and electronic equipment | |
| CN109902001B (en) | Method for detecting uninitialized variable and terminal equipment | |
| US8874968B1 (en) | Method and system for testing a processor designed by a configurator | |
| CN115964237A (en) | Method and device for testing functions and performance of Central Processing Unit (CPU) | |
| US20100058130A1 (en) | Processor to jtag test access port interface | |
| CN114385493A (en) | Performance test method and device, electronic equipment and storage medium | |
| CN114253784A (en) | Configuration method and device of chip test mode, SOC chip and electronic equipment | |
| CN114280459A (en) | Test method and device for integrated circuit | |
| US9568553B2 (en) | Method of integrated circuit scan clock domain allocation and machine readable media thereof | |
| CN115510779B (en) | Clock tree comprehensive processing method, device, equipment and medium based on chip design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |