CN117787159A

CN117787159A - Method and device for generating FPGA code, storage medium and electronic equipment

Info

Publication number: CN117787159A
Application number: CN202311843042.7A
Authority: CN
Inventors: 肖力; 刘志斌; 程国涛; 陈亚南; 王维
Original assignee: Silicon Valley Analog Suzhou Semiconductor Co ltd; Analogix International LLC
Current assignee: Silicon Valley Analog Suzhou Semiconductor Co ltd; Analogix International LLC
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-03-29

Abstract

The application provides a method and device for generating FPGA codes, a storage medium and electronic equipment. The method comprises the following steps: generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe; and calling a script program to read the register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model. Through the scheme, a set of complete automatic standard unified flow is formed, the FPGA codes and registers are automatically generated, and the problems of information errors and non-uniform standards of engineers in the design process and the communication and debugging process with the FPGA engineers are solved.

Description

Method and device for generating FPGA code, storage medium and electronic equipment

Technical Field

The application relates to the technical field of generating FPGA codes, in particular to a method, a device, a storage medium and electronic equipment for generating FPGA codes.

Background

With the high-speed development of integrated circuits, the scale of chips is larger and larger, and the research and development speed and reliability of chips are higher and higher. Both research and development departments and the customer market place strict demands on the research and development quality and speed of the chip, so in order to accelerate the research and development speed and discover hidden dangers and errors in the chip as soon as possible, the research and development departments generally select an FPGA as a tool for early functional verification and performance verification. The FPGA is used as a verification tool, so that the real application scene of the electronic chip can be simulated, and the function verification test is carried out on the chip codes; secondly, the chip hardware circuits can be laid out in advance, so that a system firmware engineer can write firmware codes conveniently, and early-stage pre-research and design can be carried out; thirdly, for some large-flow scenes which are long in simulation time consumption and need to accelerate simulation, the simulation speed and accuracy can be improved; and fourthly, before chip streaming, the FPGA development board can be delivered to a customer in advance, so that the application and popularization time is striven for the customer.

At present, a large chip research and development company can select a commercial FPGA prototype verification platform, such as a HAPS platform of New Si company. Because the large commercial FPGA prototype verification platform with the whole set of solution is expensive and complex in application, and special engineers are required for maintenance operation, in order to save time and cost, a small and medium chip company can adopt a general FPGA development board or a self-grinding FPGA development board as the prototype verification platform.

The adoption of a self-research or general FPGA verification platform is easy to cause the problem that the flow is not standard and the information transmission is lost due to human factors.

Disclosure of Invention

The main purpose of the application is to provide a method for generating FPGA codes, a device for generating FPGA codes, a storage medium, a processor and electronic equipment, so as to at least solve the problems that flow is not standard and information transmission is lost easily due to human factors when a self-research or general FPGA verification platform is adopted.

To achieve the above object, according to one aspect of the present application, there is provided a method of generating FPGA code, including: generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe; and calling a script program to read the register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model.

Optionally, after generating the unified RTL Verilog HDL logic code, FPGA probe signals, and UVM register model, the method further comprises: inputting the UVM register model to a UVM simulation platform, so that the UVM simulation platform outputs a register configuration file, a simulation waveform and simulation record information, wherein the simulation record information comprises information for recording simulation events and simulation operations, and the waveform parameters at least comprise waveform periods, waveform frequencies, waveform phases and waveform peaks; inputting the RTL Verilog HDL logic code, the FPGA probe signal and the register configuration file output by the UVM simulation platform to the FPGA test platform to obtain test waveforms and test record information, wherein the test record information comprises information for recording test events and test operations; comparing the simulation waveform with the test waveform to obtain a first comparison result, and comparing the simulation record information with the test record information to obtain a second comparison result; and verifying the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result.

Optionally, based on the first comparison result and/or the second comparison result, verifying the RTL Verilog HDL logic code includes: and determining that the RTL Verilog HDL logic code passes verification under the condition that the first comparison result indicates that the similarity of the simulation waveform and the test waveform is greater than a first similarity threshold and the second comparison result indicates that the similarity of the simulation record information and the test record information is greater than a second similarity threshold, wherein the verification passes the indication that the RTL Verilog HDL logic code meets the chip design requirement.

Optionally, inputting the UVM register model to a UVM simulation platform, where the UVM simulation platform is caused to output a register configuration file, including: operating a simulation environment of the UVM simulation platform, and instantiating the UVM register model and an RTL top layer module of the chip; after instantiating the UVM register model and the chip RTL top layer module, the UVM simulation platform outputs the register configuration file in a unified format with the FPGA test platform.

Optionally, before obtaining the test waveform and the test record information, the method further comprises: setting a logic analyzer of the FPGA test platform and a signal triggering condition, wherein the logic analyzer is a tool for grabbing the test waveform for the FPGA test platform, and the signal triggering condition is that a triggering signal meets a preset condition, and the triggering signal at least comprises a clock signal, a data reset signal and a functional switch signal.

Optionally, inputting the RTL Verilog HDL logic code, the FPGA probe signal, and the register configuration file output by the UVM simulation platform to the FPGA test platform, including: automatically adding a special descriptor into the RTL Verilog HDL logic code by using the FPGA probe signal so as to generate the RTL Verilog HDL logic code with the special descriptor; the special descriptor enables the FPGA test platform to generate test signal lines when the RTL Verilog HDL logic code is laid out and routed; and inputting the RTL Verilog HDL logic code with the special descriptor into the FPGA test platform.

Optionally, after the script program is invoked to read the register description file and generate the RTL Verilog HDL logic code, the FPGA probe signal, and the UVM register model of the unified specification, the method further comprises: after the script program is operated, the script program automatically generates operation record information of the script program operation, wherein the operation record information comprises script program operator information, operation time information and script program name information.

According to another aspect of the present application, there is provided an apparatus for generating FPGA code, comprising: the generating unit is used for generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a default value, an access attribute, a register description, a supplementary description and an FPGA probe; and the calling unit is used for calling the script program to read the register description file and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model.

According to still another aspect of the present application, there is provided a computer readable storage medium, where the computer readable storage medium includes a stored program, and when the program runs, the device in which the computer readable storage medium is located is controlled to execute any one of the methods for generating FPGA codes.

According to still another aspect of the present application, there is provided an electronic apparatus including: one or more processors, memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising a method for executing any of the generating FPGA code.

By applying the technical scheme, the register description file is generated according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe; and calling a script program to read the register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model. Through the scheme, a set of complete automatic standard unified flow is formed, the FPGA codes and registers are automatically generated, and the problems of information errors and non-uniform standards of engineers in the design process and the communication and debugging process with the FPGA engineers are solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 shows a block diagram of a hardware architecture of a mobile terminal that performs a method of generating FPGA code, provided in accordance with an embodiment of the present application;

FIG. 2 shows a flow diagram of a method of generating FPGA code provided in accordance with an embodiment of the present application;

FIG. 3 illustrates a flow chart of a method of generating FPGA code provided in accordance with an embodiment of the present application;

fig. 4 shows a schematic flow diagram of a UVM simulation platform provided according to an embodiment of the present application;

FIG. 5 shows a schematic diagram of a verification flow of FPGA code provided in accordance with an embodiment of the present application;

fig. 6 shows a block diagram of an apparatus for generating FPGA code according to an embodiment of the present application.

Detailed Description

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

For convenience of description, the following will describe some terms or terms related to the embodiments of the present application:

UVM simulation platform: is a unified verification method (Universal Verification Methodology) based on SystemVerilog for helping engineers to perform complex chip design verification and simulation. The method and the tool provide a set of standard verification method and tool, which can help engineers to perform verification work more quickly and efficiently, and improve reusability and maintainability of verification; the UVM simulation platform is widely applied to the field of semiconductor industry and integrated circuit design.

FPGA test platform: is a hardware platform for testing and verifying FPGAs (Field-Programmable Gate Array, field programmable gate arrays); these platforms typically include FPGA boards, test equipment, software tools, and other related components that can be used to perform functions verification, performance testing, timing analysis, etc. of the FPGA; the FPGA test platform can help developers and engineers to comprehensively test the FPGA in the design stage so as to ensure that the functions and performances of the FPGA meet the design requirements.

As introduced in the background art, in the prior art, the problems of nonstandard flow and information transmission loss caused by human factors are easily caused by adopting a self-research or universal FPGA verification platform, and in order to solve the problems of nonstandard flow and information transmission loss caused by human factors easily caused by adopting the self-research or universal FPGA verification platform, the embodiment of the application provides a method, a device, a storage medium and electronic equipment for generating FPGA codes.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of the mobile terminal according to a method for generating FPGA codes according to an embodiment of the present invention. As shown in fig. 1, a mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.

The memory 104 may be used to store computer programs, such as software programs of application software and modules, such as computer programs corresponding to the method of generating FPGA code in the embodiment of the present invention, and the processor 102 executes the computer programs stored in the memory 104 to perform various functional applications and data processing, that is, implement the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

In this embodiment, a method of generating FPGA code that runs on a mobile terminal, computer terminal, or similar computing device is provided, it should be noted that the steps illustrated in the flowchart of the figures may be performed in a computer system such as a set of computer executable instructions, and although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.

FIG. 2 is a flow chart of a method of generating FPGA code according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:

step S201, generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe;

the register description file is shown in table 1, table 1 further includes the following information, and the register reg_version address is 0x0, which is used for describing the version numbers of the FPGA and the chip; reg_staff is 0x1 to describe the engineer's work number; the reg_time address is 0x2 and is used for describing the code generation date and the specific clock; the reg_function address is 0x3 and is used for describing the chip functions which need to be started; reg_debug, reg_box addresses 0x0 and 0x1, are used to describe debug signals and debug data.

Table 1 register description table

Step S202, calling a script program to read a register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model.

Specifically, as shown in fig. 3, the calling program generates RTL Verilog HDL logic code, FPGA probe signals, and UVM register model of unified specification according to the detailed register description file; the FPGA probe signal can output debugging waveform and data information for the subsequent FPGA upper board test.

According to the embodiment, a register description file is generated according to chip design requirements, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe; and calling a script program to read the register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model. Through the scheme, a set of complete automatic standard unified flow is formed, the FPGA codes and registers are automatically generated, and the problems of information errors and non-uniform standards of engineers in the design process and the communication and debugging process with the FPGA engineers are solved.

In the specific implementation process, after the unified and normative RTL Verilog HDL logic code, the FPGA probe signal and the UVM register model are generated, the method further comprises the following steps: inputting the UVM register model to a UVM simulation platform, so that the UVM simulation platform outputs a register configuration file, a simulation waveform and simulation record information, wherein the simulation record information comprises information for recording a simulation event and a simulation operation, and the waveform parameters at least comprise a waveform period, a waveform frequency, a waveform phase and a waveform peak value; inputting the RTL Verilog HDL logic code, the FPGA probe signal and the register configuration file output by the UVM simulation platform to an FPGA test platform to obtain test waveforms and test record information, wherein the test record information comprises information for recording test events and test operations; comparing the simulation waveform with the test waveform to obtain a first comparison result, and comparing the simulation record information with the test record information to obtain a second comparison result; and verifying the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result.

The UVM simulation platform flow is shown in fig. 4, and the top layer of the simulation environment is a UVM _top module, which is responsible for instantiating a UVM register model automatically generated by an integrated script and UVM _env blocks, wherein the UVM _env blocks include an environment configuration (UVM _top), a comparison score indicator (UVM _scb), a scene exciter (seq_gen), a driving bus (drv_bus), a monitoring bus (mon_bus), and a register model (reg_model) automatically generated by the script. The functions and the use flow of each module will be described below, respectively. Directly calling uvm _cfg class after the uvm _env program block is started, and setting and marking data excitation type, chip state, register value, data comparison mode and the like; the seq_gen automatically generates excitation data according to the uvm _cfg type information and transmits the excitation data to the drv_bus; drv_bus is always in a loop state and is driven onto the RTL bus once the seq_gen update data is received. Meanwhile, the uvm _cfg class also transmits the register value information to the reg_model, and the reg_model receives data and then directly transmits the data to an internal register of the RTL code through a configuration bus; once the configuration is completed, the reg_model automatically outputs a set of FPGA upper board register configuration file according to the unified format of the register address and the register data, and the basis for UVM platform simulation and FPGA platform test comparison is given to the FPGA upper board reproduction case in the future. mon_bus is a passive loop receiver that automatically converts data information into transaction level information once it is sampled, and sends it to uvm _scb class; and the UVM _scb class receives the data information from the seq_gen and the mon_bus and UVM _cfg configuration information, and performs comprehensive processing comparison to obtain a verification result of the UVM simulation platform.

In the testing process, the FPGA test platform acquires the waveforms of the data signals to be compared, such as reg_debug, reg_box and the like in the table 1, and compares and analyzes the test waveforms output by the FPGA test platform and the simulation waveforms output by the UVM simulation platform together as shown in fig. 5, so that the problem and phenomenon of RTL logic codes can be positioned faster, human factors are reduced, and the unified specification and consistency of the logic codes, register information and configuration information are ensured more accurately.

Specifically, based on the first comparison result and/or the second comparison result, verifying the RTL Verilog HDL logic code includes: and under the condition that the first comparison result indicates that the similarity of the simulation waveform and the test waveform is greater than a first similarity threshold value and the second comparison result indicates that the similarity of the simulation record information and the test record information is greater than a second similarity threshold value, determining that the verification of the RTL Verilog HDL logic code is passed, wherein the verification passes the verification, and the RTL Verilog HDL logic code is indicated to meet the chip design requirement.

Specifically, under the condition that the first comparison result and the second comparison result are met, or the first comparison result is met, or the second comparison result is met, determining that the RTL Verilog HDL logic code passes verification.

The method can compare the coincidence degree of the simulation waveform and the test waveform to verify the RTL Verilog HDL logic code, and under the condition that the coincidence degree of the simulation waveform and the test waveform is consistent, the generated RTL Verilog HDL logic code passes the verification. It may also be determined whether the generated RTL Verilog HDL logic code is verified by comparing simulation log information with test log information.

More specifically, the input of the UVM register model to the UVM emulation platform, such that the UVM emulation platform outputs a register configuration file, includes: operating a simulation environment of a UVM simulation platform, and instantiating a UVM register model and an RTL top layer module of a chip; after instantiating the UVM register model and the chip RTL top layer module, the UVM simulation platform outputs a register configuration file in a unified format with the FPGA test platform.

The method enables the UVM register model and the PTL top layer module of the chip to be called and executed in a program by instantiating the UVM register model and the PTL top layer module of the chip, so that the operation and the management of the UVM register model and the PTL top layer module of the chip are more convenient.

Further, before obtaining the test waveform and the test record information, the method further comprises: setting a logic analyzer of the FPGA test platform and signal triggering conditions, wherein the logic analyzer is a tool for grabbing test waveforms for the FPGA test platform, and the signal triggering conditions are that triggering signals meet preset conditions, and the triggering signals at least comprise clock signals, data reset signals and functional switch signals.

In the FPGA testing process, corresponding test signal waveforms and chip data information can be grabbed by setting an FPGA logic analyzer and signal triggering conditions, and the corresponding test signal waveforms and chip data information are compared with waveforms of simulation cases of a UVM platform.

Further, inputting the RTL Verilog HDL logic code, the FPGA probe signal, and the register configuration file output by the UVM simulation platform to the FPGA test platform, comprising: automatically adding special descriptors into the RTL Verilog HDL logic codes by using FPGA probe signals to generate RTL Verilog HDL logic codes with the special descriptors; the special descriptor enables the FPGA test platform to generate test signal lines when RTL Verilog HDL logic code layout wiring; RTL Verilog HDL logic code with special descriptors is input into an FPGA test platform.

According to the method, as shown in FIG. 5, special descriptors are automatically added into RTL Verilog HDL logic codes by using FPGA probe signals, so that the FPGA can conveniently generate test signal lines when the comprehensive logic codes are laid out and routed, and waveform recording and comparison information is provided for positioning problems of subsequent signals.

Specifically, after the script program is called to read the register description file and generate the unified RTL Verilog HDL logic code, the FPGA probe signal and the UVM register model, the method further comprises: after the script program is finished, the script program automatically generates operation record information of the script program operation, wherein the operation record information comprises script program operator information, operation time information and script program name information.

After the script program is finished, the method can automatically generate the operation record information of the script, so that the subsequent review and archiving of staff can be facilitated.

In order to enable those skilled in the art to more clearly understand the technical solutions of the present application, the implementation process of the method for generating FPGA codes of the present application will be described in detail below with reference to specific embodiments.

The embodiment relates to a specific method for generating FPGA codes, which specifically comprises the following steps:

the implementation flow chart is shown in fig. 3, firstly, according to the description of the chip design requirement, a detailed register description table is input, the specific content of the table is shown in table 1, and the table comprises the following contents: base address (base_addr), offset address (offset_addr), register name (reg_name), register domain name (reg_field), register domain width (field_bits), default value (reg_default), access attribute (access_type), register description (reg_description), supplementary description (reg_components), FPGA probe (fpga_probe). The register reg_version address is 0x0, and is used for describing the version numbers of the FPGA and the chip; reg_staff is 0x1 to describe the engineer's work number; the reg_time address is 0x2 and is used for describing the code generation date and the specific clock; the reg_function address is 0x3 and is used for describing the chip functions which need to be started; reg_debug, reg_box addresses 0x0 and 0x1, are used to describe debug signals and debug data.

And calling a script program, reading the content of a register description table, acquiring the register information of the unified specification, and storing and recording the register information in a text file. Meanwhile, the script program automatically generates a register comprehensive logic code and outputs the register comprehensive logic code to a code text file; in addition, a register executable file program built based on UVM methodology is automatically generated. The method comprises the following operation of generating uniform and normative RTLVerilog HDL logic codes, UVM register models and FPGA probe signals. Because the FPGA test platform is limited and cannot record all waveforms for debugging and positioning, the script can generate FPGA probe signals according to FPGA probe (fpga_probe) filling items of the register form, and the FPGA probe signals automatically add special descriptors in RTL Verilog HDL logic codes, so that the FPGA can conveniently generate debugging signal lines when the comprehensive logic codes are laid out and wired, and waveform recording and comparison information is provided for positioning problems of subsequent signals. After the operation script is finished, script operation record information can be automatically generated, and the follow-up review and archiving are convenient.

The UVM simulation platform as shown in FIG. 4, the simulation environment top layer is a UVM _top module responsible for instantiating the integrated script automatically generated DUT code and UVM _env blocks, where UVM _env blocks contain environment configuration (UVM _top), comparison scorer (UVM _scb), scene exciter (seq_gen), drive bus (drv_bus), monitor bus (mon_bus), and script automatically generated register model (reg_model). The functions and the use flow of each module will be described below, respectively. Directly calling uvm _cfg class after the uvm _env program block is started, and setting and marking data excitation type, chip state, register value, data comparison mode and the like; the seq_gen automatically generates excitation data according to the uvm _cfg type information and transmits the excitation data to the drv_bus; drv_bus is always in a loop state and is driven onto the RTL bus once the seq_gen update data is received. Meanwhile, the uvm _cfg class also transmits the register value information to the reg_model, and the reg_model receives data and then directly transmits the data to an internal register of the RTL code through a configuration bus; once the configuration is completed, the reg_model automatically outputs an FPGA upper board configuration file according to the unified format of the register address and the register data, and the basis of UVM simulation and FPGA test comparison is given to the FPGA upper board reproduction case in the future. mon_bus is a passive loop receiver that automatically converts data information into transaction level information once it is sampled, and sends it to uvm _scb class; and the UVM _scb class receives the data information from the seq_gen and the mon_bus and UVM _cfg configuration information, and performs comprehensive processing comparison to obtain a verification result of the UVM simulation platform.

In the testing process, the FPGA test platform acquires the waveforms of the data signals to be compared, such as reg_debug, reg_box and the like in the table 1, and compares and analyzes the waveforms and the UVM simulation platform together, so that the problem and phenomenon of RTL logic codes can be positioned more quickly, human factors are reduced, and the unified specification and consistency of the logic codes, register information and configuration information are ensured more accurately.

In summary, as shown in fig. 5, for the whole set of application case architecture, the script program uniformly generates RTL Verilog HDL logic code and UVM register model according to the register table; the UVM simulation platform configures a register and outputs a register configuration file to the FPGA test platform; meanwhile, the FPGA test platform integrates RTL Verilog HDL logic codes comprehensively carrying probe information to carry out FPGA development board test; and finally, comparing the simulation waveform of the UVM simulation platform with the test waveform of the FPGA test platform, and comparing the simulation record information of the UVM simulation platform with the test record information of the FPGA test platform.

Through the above processes, a set of complete unified process of automatic specification is formed, FPGA codes and registers are automatically generated, and the method is applied to a UVM simulation platform and an FPGA test platform configuration method, so that the problems of information errors and non-uniform standards in the process of engineer design, verification and communication debugging of FPGA engineers are prevented, and the chip verification efficiency, accuracy and reusability are improved.

The embodiment of the application also provides a device for generating the FPGA code, and the device for generating the FPGA code can be used for executing the method for generating the FPGA code. The device is used for realizing the above embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The following describes an apparatus for generating FPGA codes provided in the embodiments of the present application.

Fig. 6 is a schematic diagram of an apparatus for generating FPGA code according to an embodiment of the present application. As shown in fig. 6, the apparatus includes:

a generating unit 61, configured to generate a register description file according to a chip design requirement, where the register description file at least includes a register base address, a register offset address, a register name, a register domain width, a default value, an access attribute, a register description, a supplementary instruction, and an FPGA probe;

And the calling unit 62 is used for calling the script program to read the register description file and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model.

In this embodiment, the first generating unit 61 generates a register description file according to the chip design requirement, where the register description file at least includes a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description, and an FPGA probe; and the calling unit 62 is used for calling the script program to read the register description file and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model. Through the scheme, a set of complete automatic standard unified flow is formed, the FPGA codes and registers are automatically generated, and the problems of information errors and non-uniform standards of engineers in the design process and the communication and debugging process with the FPGA engineers are solved.

As an alternative, the device further comprises a first input unit, a second input unit, an alignment unit and a verification unit;

the first input unit is used for inputting the UVM register model to the UVM simulation platform after generating the unified and standardized RTL Verilog HDL logic code, the FPGA probe signal and the UVM register model so as to enable the UVM simulation platform to output a register configuration file, a simulation waveform and simulation record information, wherein the simulation record information comprises information for recording a simulation event and a simulation operation, and the waveform parameters at least comprise waveform period, waveform frequency, waveform phase and waveform peak value; the second input unit is used for inputting the RTL Verilog HDL logic code, the FPGA probe signal and the register configuration file output by the UVM simulation platform to the FPGA test platform to obtain test waveforms and test record information, wherein the test record information comprises information for recording test events and test operations; the comparison unit is used for comparing the simulation waveform with the test waveform to obtain a first comparison result, and comparing the simulation record information with the test record information to obtain a second comparison result; and the verification unit is used for verifying the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result.

The verification unit comprises a determination module, and the determination module is used for determining that the RTL Verilog HDL logic code passes verification when the first comparison result indicates that the similarity of the simulation waveform and the test waveform is greater than a first similarity threshold value and the second comparison result indicates that the similarity of the simulation record information and the test record information is greater than a second similarity threshold value, wherein the verification passes to indicate that the RTL Verilog HDL logic code meets the chip design requirement.

The device can compare the coincidence degree of the simulation waveform and the test waveform to verify the RTL Verilog HDL logic code, and under the condition that the coincidence degree of the simulation waveform and the test waveform is consistent, the generated RTL Verilog HDL logic code passes the verification. It may also be determined whether the generated RTL Verilog HDL logic code is verified by comparing simulation log information with test log information.

Alternatively, the first input unit includes an instantiation module and an output module;

the instantiation module is used for running the simulation environment of the UVM simulation platform and instantiating the UVM register model and the RTL top layer module of the chip; and the output module is used for outputting a register configuration file in a unified format with the FPGA test platform by the UVM simulation platform after instantiating the UVM register model and the chip RTL top layer module.

The device can be called and executed in a program by instantiating the UVM register model and the PTL top layer module of the chip, so that the operation and management of the UVM register model and the PTL top layer module of the chip are more convenient.

The device comprises a logic analyzer of the FPGA test platform and a signal triggering condition, wherein the logic analyzer is a tool for capturing the test waveform for the FPGA test platform, and the signal triggering condition is that a triggering signal meets a preset condition, and the triggering signal at least comprises a clock signal, a data reset signal and a function switch signal.

In the FPGA testing process, the device can grasp corresponding test signal waveforms and chip data information by setting an FPGA logic analyzer and signal triggering conditions, and compare the corresponding test signal waveforms and the waveforms of the UVM platform simulation cases.

Alternatively, the second input unit includes a generating module and an input module;

the generation module is used for automatically adding special descriptors into the RTL Verilog HDL logic codes by using FPGA probe signals so as to generate the RTL Verilog HDL logic codes with the special descriptors; the special descriptor enables the FPGA test platform to generate test signal lines when RTL Verilog HDL logic code layout wiring; and the input module is used for inputting the RTL Verilog HDL logic code with the special descriptor into the FPGA test platform.

The device is shown in fig. 5, and a special descriptor is automatically added in the RTL Verilog HDL logic code by using an FPGA probe signal, so that the FPGA can conveniently generate a test signal line when the comprehensive logic code is laid out and routed, and waveform record and comparison information is provided for the positioning problem of the subsequent signals.

The device further comprises a second generation unit, wherein the second generation unit is used for automatically generating operation record information of script program operation after the script program operation is finished after the script program is called to read the register description file and generate the unified and standardized RTL Verilog HDL logic code, FPGA probe signals and UVM register model, and the operation record information comprises script program operator information, operation time information and script program name information.

Specifically, after the script program is run, the running record information of the script can be automatically generated, so that the subsequent review and archiving of staff can be facilitated.

The device for generating FPGA codes includes a processor and a memory, where the first generating unit 61, the calling unit 62, etc. are stored as program units, and the processor executes the program units stored in the memory to implement corresponding functions. The modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.

The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The kernel can be provided with one or more than one kernel, and the problems that flow is not standard and information transmission is lost easily caused by human factors by adopting a self-research or universal FPGA verification platform are solved by adjusting kernel parameters.

The memory may include volatile memory, random Access Memory (RAM), and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip.

The embodiment of the invention provides a computer readable storage medium, which comprises a stored program, wherein when the program runs, equipment where the computer readable storage medium is located is controlled to execute the method for generating FPGA codes.

Specifically, the method for generating the FPGA code comprises the following steps:

step S201, according to the chip design requirement, generating a register description file, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe;

step S202, calling a script program to read a register description file, and generating a unified standard RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model.

Optionally, after generating the unified RTL Verilog HDL logic code, FPGA probe signals, and UVM register model, the method further comprises: inputting the UVM register model to a UVM simulation platform, so that the UVM simulation platform outputs a register configuration file, a simulation waveform and simulation record information, wherein the simulation record information comprises information for recording a simulation event and a simulation operation, and the waveform parameters at least comprise a waveform period, a waveform frequency, a waveform phase and a waveform peak value; inputting the RTL Verilog HDL logic code, the FPGA probe signal and the register configuration file output by the UVM simulation platform to an FPGA test platform to obtain test waveforms and test record information, wherein the test record information comprises information for recording test events and test operations; comparing the simulation waveform with the test waveform to obtain a first comparison result, and comparing the simulation record information with the test record information to obtain a second comparison result; and verifying the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result.

Optionally, verifying the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result, including: and under the condition that the first comparison result indicates that the similarity of the simulation waveform and the test waveform is greater than a first similarity threshold value and the second comparison result indicates that the similarity of the simulation record information and the test record information is greater than a second similarity threshold value, determining that the verification of the RTL Verilog HDL logic code is passed, wherein the verification passes the verification, and the RTL Verilog HDL logic code is indicated to meet the chip design requirement.

Optionally, inputting the UVM register model to the UVM emulation platform, where the UVM emulation platform is caused to output a register configuration file comprising: operating a simulation environment of a UVM simulation platform, and instantiating a UVM register model and an RTL top layer module of a chip; after instantiating the UVM register model and the chip RTL top layer module, the UVM simulation platform outputs a register configuration file in a unified format with the FPGA test platform.

Optionally, before obtaining the test waveform and the test record information, the method further comprises: setting a logic analyzer of the FPGA test platform and signal triggering conditions, wherein the logic analyzer is a tool for grabbing test waveforms for the FPGA test platform, and the signal triggering conditions are that triggering signals meet preset conditions, and the triggering signals at least comprise clock signals, data reset signals and functional switch signals.

Optionally, inputting the RTL Verilog HDL logic code, the FPGA probe signal, and the register configuration file output by the UVM simulation platform to the FPGA test platform, including: automatically adding special descriptors into the RTL Verilog HDL logic codes by using FPGA probe signals to generate RTL Verilog HDL logic codes with the special descriptors; the special descriptor enables the FPGA test platform to generate test signal lines when RTL Verilog HDL logic code layout wiring; RTL Verilog HDL logic code with special descriptors is input into an FPGA test platform.

Optionally, after the script program is invoked to read the register description file and generate the RTL Verilog HDL logic code, the FPGA probe signal, and the UVM register model of the unified specification, the method further comprises: after the script program is finished, the script program automatically generates operation record information of the script program operation, wherein the operation record information comprises script program operator information, operation time information and script program name information.

The embodiment of the invention provides a processor for running a program, wherein the method for generating FPGA codes is executed when the program runs.

The embodiment of the invention provides equipment, which comprises a processor, a memory and a program stored in the memory and capable of running on the processor, wherein the processor realizes at least the following steps when executing the program:

The device herein may be a server, PC, PAD, cell phone, etc.

The present application also provides a computer program product adapted to perform a program initialized with at least the following method steps when executed on a data processing device:

It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.

From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

1) A method of generating FPGA code of the present application, comprising: generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe; and calling a script program to read the register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model. Through the scheme, a set of complete automatic standard unified flow is formed, the FPGA codes and registers are automatically generated, and the problems of information errors and non-uniform standards of engineers in the design process and the communication and debugging process with the FPGA engineers are solved.

2) An apparatus for generating FPGA code according to the present application, comprising: the generating unit is used for generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a default value, an access attribute, a register description, a supplementary description and an FPGA probe; and the calling unit is used for calling the script program to read the register description file and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model. Through the scheme, a set of complete automatic standard unified flow is formed, the FPGA codes and registers are automatically generated, and the problems of information errors and non-uniform standards of engineers in the design process and the communication and debugging process with the FPGA engineers are solved.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method of generating FPGA code, comprising:

generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a register default value, a register access attribute, a register description, a register supplement description and an FPGA probe;

and calling a script program to read the register description file, and generating a unified and normative RTL Verilog HDL logic code, an FPGA probe signal and a UVM register model.

2. The method of claim 1, wherein after generating the unified RTL Verilog HDL logic code, FPGA probe signals, and UVM register model, the method further comprises:

inputting the UVM register model to a UVM simulation platform, so that the UVM simulation platform outputs a register configuration file, a simulation waveform and simulation record information, wherein the simulation record information comprises information for recording simulation events and simulation operations, and the waveform parameters at least comprise waveform periods, waveform frequencies, waveform phases and waveform peaks;

Inputting the RTL Verilog HDL logic code, the FPGA probe signal and the register configuration file output by the UVM simulation platform to the FPGA test platform to obtain test waveforms and test record information, wherein the test record information comprises information for recording test events and test operations;

comparing the simulation waveform with the test waveform to obtain a first comparison result, and comparing the simulation record information with the test record information to obtain a second comparison result;

and verifying the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result.

3. The method of claim 2, wherein validating the RTL Verilog HDL logic code based on the first comparison result and/or the second comparison result comprises:

and determining that the RTL Verilog HDL logic code passes verification under the condition that the first comparison result indicates that the similarity of the simulation waveform and the test waveform is greater than a first similarity threshold and the second comparison result indicates that the similarity of the simulation record information and the test record information is greater than a second similarity threshold, wherein the verification passes the indication that the RTL Verilog HDL logic code meets the chip design requirement.

4. The method of claim 2, wherein inputting the UVM register model to a UVM emulation platform, such that the UVM emulation platform outputs a register configuration file, comprises:

operating a simulation environment of the UVM simulation platform, and instantiating the UVM register model and an RTL top layer module of the chip;

after instantiating the UVM register model and the chip RTL top layer module, the UVM simulation platform outputs the register configuration file in a unified format with the FPGA test platform.

5. The method of claim 2, wherein prior to obtaining the test waveform and the test record information, the method further comprises:

setting a logic analyzer and signal triggering conditions of the FPGA test platform,

the logic analyzer is a tool for capturing the test waveform for the FPGA test platform, and the signal triggering condition is that a triggering signal meets a preset condition, wherein the triggering signal at least comprises a clock signal, a data reset signal and a functional switch signal.

6. The method of claim 2, wherein inputting the RTL Verilog HDL logic code, the FPGA probe signals, and the register configuration file output by the UVM simulation platform to the FPGA test platform comprises:

Automatically adding a special descriptor into the RTL Verilog HDL logic code by using the FPGA probe signal so as to generate the RTL Verilog HDL logic code with the special descriptor;

the special descriptor enables the FPGA test platform to generate test signal lines when the RTL Verilog HDL logic code is laid out and routed;

and inputting the RTL Verilog HDL logic code with the special descriptor into the FPGA test platform.

7. The method of claim 1, wherein after invoking the script program to read the register description file to generate a unified RTL Verilog HDL logic code, FPGA probe signals, and UVM register model, the method further comprises:

after the script program is operated, the script program automatically generates operation record information of the script program operation, wherein the operation record information comprises script program operator information, operation time information and script program name information.

8. An apparatus for generating FPGA code, comprising:

the generating unit is used for generating a register description file according to the chip design requirement, wherein the register description file at least comprises a register base address, a register offset address, a register name, a register domain width, a default value, an access attribute, a register description, a supplementary description and an FPGA probe;

And the calling unit is used for calling the script program to read the register description file and generating a unified and normative RTLVerilog HDL logic code, an FPGA probe signal and a UVM register model.

9. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored program, wherein the program when run controls a device in which the computer readable storage medium is located to perform the method of generating FPGA code according to any of claims 1 to 7.

10. An electronic device, comprising: one or more processors, memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs comprising a method for performing the generating FPGA code of any of claims 1-7.