CN115441874A - Fourteen-bit resolution two-stage cyclic analog-to-digital converter - Google Patents
Fourteen-bit resolution two-stage cyclic analog-to-digital converter Download PDFInfo
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
A fourteen-bit resolution two-stage cyclic analog-to-digital converter comprises a first-stage multiplication digital-to-analog converter unit with 6-bit resolution, a second-stage multiplication digital-to-analog converter unit with 9-bit resolution, a redundancy addition module and a clock phase high-precision adjustable module. According to the invention, through the structural design of two-stage circulation of 6 bits +9 bits, the power consumption is greatly reduced compared with a single-stage 14-bit circulation type analog-to-digital converter, and the application of low-power consumption analog-to-digital conversion is met.
Description
Technical Field
The present invention relates to analog-to-digital converters, and more particularly, to a fourteen-bit resolution two-stage cyclic analog-to-digital converter.
Background
The analog-to-digital converter is used as an important module for communication between digital signals and analog signals, and is often applied to the fields of image processing, digital base stations and the like. The analog-to-digital converter samples the input analog signal at regular time intervals and compares the sampled analog signal with a series of standard digital signals, and the digital signals are converged successively until the two signals are equal, thereby finally obtaining binary numbers representing the signals. The cyclic analog-to-digital converter belongs to a cyclic structure in the analog-to-digital converter, has the characteristics of low power consumption and small area, and is widely applied to image sensors.
The problem of high power consumption of the existing analog-to-digital converter is difficult to solve due to high requirement on precision, and the realization of low power consumption is always a difficult point of analog-to-digital converter design.
Disclosure of Invention
The invention solves the problems that: the defects in the prior art are overcome, the fourteen-bit resolution two-stage cyclic analog-to-digital converter is provided, power consumption can be greatly reduced through two-stage design of 6-bit resolution and 9-bit resolution, and high-speed analog-to-digital conversion application is met.
The technical problem to be solved by the invention is realized by the following technical scheme:
a fourteen-bit resolution two-stage cyclic analog-digital converter comprises a first-stage multiplication digital-analog converter unit MDAC1 with 6-bit resolution and a second-stage multiplication digital-analog converter unit MDAC2 with 9-bit resolution, wherein the first-stage multiplication digital-analog converter unit MDAC1 and the second-stage multiplication digital-analog converter unit MDAC2 are both in a cyclic structure;
the first stage multiplication digital-to-analog converter unit MDAC1 and the second stage multiplication digital-to-analog converter unit MDAC2 work in a pipeline operation mode;
the first-stage multiplication digital-to-analog converter unit MDAC1 receives an input signal, obtains a high-6-bit conversion result through 5 times of cyclic processing, and transmits the high-6-bit conversion result to the second-stage multiplication digital-to-analog converter unit MDAC2;
the second-stage multiplication digital-to-analog converter unit MDAC2 receives the high-6-bit conversion result, and outputs a low-9-bit conversion result after 8 times of cyclic processing which is the same as that of the first-stage multiplication digital-to-analog converter;
and the high-order 6-bit conversion result and the low-order 9-bit conversion result are subjected to data processing, and the 14-bit conversion result synthesized by staggered addition is used as the output data of the whole analog-digital converter.
Preferably, the pipelining is of the form: after completing the conversion of high 6 bits, the first stage of multiplication digital-to-analog converter unit MDAC1 transfers the result to the second stage of multiplication digital-to-analog converter unit MDAC2, and when completing the low 9-bit quantization result, the first stage completes the high 6-bit conversion of the next signal; the conversion time of the first stage multiplying digital-to-analog converter unit MDAC1 is equal to the conversion time of the second stage multiplying digital-to-analog converter unit MDAC2 and equal to the conversion time of the whole analog-to-digital converter.
Preferably, each processing procedure of the first-stage multiplying digital-to-analog converter unit MDAC1 is as follows: sampling an input signal, wherein the state is called a sampling state; then, carrying out data processing on the input signal, wherein the state is called a holding state, and the next sampling operation is carried out on the sampling state while the holding state works; each time of processing obtains 1.5 bit results, and after 5 times of circulation and malposition addition, a high 6 bit conversion result is output.
Preferably, the first-stage multiplying digital-to-analog converter unit MDAC1 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier;
two input signals at the input end of the differential operational amplifier are sampled by a capacitor bank for sampling in the capacitor array through a time sequence driven switch, and a sampling result is stored in the capacitor bank to finish sampling state operation; while sampling, carrying out 1.5-bit quantization on an input signal through a 1.5-bit analog-to-digital converter;
after sampling is finished, the circuit enters a holding state, the capacitor is connected to the output of the 1.5-bit digital-to-analog converter module through switch control, the output end of the differential operational amplifier charges a capacitor bank used for the holding state in the capacitor array, the voltage of the capacitor bank finishes multiplication and bias function operation in the process of forming a new balance state, an operation result is stored in the capacitor bank, and the operation result is used as a result of the holding state and is sampled by a sampling capacitor in the next sampling state.
Preferably, each processing procedure of the second-stage multiplying digital-to-analog converter unit MDAC2 is as follows: sampling an input signal, wherein the state is called a sampling state; then, carrying out data processing on the input signal, wherein the state is called a holding state, and the next sampling operation is carried out on the sampling state while the holding state works; each time of processing obtains 1.5 bit result, 8 times of circulation and dislocation addition are carried out, and then the lower 9 bit conversion result is output.
Preferably, the second stage of multiplication digital-to-analog converter unit MDAC2 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier;
two input signals at the input end of the differential operational amplifier are sampled by a capacitor bank for sampling in the capacitor array through a switch driven by a time sequence, and a sampling result is stored in the capacitor bank to finish sampling state operation; 1.5 bits are quantized by a 1.5 bit analog-to-digital converter while the input signal is sampled;
after sampling is finished, the circuit enters a holding state, the capacitor is connected to the output of the 1.5-bit digital-to-analog converter module through switch control, the output end of the differential operational amplifier charges a capacitor bank used for the holding state in the capacitor array, the voltage of the capacitor bank finishes multiplication and bias function operation in the process of forming a new balance state, an operation result is stored in the capacitor bank, and the operation result is used as a result of the holding state and is sampled by a sampling capacitor in the next sampling state.
Preferably, the device further comprises a redundancy addition module, which is used for performing redundancy addition operation on the high-order 6-bit conversion result and the low-order 9-bit conversion result, subtracting one redundancy bit, and synthesizing a 14-bit conversion result.
Preferably, the digital-to-analog converter further comprises a clock phase high-precision adjustable module, which drives the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2, and controls the pipelining operation mode of the first-stage multiplication digital-to-analog converter unit MDAC2 and the second-stage multiplication digital-to-analog converter unit MDAC2 to work.
Preferably, the clock phase high-precision adjustable module is composed of an output signal of the same-phase clock unit, an output signal of the two-phase non-overlapping unit and an and operation unit, the same-phase clock signal and the clock signal of different phases are operated to obtain different time sequence clock signals, and the on-off of the switches of the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are controlled.
Preferably, the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are both in a modular design, and have the same circuit structure, so that replacement is facilitated.
Compared with the prior art, the invention has the advantages that:
(1) Compared with a single-stage circulation type analog-to-digital converter, the two-stage circulation type analog-to-digital converter can greatly reduce the power consumption under the same conversion rate, and meets the application of high-speed analog-to-digital conversion.
(2) The power consumption of the "6-bit + 9-bit" architecture is only one third of that of the single-stage 14-bit architecture at the same conversion rate, which has power consumption advantages. Meanwhile, compared with other two-stage architectures, the power consumption is lowest under the same conversion rate.
Drawings
FIG. 1 is a schematic diagram of a fourteen-bit resolution two-stage cyclic analog-to-digital converter according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a holding state of the cyclic analog-to-digital conversion unit, where a is an integrator structure in the holding state, and b is a relationship diagram of input and output signals.
Detailed description of the preferred embodiment
For the convenience of understanding of the present invention, the following description will be further explained by taking specific embodiments as examples in conjunction with the drawings, and the embodiments do not limit the embodiments of the present invention.
The invention carries out deep theoretical research and experimental verification on the analog-digital converter, and solves the design problem of realizing low power consumption of the 14-bit resolution analog-digital converter.
The multiplying digital-to-analog converter unit MDAC of the cyclic analog-to-digital converter is mainly based on a switched capacitor circuit and a switched optical capacitor circuit, and the sampling state and the holding state are divided. As shown in fig. 2a, a sampling capacitor C is used for the integrator structure in the hold state S And a holding capacitance C f Redistributing the two-plate charge while establishing the output voltage to C with respect to the input voltage f /C s A multiple relation value of. FIG. 2b is a graph showing the relationship between an input signal and an output signal, wherein the input signal is a step signal, the output signal is limited by the gain bandwidth product and the finite gain of the operational amplifier, and after a period of slow settling, the output signal gradually approaches the high level V of the input step signal step Wherein the functional relation of the output signal approaching the input step signal is as follows:
the output signal approaches V step Need to be smaller than the analog-to-digital converter
The single-stage cycle type fourteen-bit analog-to-digital converter generally requires that the establishing precision reaches
From the above functional relationship, one can obtain:
t >10.4 τ is calculated from the above equation.
Under the same conversion period, the higher the quantization bit number is, the shorter the single quantization time of the cyclic analog-to-digital converter is, to achieve the corresponding establishment accuracy, the operational amplifier needs to have a larger GBW, and the relationship between the tail current of the operational amplifier and the GBW is:
assuming that the working voltage of the analog-to-digital converter is 3.3V, the static power consumption of the operational amplifier is as follows:
P＝I×3.3
the list of requirements for the accuracy of the various digital-to-analog converters is obtained by calculation and is shown in table 1:
TABLE 1 list of requirements for building accuracy for different bit DAC
For a single-stage structure, the larger the quantization digit is, the larger the unit capacitance is, the shorter the signal establishment period is, the requirement of the single-stage fourteen-digit analog-to-digital converter on the operational amplifier is equal to the requirement of establishing higher precision on a larger capacitance in a shorter time, and the higher requirement on the GBW of the operational amplifier is put forward, so that the power consumption of the operational amplifier is increased.
In order to reduce power consumption, the invention abandons the design of a single-stage structure and provides a technical path of a two-stage structure with a one-bit redundancy bit. The two-stage structure is composed of two multiplication digital-to-analog conversion modules with different quantization bits, and through pipelining operation, the first stage can quantize the mth signal and the second stage quantizes the first stage processing result of the (m-1) th signal, so that the requirement on the establishing time of the first stage is relaxed, and the power consumption can be greatly reduced.
Based on the technical path, different quantization combinations of the fourteen-bit resolution two-stage circulation type analog-to-digital converter are analyzed and verified, and the operational amplifier tail current and the operational amplifier power consumption under different combinations are obtained. Table 2 shows the data of the superior combinations (5 + 10-1), (6 + 9-1) and (7 + 8-1) in all combinations, wherein the quantization bits refer to the quantization bits of the first stage structure, and the first stage needs to adopt a capacitor of 1.75pF to obtain the corresponding noise and matching performance.
TABLE 2 two-stage architecture first stage Divider digital-to-analog converter with different bits requirement list for accuracy of build
Under the same conversion rate, the data in the tables 1 and 2 are synthesized, and the comparison test is carried out on the structures of the single-stage structure and the two poles in different quantization combinations, so as to obtain a total power consumption comparison table shown in the table 3:
TABLE 3 Total power consumption chart of 14-bit resolution A/D converter based on different structures
| Architecture selection | Total power consumption |
| Single stage 14-position | 63.7uW |
| 6+9 bit architecture | 12.6+14.7＝23.3uW |
| 7-bit + 8-bit architecture | 16.8+10.5＝27.3uW |
| 5+10 bit architecture | 9+19.9＝28.9uW |
From table 3, it can be seen that the power consumption of the "6-bit + 9-bit" architecture is only one third of that of the single-stage 14-bit architecture, which has a larger power consumption advantage, and the power consumption is lower compared to the other two combination options. Especially for the application in multi-channel scenes such as CMOS image sensor column level readout circuits, the scale of parallel application of one thousand columns to ten thousand columns is usually reached, and the power consumption advantage of a single channel can be greatly shown in the multi-channel application.
Based on the above system demonstration and analysis, the invention provides a fourteen-bit resolution two-stage cyclic analog-to-digital converter, which comprises a first-stage multiplication digital-to-analog converter unit MDAC1 with 6-bit resolution, a second-stage multiplication digital-to-analog converter unit MDAC2 with 9-bit resolution, a redundancy addition module and a clock phase high-precision adjustable module, wherein a circuit diagram is shown in FIG. 1.
(1) Fig. 1 is a differential circuit structure, the circuit structure is divided into two parts which are the same from top to bottom, capacitors C1p1, C2p1, C3p1 and C1n1, C2n1, C3n1 included in the first-stage multiplying digital-to-analog converter unit MDAC1 have the same capacitance, phi s1p 、φ aAp 、φ 1Ap 、φ 2Ap 、φ 3Ap 、φ 4Ap And phi s1n 、φ aAn 、φ 1An 、φ 2An 、φ 3An 、φ 4An Phi crossing two parts of pn with the same timing 3A 、φ 4A Phi and phi 3Ap 、φ 4Ap 、φ 3An 、φ 4An The timing sequence is the same. The capacitors C1p2, C2p2, C3p2 and C1n2, C2n2 and C3n2 contained in the second-stage multiplying digital-to-analog converter unit MDAC2 have the same capacitance phi s2p 、φ aBp 、φ 1Bp 、φ 2Bp 、φ 3Bp 、φ 4Bp And phi s2n 、φ aBn 、φ 1Bn 、φ 2Bn 、φ 3Bn 、φ 4Bn Phi bridging two parts of pn with the same timing 3B 、φ 4B Phi and phi 3Bp 、φ 4Bp 、φ 3Bn 、φ 4Bn The timing is the same.
(2) Clock phase high-precision adjustable module
The clock phase high-precision adjustable module drives the first-stage multiplication digital-to-analog converter unit MDAC1, the second-stage multiplication digital-to-analog converter unit MDAC2 and the redundancy addition module to control the pipelining mode work of the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2.
(3) First stage multiplying digital-to-analog converter unit MDAC1
The first-stage multiplying digital-to-analog converter unit MDAC1 receives an input signal, outputs a 1.5-bit result each time after 5 times of cyclic processing, wherein the result contains redundant bit information, outputs a high-bit conversion result after staggered addition, and transmits the high-bit conversion result to the second-stage multiplying digital-to-analog converter unit MDAC2. The first-stage multiplying digital-to-analog converter unit MDAC1 comprises a 1.5-bit comparator, a 1.5-bit digital-to-analog converter, a switch, a capacitor and a differential operational amplifier. As shown in fig. 1:
two signals at the input of the differential operational amplifier pass phi s1p The controlled switch is sampled by capacitors C1p1 and C3p1, and phi at the same time s1p The controlled switch is opened across the input and output terminals of the differential operational amplifier to short circuit the differential operational amplifier 3Ap And the controlled switch is opened, the right ends of the C1p1 and C3p1 capacitors are connected together and charged through the output end of the differential operational amplifier, and the sampling result is stored at the right ends of the C1p1 and C3p1 capacitors, wherein the process is a sampling state. The timing of the switches and n-part control signals of C1n1, C2n1 and C3n1 coincide with the p-type circuit part.
After sampling is completed, phi s1p The controlled switch is closed and the circuit enters a hold state, phi aAp 、φ 1Ap And phi 3Ap Controlled switch on, [ phi ] s1p 、φ 4Ap And phi 2Ap The controlled switch is closed, the C1p1 capacitor is connected to the output of the 1.5-bit digital-to-analog converter module, the output end of the differential operational amplifier charges the left ends of the C1p1 and the C3p1, the capacitor voltages of the C3p1 and the C1p1 complete multiplication and offset function operation in the process of forming a new balanced state, the operation result is stored at the left ends of the C2p1 and the C3p1, and the result is used as the result of a holding state and is sampled by the sampling capacitor in the next sampling state. The timings of the switches of C1n1, C2n1 and C3n1 and the n-part control signals coincide with the p-type circuit part.
(4) Second stage multiplying digital-to-analog converter unit MDAC2
The second-stage multiplying digital-to-analog converter unit MDAC2 receives the high-6-bit conversion result of the first-stage multiplying digital-to-analog converter unit MDAC1, and outputs a low-9-bit conversion result after 8 times of cyclic processing which is the same as that of the first-stage multiplying digital-to-analog converter. The second-stage multiplication digital-to-analog converter unit MDAC2 comprises a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different time sequences, a capacitor array and a differential operational amplifier.
Two output signals of the second stage multiplying digital-to-analog converter unit MDAC2 pass through phi s2p The controlled switches are sampled by the second stage capacitors C1p2 and C3p2, and phi s2p The controlled switch is opened across the input and output terminals of the differential operational amplifier to short circuit the differential operational amplifier 3Bp And the controlled switch is opened, the right ends of the C1p2 and C3p2 capacitors are connected together and charged through the output end of the differential operational amplifier, and the sampling result is stored at the right ends of the C1p2 and C3p2 capacitors, wherein the process is a sampling state.
The first stage multiplying DAC unit MDAC1 is in the holding state of the fifth cycle and the sampling state of the first cycle of the second stage multiplying DAC, phi s2p 、φ 2Bp 、φ 3Bp 、φ aAp 、φ 1Ap And phi 3Ap Controlled switch on, [ phi ] aBp 、φ 1Bp 、φ 4Bp 、φ s1p 、φ 2Ap And phi 4Ap The controlled switch is closed. The timing of the n-part control signal is consistent with the p-type circuit part.
After completion of the sampling state, phi s2 The controlled switch is closed, and the second stage of the multiplying digital-to-analog converter unit MDAC2 circuit enters a holding state phi aBp 、φ 1Bp And phi 3Bp Controlled switch on, phi s2p 、φ 4Bp And phi 2Bp The controlled switch is closed, the C1p2 capacitor is connected to the output of the 1.5-bit digital-to-analog converter module, the output end of the differential operational amplifier charges the left ends of the C1p2 and the C3p2, the capacitor voltages of the C3p2 and the C1p2 complete multiplication and offset function operation in the process of forming a new balanced state, the operation result is stored at the left ends of the C2p2 and the C3p2, and the result is used as the result of a holding state and is sampled by the sampling capacitor in the next sampling state. The timing of the switches and n-part control signals of C1n2, C2n2 and C3n2 coincide with the p-type circuit part.
(5) Redundant addition module
The two-stage structure of the invention contains a redundant bit, the high 6-bit conversion result of the first-stage multiplication digital-analog converter unit MDAC1 and the low 9-bit conversion result of the second-stage multiplication digital-analog converter unit MDAC2 are operated by a redundant addition module, the redundant bit is subtracted, and a 14-bit conversion result is synthesized and used as the output data of the whole analog-digital converter.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (10)
1. A fourteen-bit resolution two-stage cyclic analog-to-digital converter is characterized by comprising a first-stage multiplication digital-to-analog converter unit MDAC1 with 6-bit resolution and a second-stage multiplication digital-to-analog converter unit MDAC2 with 9-bit resolution, wherein the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are both in a cyclic structure;
the first stage multiplication digital-to-analog converter unit MDAC1 and the second stage multiplication digital-to-analog converter unit MDAC2 work in a pipeline operation mode;
the first-stage multiplication digital-to-analog converter unit MDAC1 receives an input signal, obtains a high-6-bit conversion result through 5 times of cyclic processing, and transmits the high-6-bit conversion result to the second-stage multiplication digital-to-analog converter unit MDAC2;
the second-stage multiplication digital-to-analog converter unit MDAC2 receives the high-order 6-bit conversion result, and outputs a low-order 9-bit conversion result after 8 times of cyclic processing which is the same as that of the first-stage multiplication digital-to-analog converter;
and the high-order 6-bit conversion result and the low-order 9-bit conversion result are subjected to data processing, and the 14-bit conversion result synthesized by staggered addition is used as the output data of the whole analog-digital converter.
2. A fourteen bit resolution two stage cyclic analog to digital converter according to claim 1, in which the pipeline operates in the form of: after completing the conversion of high 6 bits, the first stage of multiplication digital-to-analog converter unit MDAC1 transfers the result to the second stage of multiplication digital-to-analog converter unit MDAC2, and when completing the low 9-bit quantization result, the first stage completes the high 6-bit conversion of the next signal; the conversion time of the first stage multiplying digital-to-analog converter unit MDAC1 is equal to the conversion time of the second stage multiplying digital-to-analog converter unit MDAC2 and equal to the conversion time of the whole analog-to-digital converter.
3. A fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, wherein the first-stage multiplying digital-to-analog converter unit MDAC1 performs the following processing procedures each time: sampling an input signal, wherein the state is called a sampling state; then, data processing is carried out on the input signal, the state is called a holding state, and the next sampling operation is carried out on a sampling state while the holding state works; each time of processing obtains 1.5 bit results, and after 5 times of circulation and malposition addition, a high 6 bit conversion result is output.
4. A fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 3, wherein the first-stage multiplying digital-to-analog converter unit MDAC1 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier;
two input signals at the input end of the differential operational amplifier are sampled by a capacitor bank for sampling in the capacitor array through a time sequence driven switch, and a sampling result is stored in the capacitor bank to finish sampling state operation; while sampling, carrying out 1.5-bit quantization on an input signal through a 1.5-bit analog-to-digital converter;
after sampling is finished, the circuit enters a holding state, the capacitor is connected to the output of the 1.5-digit digital-to-analog converter module through switch control, the output end of the differential operational amplifier charges a capacitor bank used for the holding state in the capacitor array, the voltage of the capacitor bank finishes multiplication and bias function operation in the process of forming a new balance state, an operation result is stored in the capacitor bank, and the operation result is sampled by a sampling capacitor in the next sampling state as the result of the holding state.
5. The fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, wherein the second stage multiplying digital-to-analog converter unit MDAC2 performs the following processing procedures each time: sampling an input signal, wherein the state is called a sampling state; then, data processing is carried out on the input signal, the state is called a holding state, and the next sampling operation is carried out on a sampling state while the holding state works; each time of processing obtains 1.5 bit result, 8 times of circulation and dislocation addition are carried out, and then the lower 9 bit conversion result is output.
6. The fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, wherein the second-stage multiplying digital-to-analog converter unit MDAC2 includes a 1.5-bit analog-to-digital converter, a 1.5-bit digital-to-analog converter, switches driven by different timings, a capacitor array, and a differential operational amplifier;
two input signals at the input end of the differential operational amplifier are sampled by a capacitor bank for sampling in the capacitor array through a time sequence driven switch, and a sampling result is stored in the capacitor bank to finish sampling state operation; 1.5 bits are quantized by a 1.5 bit analog-to-digital converter while the input signal is sampled;
after sampling is finished, the circuit enters a holding state, the capacitor is connected to the output of the 1.5-digit digital-to-analog converter module through switch control, the output end of the differential operational amplifier charges a capacitor bank used for the holding state in the capacitor array, the voltage of the capacitor bank finishes multiplication and bias function operation in the process of forming a new balance state, an operation result is stored in the capacitor bank, and the operation result is sampled by a sampling capacitor in the next sampling state as the result of the holding state.
7. A fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, wherein: the redundancy addition module is used for performing redundancy addition operation on the high-order 6-bit conversion result and the low-order 9-bit conversion result, subtracting one redundancy bit and synthesizing a 14-bit conversion result.
8. A fourteen bit resolution two stage cyclic analog to digital converter according to any one of claims 1 to 7, wherein: the digital-to-analog converter further comprises a clock phase high-precision adjustable module which drives the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 and controls the first-stage multiplication digital-to-analog converter unit MDAC2 and the second-stage multiplication digital-to-analog converter unit MDAC2 to work in a pipelining operation mode.
9. The fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 8, wherein: the clock phase high-precision adjustable module consists of an output signal of a same-phase clock unit, an output signal of a two-phase non-overlapping unit and an AND operation unit, wherein the clock signal of the same phase and the clock signal of different phases are operated to obtain different time sequence clock signals, and the on-off of switches of a first-stage multiplication digital-to-analog converter unit MDAC1 and a second-stage multiplication digital-to-analog converter unit MDAC2 are controlled.
10. A fourteen-bit resolution two-stage cyclic analog-to-digital converter according to claim 1, wherein: the first-stage multiplication digital-to-analog converter unit MDAC1 and the second-stage multiplication digital-to-analog converter unit MDAC2 are both in modular design, and circuit structures are the same, so that replacement is facilitated.
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