CN115426761A

CN115426761A - Optimum starting device for cyclotron

Info

Publication number: CN115426761A
Application number: CN202211117355.XA
Authority: CN
Inventors: 牟雪儿; 殷治国; 汪洋; 黄鹏; 杨芳迪; 宋琦琪
Original assignee: China Institute of Atomic of Energy
Current assignee: China Institute of Atomic of Energy
Priority date: 2022-09-14
Filing date: 2022-09-14
Publication date: 2022-12-02

Abstract

The invention discloses an optimized starting device of a cyclotron, which comprises a tuning module used for searching a tuning point based on a continuous closed loop or pulse closed loop mode, a low-level modulation output module based on the continuous closed loop or pulse closed loop mode, an amplitude demodulation module based on the continuous closed loop or pulse closed loop mode, a CPU based on the continuous closed loop or pulse closed loop mode, and a digital controller based on the continuous closed loop or pulse closed loop mode; the method is characterized in that: the tuning module for searching the tuning point based on the continuous closed loop or pulse closed loop mode finds the tuning point in a low-power tuning stage and a pulse searching stage, so that the frequency of a cavity and the frequency of a high-frequency signal are consistent, the Q value of the cavity is improved, and the condition of accelerating particles is met; the invention adopts a pre-tuning point + pulse closed loop mode, thereby not only improving the quality factor in the starting process of the cavity, but also avoiding the potential safety hazard caused by overhigh power.

Description

Optimum starting device for cyclotron

Technical Field

The invention relates to a design technology of a high-frequency low-level system of a cyclotron, in particular to an optimized starting device of the cyclotron.

Background

The starting process of the high-frequency cavity of the cyclotron encounters three difficulties: the first difficulty is to avoid the secondary electron multiplication effect region, because the secondary electron multiplication effect limits the power boost of the high frequency system; a second difficulty is finding a tuning point, which, even across the secondary electron multiplication effect region, limits the power boost of high frequency systems because it cannot be found, because the difficulty in finding a tuning point is: the compact cyclotron designed by the Chinese atomic energy institute has lower power of the initial point of the secondary electron multiplication region, nearly dozens of milliwatts, nearly 100 times of the initial point of the secondary electron multiplication region of the prior art, finds a tuning point under ultralow power, and has higher design difficulty; the third difficulty is that: even if the tuning point is found and the secondary electron multiplication effect area is crossed, a new problem is encountered in the high-level continuous signal phase after the power is boosted: on one hand, the signal is required to be a high-power signal, and on the other hand, when the signal power is too high, if the quality factor Q of the cavity is not high enough, the reflected power is too large, so that the transmitter and the coupling window are burnt. For example, after a tuning point is found, a pulse stretching mode is adopted to span an electron multiplication region, after the pulse stretching is 50%, the pulse becomes a continuous signal, a power boosting and normal operation stage is carried out under the continuous signal, the power is required to be kept high in the last two stages, but due to the continuous high-power signal, the transmitter and the coupling window are extremely likely to be burnt when the continuous high-power signal is accumulated to a certain degree.

Disclosure of Invention

The invention provides an optimized starting device of a cyclotron, aiming at solving the problems in the prior art, and aiming at solving the problem that a tuning point is found under ultra-low power and the problem that a cavity is easy to puncture and burn under a high-power continuous signal.

The invention provides the following technical scheme for solving the technical problems:

a cyclotron optimization starting device comprises a tuning module for searching a tuning point based on a continuous closed loop or pulse closed loop mode, a low-level modulation output module based on the continuous closed loop or pulse closed loop mode, an amplitude demodulation module based on the continuous closed loop or pulse closed loop mode, a CPU based on the continuous closed loop or pulse closed loop mode, and a digital controller based on the continuous closed loop or pulse closed loop mode; the CPU based on the continuous closed loop or the pulse closed loop mode is provided with a state machine used for controlling the starting process of the high-frequency cavity, wherein the state machine comprises a closing state s0, a low-power tuning state s1, a pulse searching state s2, a power boosting state s3 and a normal running state s4 in the starting process of the high-frequency cavity; the digital controller based on the continuous closed loop or pulse closed loop mode is provided with a PID tuning algorithm unit, a DSP balance algorithm unit, a Digital Signal Processor (DSP) and a digital signal processor (CPU), receives signals from an analog circuit and realizes communication with the CPU; the PID tuning algorithm unit is used for avoiding cavity detuning by accelerating the PID operation rate; the DSP balance algorithm unit ensures that the cavity pressures of the two groups of cavities are balanced by adjusting the capacitor motor;

the method is characterized in that: the tuning module for searching the tuning point based on the continuous closed loop or pulse closed loop mode finds the tuning point in a low-power tuning stage and a pulse searching stage, so that the frequency of the cavity and the frequency of a high-frequency signal are consistent, the Q value of the cavity is improved, and the condition of accelerating particles is met; the continuous closed-loop modes, namely the closed-loop modes of a low-power tuning state, a pulse searching state and a power boosting state, are continuous closed-loop modes; the pulse closed-loop mode is a continuous closed-loop mode which is a closed-loop mode of a low-power tuning state, and is a pulse closed-loop mode which is a closed-loop mode of a pulse searching state and a power boosting state.

Further, in the continuous closed-loop mode, a low-power tuning state, a power boost state and a normal operation state are set as a continuous signal operation mode, a pulse search state is set as a pulse signal operation mode, and a tuning closed loop in the low-power tuning state, a tuning closed loop in the power search state and an amplitude modulation closed loop in the power boost state are closed loops under continuous signals; the pulse closed-loop mode is characterized in that only the low-power tuning state is set to be a continuous signal operation mode, the power searching state, the power boosting state and the normal operation state are all pulse signal operation modes, only the tuning closed loop in the low-power tuning state is a closed loop in the continuous signal operation mode, the tuning closed loop in the power searching state and the amplitude modulation closed loop in the power boosting state are closed loops in the pulse signals, and the closed loop in the pulse signals is a closed loop judged at the high pulse level.

Further, the tuning module for searching tuning points based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a cavity Forward signal Forward, a cavity sampling signal Pickup1, a high-frequency switch 2, an amplifier, an attenuator, a phase discriminator, a tuning parameter setting module and a tuning comparator between the cavity of the accelerator and the CPU; performing subtraction operation on an ADC (analog to digital converter) analog signal led out from the phase discriminator and the tuning parameter setting value, and sending one path of an operation result to a digital controller through the ADC, and sending the other path of the operation result to a tuning comparator; in the low-power tuning and pulse searching states, the tuning comparator adopts continuous signals to judge a tuning closed loop, and when the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signals PhaseOK are respectively output and sent to the CPU through the digital controller; the cavity Forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling through a sampling cable after the accelerator cavity is driven by the low level modulation output module in the continuous closed loop or pulse closed loop mode.

Further, in a low-power tuning state of a continuous closed-loop mode, a pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty ratio of 10%, a CPU controls a forceCW signal to output a low-level signal, and the output of the pulse-to-continuous circuit is subjected to AND operation, the result is still a low-level signal, and the result is output to a high-frequency switch 1 and a high-frequency switch 2 of the tuning module and a high-voltage switch 3 of a low-level modulation output module through the operation, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of a 25db amplifier of each through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects one path of a 14db attenuator; in a power searching state of a continuous closed-loop mode, a pulse transfer continuous circuit of an amplitude demodulation module outputs a pulse signal with continuously widened duty ratio from 10% -50%, a CPU controls a forceCW signal to output a high-level signal, and the pulse signal output by the pulse transfer continuous circuit is subjected to AND operation, the result is still the pulse signal with continuously widened duty ratio, high-

frequency switches

1 and 2 select back and forth between an amplifier and an attenuator according to the pulse signal, and a high-frequency switch 3 also selects back and forth between 3db attenuation and 14db attenuation at the same time, namely when the pulse is high level, the switch 1 and the switch 2 select 23db attenuators, the switch 3 selects 3db attenuation, when the pulse is low level, the switch 1 and the switch 2 select 25db amplifiers, and the switch 3 selects 14db attenuation; under the power boost state and the normal operation state of the continuous closed-loop mode, the output of a pulse transfer continuous circuit of an amplitude demodulation module is a high-level continuous signal, a CPU controls a forceCW signal to output a high-level signal, and the output result of the pulse transfer continuous circuit is subjected to AND operation to obtain a high-level signal, the high-level signal and the operation output result are sent to a high-frequency switch 1, a high-frequency switch 2 and a high-frequency switch 3 of a low-level modulation output module, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of each attenuator through the high-frequency switch 1 and the high-frequency switch 2, and the high-frequency switch 3 is connected with one path of a 3db attenuator.

Further, in a low-power tuning state of a pulse closed-loop mode, the CPU state machine turns from an off state s0 to a low-power tuning state s1, and sends s1 to the digital controller, the digital controller provides a low-level signal to the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, and the high-voltage switch 3 of the low-level modulation output module, the Forward signal Forward of the cavity and the cavity sampling signal Pickup1 are selectively connected to one path of each amplifier through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects one path of the 14db attenuator; in a power searching state, a power boosting state and a normal operation state of a pulse closed-loop mode, a CPU state machine respectively sends signals s2, s3 and s4 to a digital controller in the pulse closed-loop mode according to a continuous tuning closed-loop signal PhaseOK in a low-power tuning state, a pulse amplitude closed-loop signal PhaseOK in the pulse searching state and a pulse amplitude closed-loop signal VDeeOK in the power boosting state, the digital controller in the pulse closed-loop mode gives a high level to a high-frequency switch 1 and a high-frequency switch 2 of a tuning module and a high-voltage switch 3 of a low-level modulation output module, a Forward signal Forward and a cavity sampling signal Pickup1 of a cavity are selectively connected with one path of each attenuator through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 is connected with one path of a 3db attenuator.

Furthermore, the amplitude demodulation module based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator between the accelerator cavity and the CPU; in a continuous closed-loop mode, after the cavity sampling signal Pickup2 is divided into three centimeters, one path of signal is used for ignition detection and judgment through a differential circuit, and the other two paths of signal are used for inputting a pulse signal or a continuous signal to an AND gate and a CPU (central processing unit) for AND operation after one path of signal passes through a detector 1 and a pulse transfer continuous circuit; one path is used for amplitude closed loop judgment after being detected by the detector 2; under the power boosting state, when the voltage value of the detection result of the detector 1 is different from the amplitude modulation parameter setting, judging that the detection result is in an allowable range, judging that the detection result is amplitude closed loop, and outputting a continuous amplitude closed loop signal VDee _ OK signal to a CPU (central processing unit); in a pulse closed-loop mode, after the cavity sampling signal Pickup is divided into two centimeters by 2, one path is used for ignition detection judgment through a differential circuit, and the other path is used for amplitude closed-loop judgment after being detected by a detector; under the power boosting state, after the voltage value of the detection result of the detector is different from the amplitude modulation parameter setting, if the voltage value is judged to be within the allowable range, the amplitude closed loop is judged, and a pulse amplitude closed loop signal VDee _ OK is output to the CPU.

Furthermore, in the pulse-to-continuous circuit in the continuous closed-loop mode, in the low-power tuning stage, the input of the pulse-to-continuous circuit is a low-power signal, the output of the pulse-to-continuous circuit is a signal with a 10% duty ratio, the signal is sent to an AND gate and is subjected to AND operation with a ForceCW controlled by a CPU, and the AND operation result is a low level; in the pulse searching stage, the pulse transfer continuous circuit judges that the current power reaches the power of a low-power tuning closed loop, then the pulse with the gradually broadened duty ratio is output to an AND gate and is subjected to AND operation with a ForceCW controlled by a CPU, the AND gate supplies the pulse with the gradually broadened duty ratio to a high-frequency switch 3, a 14db attenuator is selected and connected when the pulse is in a low level, and a 3db attenuator is selected when the pulse is in a high level, so that the pulse broadening is realized; in the power boosting stage, the pulse transfer continuous circuit judges that the current power reaches the power of the amplitude closed loop in the pulse searching state, then a continuous signal is output to an AND gate and is subjected to AND operation with a CPU, the output of the AND gate is a continuous high level and is output to a high-frequency switch 3, and the high-frequency switch 3 is connected with one path of a 3db attenuator according to the continuous high level signal.

Furthermore, the low level modulation output module based on the continuous closed loop or pulse closed loop mode is sequentially provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator, a 14db attenuator, a high-frequency switch 3, a numerical control attenuator and a low level output signal along the direction from the digital controller to the accelerator cavity; and in a low-power tuning state, the low-level output signal drives the cavity of the accelerator, so that a cavity Forward signal Forward and a cavity sampling signal Pickup1 of the tuning module are obtained through the sampling cable.

Further, in the power searching state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal in the low-power tuning state, the time that the high-frequency switch 3 is connected to the 3db attenuator and the 14db attenuator is controlled to be unequal through the and gate operation result to realize pulse width broadening, and at this time, the numerical control attenuator is constant; in the power boosting state of the continuous closed-loop mode, after receiving a continuous tuning closed-loop signal PhaseOK in the pulse searching stage, the CPU controls the high-frequency switch 3 to be connected with the 3db attenuator through an AND gate operation result, and instructs the digital controller to control the numerical control attenuator to continuously reduce attenuation, so that the power is continuously boosted until an amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU, and then the power boosting stage is completed and the normal operation state is entered.

Further, in a power searching state of a pulse closed-loop mode, after the CPU receives a continuous tuning closed-loop PhaseOK signal in a low-power tuning state, the CPU state machine sends an s2 signal to the digital controller, the digital controller sends a pulse with a certain duty ratio to the high-frequency switch 3, the high-frequency switch 3 connects one path of a 3db attenuator at a high level of the pulse according to the pulse with the constant duty ratio, connects one path of a 14db attenuator at a low level of the pulse, and the numerical control attenuator is constant at this time; in the power boosting state, after the CPU receives a pulse tuning closed-loop signal PhaseOK in the pulse searching state, a state machine of the CPU sends a signal s3 to a digital controller, the digital controller sends pulses with a certain duty ratio to a high-frequency switch 3, the high-frequency switch 3 is connected with a 3db attenuator at the pulse high level and connected with a 14db attenuator at the pulse low level according to the pulse with the constant duty ratio, meanwhile, the digital controller controls the numerical control attenuator to continuously reduce attenuation, and then the power is continuously boosted until an amplitude modulation comparator of an amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU, and at the moment, the power boosting stage is completed and the normal operation stage is entered.

Further, when the CPU based on the continuous closed loop or pulse closed loop mode receives the amplitude closed loop signal VDeeOK of the amplitude demodulation module and enters a normal operation state, the digital controller starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities.

Furthermore, the PID tuning algorithm unit of the digital controller based on the continuous closed loop or the pulse closed loop mode is arranged in the digital controller, and a PID operation module, a data arithmetic logic module and a multi-bus architecture are used; the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and realizes the synchronous operation of a plurality of operation instructions by utilizing parallel processing instructions under a multi-bus architecture, thereby accelerating the PID operation speed and avoiding the cavity detuning.

Furthermore, the PID operation module is provided with a PID operation output y (n) sub-module for driving the accelerator cavity motor, a PID operation output y (n-1) sub-module at the last moment of PID, PID adjustment coefficients K0, K1 and K2 sub-modules, and x (n), x (n-1) and x (n-2) PID input sub-modules at the current moment, the last moment and the previous two moments; the data arithmetic logic module comprises a DSP5600 series digital signal processor, the DSP5600 series digital signal processor stores the input x (n), x (n-1) and x (n-2) of PID of the current time, the previous time and the previous two times into a register R0, stores PID adjusting coefficients k0, k1 and k2 into a register R3, reads and writes the two registers by using a global bus, and realizes the purpose by using an accumulator and a multiplication function in the DSP and an assembly instruction

y(n)＝y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2)。

Furthermore, the DSP balance algorithm unit is provided with a voltage balance ratio calculation unit and a voltage balance adjustment unit; the voltage balance ratio calculation unit is used for a ratio relation formula:

wherein, C12 is the coupling capacitance value between two groups of cavities, and is divided into two parts, C12 'and C12', wherein C12 'is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity; the voltage balance adjusting unit can adjust the voltage of the plate D of the cavity by changing the ratio of C12 'to C12'.

Further, the CPU based on the continuous closed loop mode has a forcible conversion signal ForceCW of the CPU with a value of 0 when in the low power tuning state and a forcible conversion signal ForceCW of the CPU with a value of 1 when in the power searching, power boosting and normal operation states.

Advantageous effects of the invention

1. The invention adopts a pre-tuning point + pulse closed loop mode, thereby not only improving the quality factor in the starting process of the cavity, but also avoiding the potential safety hazard caused by overhigh power. The pre-tuning point is found before the power is boosted in two stages. The first pre-tuning point is the tuning point found before the low-power tuning state enters the pulse searching state, so that the input power to the cavity can be maximized when the power is increased in the pulse searching state, the power reflected by the cavity is minimized, and the quality factor Q value of the cavity is the highest. The second pre-tuning point is the tuning point found before the pulse searching state enters the power boosting state, namely the tuning point is found for the second time in the pulse searching stage, so that the input power to the cavity can be maximized when the pulse searching state enters the power boosting state, and the reflected power of the cavity is minimized; the pulse closed-loop mode is a high-level continuous mode in which pulses with fixed duty ratios are adopted to replace pulse searching, power boosting and normal operation states, so that the problem that a transmitter and a coupling window are burnt due to overhigh power in the debugging process is solved, and meanwhile, the problem that the transmitter and the coupling window are burnt due to overhigh power is solved because tuning points are judged at the high-level pulse, so that the judgment of tuning closed loops is not influenced, and the problem that the transmitter and the coupling window are burnt due to overhigh power is also solved.

2. The invention solves the problem that the tuning point is searched under ultra-low power in the starting process of the accelerator cavity for a long time in the field and also solves the problem that the tuning point needs to be searched for the second time due to the power change in the starting process of the cavity by organically combining the tuning module, the low-level modulation output module, the amplitude demodulation module, the PID tuning algorithm unit of the digital controller, the DSP balance algorithm unit and the CPU state machine: the problems that low-power signals cannot be identified by the phase discriminator under ultra-low power and high-power signals exceed the maximum input voltage range of the phase discriminator are solved by arranging the high-frequency switch 1 and the high-frequency switch 2 of the tuning module, the amplifier, the attenuator and the phase discriminator; through the organic combination of the PID tuning algorithm unit, the tuning parameter setting module and the tuning comparator of the tuning module, the problem that the PID operation rate cannot keep up with the state change when the tuning point is searched is solved; through the organic combination of the low level output signal of the low level modulation output module, the high-frequency switches 3 and 3db attenuation, the 14db attenuation and the tuning module, the tuning closed loop in a low-power tuning state and the tuning closed loop in a high-power pulse searching state are realized; by the opposite combination of the tuning closed loop of the tuning module and the amplitude demodulation module, the amplitude closed loop signal, the CPU state machine and the digital controller, the control problem of high-

frequency signals

1, 2 and 3 in two stages of the tuning closed loop is solved, so that one path of the amplifier and one path of the 14db attenuator are selected by three high-frequency switches at ultralow power, and thus, low-power signals can enter the phase discrimination range of the phase discriminator; and when the phase detector is high in power, one path of the high-

frequency signals

1, 2 and 3 select one path of the attenuator and one path of the 3db attenuator, so that the sampling signal of the cavity with high power cannot exceed the maximum input voltage range of the phase detector. In summary, through the organic combination of the modules, mutual support and mutual effect are generated. Substantial progress has been made.

Drawings

FIG. 1-1 is a schematic diagram of an optimized starting device for a cyclotron based on a continuous closed loop mode according to the present invention;

fig. 1-2 are schematic diagrams of the optimum starting device of the cyclotron based on the pulse closed loop mode according to the invention;

FIG. 2 is a schematic diagram of the PID tuning algorithm of the optimized starting device of the invention.

Fig. 3-1 is a flow chart of the method for starting the cyclotron optimization based on the continuous closed loop mode.

Fig. 3-2 is a flow chart of the optimum starting method of the cyclotron based on the pulse closed loop mode.

Detailed Description

Principle of the invention

1. The innovation points of the invention are as follows: pre-tuning point + pulse closed loop mode. The pre-tuning point is found before the power is boosted in two stages. The first pre-tuning point is the tuning point found before the low-power tuning state enters the pulse searching state, so that the maximum power of the input to the cavity can be achieved when the pulse searching state is entered to improve the power, the minimum power reflected by the cavity is achieved, and the Q value of the cavity is the highest. The second pre-tuning point is the tuning point found before the pulse searching state enters the power boosting state, namely the tuning point is found for the second time in the pulse searching stage, so that the input power to the cavity can be maximized when the pulse searching state enters the power boosting state, and the reflected power of the cavity is minimized; the pulse closed-loop mode is a high-level continuous mode in which pulses with fixed duty ratios are adopted to replace pulse searching, power boosting and normal operation states, so that the problem that a transmitter and a coupling window are burnt due to overhigh power in the debugging process is solved, and meanwhile, the problem that the transmitter and the coupling window are burnt due to overhigh power is solved because tuning points are judged at the high-level pulse, so that the judgment of tuning closed loops is not influenced, and the problem that the transmitter and the coupling window are burnt due to overhigh power is also solved.

2. The design difficulty of the invention is as follows: one of the difficulties is to achieve tuning at ultra-low power. 1) Compared with the prior art with the lowest power of 1 watt, the low power of the invention is only dozens of milliwatts, and the difference is more than 100 times. Because the cavity signal is weak under the ultra-low power signal, the cavity signal can not enter the phase discrimination range of the phase discriminator; 2) When the low-power tuning is switched to the pulse searching state, the tuning point is changed when the power is changed, the tuning point needs to be found again, when the tuning point is found again, the signal of the sampling cavity is a high-power signal, and the high-power signal burns the phase discriminator when entering the phase discriminator; 3) The PID algorithm is required to adapt to the rate of change of state, to the requirements of the data processing speed of the previous state and the next state. The PID output result is used for controlling a motor of the cavity, so that the cavity signal and the high-frequency signal are consistent, a tuning closed loop is realized, and before the next state is not reached, the PID is required to finish processing the data of the previous state, so that the output error caused by mixing the data of the next state and the data of the previous state together for processing because the data of the previous state is not finished yet is avoided. The second difficulty lies in: the high power requirement is satisfied under the high power condition, and the cavity is prevented from being broken down and damaged.

3. The solution of the invention is as follows: the solution to the first difficulty is: 1) 3 high-frequency switches are arranged, a high-frequency switch 1 and a high-frequency switch 2 are arranged on the tuning module, and amplifiers and attenuators corresponding to the high-

frequency switches

1 and 2 are arranged. A high-frequency switch 3 is arranged on the low-level modulation output module, and 3db and 14db attenuators are arranged. When in a low-power tuning state, the high-

frequency switches

1 and 2 are used for selecting the amplifier, the amplifier is 25db, so that the signal amplification enters the range of the phase discriminator, the problem that the signal power is too low and cannot easily enter the range of the phase discriminator is solved, and in order to ensure that an ultralow-power signal is input to the cavity in the low-power tuning state, the high-frequency switch 3 is also used for selecting a 14db attenuator to ensure that the signal output to the cavity is an ultralow-power signal of dozens of millivolts; 2) When the power searching state is switched to, in order to avoid that a cavity sampling signal burns out the phase detector, the high-

frequency switches

1 and 2 select one path of the attenuator, and the attenuation is based on the condition that the phase detector is not burnt out, so that the attenuator is properly designed (23 db attenuation); in order to ensure that a high-power signal is input to the cavity in the power searching state, the high-frequency switch 3 is also required to select a 3db attenuator, and the high-frequency switch 3 is used for selecting different attenuators to increase or decrease the power. 3) And (3) accelerating the PID processing speed: one of the methods is executed together with a plurality of instructions, including an addition instruction, a multiplication instruction, an input instruction, an output instruction and a shift instruction, and compared with the instruction serial execution of the conventional method, the speed is increased; the second method for accelerating the processing speed of the PID is to adopt assembly language, and the assembly language is more bottom-layer than other languages, so the operation speed is high; the third method for accelerating the processing speed of the PID is to adopt a multi-bus architecture, and compared with an architecture with only one bus, the effect of parallel processing is further highlighted. The three methods support mutual dependence, and only the combination of the three methods can achieve the best effect.

The solution to the second problem is: in a power searching state, a power boosting state and a formal running state, a pulse signal with a constant duty ratio is used for replacing a high-power continuous signal; under the power searching state, judging a tuning closed loop by using a pulse high level; under the power boosting state, judging an amplitude closed loop by using the high level of the pulse; in the formal operation state, the high-power continuous signal is changed into the pulse signal with a constant duty ratio, so that the discrete high-power pulse signal is used for replacing the high-power continuous signal, and the accumulation effect of the high-power signal is reduced. Because the power of the discrete pulse signal is not reduced, the high power requirements of a power searching state, a power boosting state and a formal operation state are also met. The power of the power boost state and the formal operation state is higher than that of the pulse search state, because the power is the power after the power boost after the pulse search state.

The invention is further explained below with reference to the drawings in which:

an optimized starting device of a cyclotron is shown in figures 1-1 and 1-2, and comprises a tuning module for searching a tuning point based on a continuous closed loop or a pulse closed loop mode, a low-level modulation output module based on the continuous closed loop or the pulse closed loop mode, an amplitude demodulation module based on the continuous closed loop or the pulse closed loop mode, a CPU based on the continuous closed loop or the pulse closed loop mode, and a digital controller based on the continuous closed loop or the pulse closed loop mode; the CPU based on the continuous closed loop or the pulse closed loop mode is provided with a state machine used for controlling the starting process of the high-frequency cavity, wherein the state machine comprises a closing state s0, a low-power tuning state s1, a pulse searching state s2, a power boosting state s3 and a normal running state s4 in the starting process of the high-frequency cavity; the digital controller based on the continuous closed loop or pulse closed loop mode is provided with a PID tuning algorithm unit, a DSP balance algorithm unit, a Digital Signal Processor (DSP) and a digital signal processor (CPU), receives signals from an analog circuit and realizes communication with the CPU; the PID tuning algorithm unit is used for avoiding cavity detuning by accelerating the PID operation rate; the DSP balance algorithm unit ensures the pressure balance of the two groups of cavities by adjusting the capacitor motor;

Supplementary notes 1:

1. the optimum starting device of the cyclotron comprises five main parts, namely a tuning module, a low level modulation output module, an amplitude demodulation module, a CPU and a digital controller, wherein the five main parts can be used in a continuous closed-loop mode and a pulse closed-loop mode, and different from the five main parts, when the optimum starting device is used in the continuous closed-loop mode, high-

frequency switches

1 and 2 of the tuning module and a high-frequency switch 3 of the low level modulation output module are controlled by an AND gate of the amplitude demodulation module; when the high-

frequency switch

1, 2 of the tuning module and the high-frequency switch 3 of the low-level modulation output module are controlled by a state machine of the CPU and a digital controller, the CPU state machine signals the digital controller, and the digital controller controls the high-

frequency switches

1, 2 and 3. The continuous closed loop is a tuning closed loop and an amplitude closed loop which are realized under a continuous signal, the pulse closed loop is a tuning closed loop and an amplitude closed loop which are realized under the high level of a pulse signal, but the tuning closed loop of the pulse closed loop is only suitable for a tuning closed loop in a pulse searching state, but not suitable for a tuning closed loop in a low-power tuning state, and the tuning closed loop in the low-power tuning state is always a tuning closed loop under the continuous signal.

2. Fig. 1-1 and 1-2 are divided into an upper part, a middle part and a lower part, wherein the upper layer is a tuning module, the lower layer is an amplitude demodulation module, the middle part is a low-level output module, the upper layer and the lower layer are sampled from a cavity, and the middle layer is used for inputting a high-frequency signal to the cavity. The purpose of sampling from the cavity is to perform a tuning closed loop and an amplitude closed loop; the purpose of inputting high-frequency signals into the cavity is to enable the cavity to boost the power to the voltage capable of accelerating particles and ensure that the frequency of the cavity is stabilized on the frequency of the high-frequency signals, so that the purpose of accelerating the particles is achieved.

3. The power is increased by two conditions, wherein the first condition is that a tuning point, namely a tuning closed loop, is found, and the power can be increased by a signal output to the cavity at the moment; the second is an amplitude closed loop, and although the tuning point is found by the tuning closed loop, the power may not reach the set height, so that the amplitude closed loop needs to be realized, that is, the amplitude reaches the set height. Therefore, the low level output signal of the middle layer is a process of low power to high power.

4. The pulse search state is used for crossing multiple electron multiplication regions, in the pulse search state, the first pulse crosses the voltage region generating multiple electric word multiplication, and assuming that the multiple electron multiplication region is from 10 mV to 100 mV, the voltage region of the first pulse applied to the high frequency cavity is 101 mV, which crosses the electron multiplication region, so as to achieve the effect of avoiding the multiple electron multiplication region. In the continuous closed-loop mode, the pulse in the pulse search state is rapidly spread to 0.5% duty ratio and then becomes a high-level continuous signal, and in the pulse closed-loop mode, the pulse in the pulse search state is a pulse with a constant duty ratio. Because the tuning point is found in advance in the low-power tuning state, the power added to the high-frequency cavity in the pulse searching stage is high enough, and the reflected power of the high-frequency cavity is as small as possible, so that the power added to the high-frequency cavity in the power searching state meets the requirement due to the fact that the Q value of the cavity is high no matter whether the high-frequency cavity is a continuous closed loop or a pulse closed loop.

Supplementary notes 2

The continuous closed loop mode is that the two-stage tuning closed loop (low power tuning state, power searching state) and the one-stage amplitude closed loop (power boosting state) are closed loops under the condition of continuous signals.

The pulse closed loop mode is that the low power tuning state is a closed loop tuned under a continuous signal, and the power searching state and the power boosting state are closed loops under the condition of a pulse signal.

Supplementary notes 3

The relationship of the tuning module to the other two modules. Although it is an independent module, the tuning module is a low level output signal that is not separated from the low level output module: the cavity Forward signal Forward and the cavity sampling signal Pickup1 are generated only when the accelerator cavity is driven by the low-level output signal; the tuning module does not leave the and gate operation result of the amplitude demodulation module, because the and gate operation result controls the high-

frequency switches

1 and 2 of the tuning module and controls the high-frequency switch 3 at the same time, although the high-frequency switch 3 belongs to the low-level output module, the tuning module also affects the tuning closed loop of the second stage of the tuning module, namely the power search stage: specifically, in the power search stage, the power of the cavity signals entering the high-

frequency switches

1 and 2 is increased, an amplifier is not required to be selected and an attenuator is selected at the moment, the phase discrimination of the phase discriminator is facilitated only by attenuating the signals due to too strong signals, and the tuning closed-loop judgment in the following power search state can be performed only when the signals enter the phase discrimination range of the phase discriminator. And the cavity signal power entering the high-

frequency switches

1 and 2 is enhanced because the high-frequency switches select the 3db attenuator to enhance the signal power entering the cavity. In short, the tuning module is not separated from the other two modules because the tuning module serves two stages, and the tuning closed-loop judgment of the two stages can be realized only if the tuning module is organically combined with the other two modules.

Further, in a low-power tuning state of a continuous closed-loop mode, a pulse-to-continuous circuit of the amplitude demodulation module outputs a pulse signal with a duty ratio of 10%, a CPU controls a forceCW signal to output a low-level signal, and the output of the pulse-to-continuous circuit is subjected to AND operation, the result is still a low-level signal, and the result is output to a high-frequency switch 1 and a high-frequency switch 2 of the tuning module and a high-voltage switch 3 of a low-level modulation output module through the operation, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of a 25db amplifier of each through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects one path of a 14db attenuator; when the power searching state is in a continuous closed loop mode, a pulse transfer continuous circuit of an amplitude demodulation module outputs a pulse signal with continuously widened duty ratio from 10% -50%, a CPU controls a forceCW signal to output a high level signal, and the pulse signal output by the pulse transfer continuous circuit is subjected to AND operation, so that the result is the pulse signal with continuously widened duty ratio, high-frequency switches 1 and 2 select back and forth between an amplifier and an attenuator according to the pulse signal, and a high-frequency switch 3 also selects back and forth between 3db attenuation and 14db attenuation at the same time, namely when the pulse is high level, the switch 1 and the switch 2 select 23db attenuators, the switch 3 selects 3db attenuation, when the pulse is low level, the switch 1 and the switch 2 select 25db amplifiers, and the switch 3 selects 14db attenuation; under the power boost state and the normal operation state of the continuous closed-loop mode, the output of a pulse transfer continuous circuit of an amplitude demodulation module is a high-level continuous signal, a CPU controls a forceCW signal to output a high-level signal, and the output result of the pulse transfer continuous circuit is subjected to AND operation to obtain a high-level signal, the high-level signal and the operation output result are sent to a high-frequency switch 1, a high-frequency switch 2 and a high-frequency switch 3 of a low-level modulation output module, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of each attenuator through the high-frequency switch 1 and the high-frequency switch 2, and the high-frequency switch 3 is connected with one path of a 3db attenuator.

Furthermore, the amplitude demodulation module based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator between the accelerator cavity and the CPU; in a continuous closed-loop mode, after the cavity sampling signal Pickup2 is divided into three centimeters, one path of signal is used for ignition detection and judgment through a differential circuit, and the other two paths of signal are used for inputting a pulse signal or a continuous signal to an AND gate and a CPU (central processing unit) for AND operation after one path of signal passes through a detector 1 and a pulse transfer continuous circuit; one path is used for amplitude closed loop judgment after being detected by the detector 2; under the power boosting state, when the voltage value of the detection result of the detector 1 is different from the amplitude modulation parameter setting, judging that the detection result is in an allowable range, judging that the detection result is amplitude closed loop, and outputting a continuous amplitude closed loop signal VDee _ OK signal to a CPU (central processing unit); in a pulse closed-loop mode, after the cavity sampling signal Pickup is divided into two centimeters, one path is used for ignition detection judgment through a differential circuit, and the other path is used for amplitude closed-loop judgment after being detected by a detector; under the power boosting state, after the voltage value of the detection result of the detector is different from the amplitude modulation parameter setting, if the voltage value is judged to be within the allowable range, the amplitude closed loop is judged, and a pulse amplitude closed loop signal VDee _ OK is output to the CPU.

Supplementary notes 4

In the continuous closed-loop mode, as shown in fig. 1-1, the pulse-to-continuous circuit of the amplitude demodulation module cooperates with the CPU to output signals to the and gate together, and the operation result of the and gate is used to control 3 high-frequency switches.

In the pulse closed loop mode, as shown in fig. 1-2, the amplitude demodulation module is not provided with an and gate, and the control of the

high frequency switches

1, 2, 3 is controlled by the CPU state machine.

Furthermore, in the pulse-to-continuous circuit in the continuous closed-loop mode, in the low-power tuning stage, the input of the pulse-to-continuous circuit is a low-power signal, the output of the pulse-to-continuous circuit is a signal with a 10% duty ratio, the signal is sent to an AND gate and is subjected to AND operation with a ForceCW controlled by a CPU, and the AND operation result is a low level; in the pulse searching stage, the pulse transfer continuous circuit judges that the current power reaches the power of a low-power tuning closed loop, then the pulse with gradually widened duty ratio is output to an AND gate and is subjected to AND operation with ForceCW controlled by a CPU, the AND gate sends the pulse with gradually widened duty ratio to a high-frequency switch 3, a 14db attenuator is selected and connected when the pulse is in a low level, and a 3db attenuator is selected when the pulse is in a high level, so that pulse widening is realized; in the power boosting stage, the pulse transfer continuous circuit judges that the current power reaches the power of the amplitude closed loop in the pulse searching state, then a continuous signal is output to an AND gate and is subjected to AND operation with a CPU, the output of the AND gate is a continuous high level and is output to a high-frequency switch 3, and the high-frequency switch 3 is connected with one path of a 3db attenuator according to the continuous high level signal.

Furthermore, the low level modulation output module based on the continuous closed loop or pulse closed loop mode is sequentially provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator, a 14db attenuator, a high-frequency switch 3, a numerical control attenuator and a low level output signal along the direction from the digital controller to the accelerator cavity; and in a low-power tuning state, the low-level output signal drives the accelerator cavity, so that a cavity Forward signal Forward and a cavity sampling signal Pickup1 of the tuning module are obtained through the sampling cable.

Supplementary notes 5

1. The relationship between the low level modulation output module and other two types of modules: the purpose of setting up low level modulation output module is for the signal of cavity input different power under different states, and simultaneously, low level modulation output module also needs the cooperation of other two modules: in a low-power tuning state, because the signal power output to the cavity is very low, the high-

frequency switches

1 and 2 of the tuning module are required to amplify the signal through the amplifier, and the high-frequency switch 3 of the low-power output module is required to select 14db to attenuate one path; in a power searching stage, a power boosting state and a normal operation state, because the power of a signal output to the cavity is enhanced, 3 high-frequency switches are required to select one path of the screening device or a 3db attenuator; meanwhile, the low-level modulation output module also needs the matching of the amplitude modulation module, samples the cavity sampling signal of the amplitude modulation module and sends the sampling signal to the AND gate, and controls 3 high-frequency signal switches through the operation result.

2. The low-level modulation output module also controls the magnitude of signal power output to the cavity under four states through the combination of the high-frequency switch 3 and the numerical control attenuator, and when the low-power tuning state is realized, the high-frequency switch 3 selects the 14db attenuator and the numerical control attenuator is constant; in the pulse searching state, the high-frequency switch 3 selects the 3db attenuator and the numerical control attenuator is constant; in a power boosting state, the digital controller controls the numerical control attenuator to continuously reduce attenuation and the high-frequency switch 3 selects the 3db attenuator; in the normal operation stage, the high-frequency switch 3 selects the 3db attenuator, and the numerical control attenuator is constant.

3. In the continuous closed-loop mode, the high-frequency switch 3 of the low-level modulation output module is controlled by the AND gate operation result of the amplitude modulation module, and in the pulse closed-loop mode, the high-frequency switch 3 of the low-level modulation output module is controlled by a CPU state machine.

Further, in the power searching state of the continuous closed-loop mode, after the CPU receives the continuous tuning closed-loop PhaseOK signal in the low-power tuning state, the time that the high-frequency switch 3 is connected to the 3db attenuator and the 14db attenuator is controlled to be unequal through the and gate operation result to realize pulse width broadening, and at this time, the numerical control attenuator is constant; in the power boosting state of the continuous closed-loop mode, after the CPU receives a continuous tuning closed-loop signal PhaseOK in the pulse searching stage, the high-frequency switch 3 is controlled to be connected with the 3db attenuator through an AND gate operation result, and the digital controller is instructed to control the numerical control attenuator to continuously reduce the attenuation, so that the power is continuously boosted until an amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU, and at the moment, the power boosting stage is finished, and the normal operation state is entered.

Further, in a power searching state of a pulse closed-loop mode, after the CPU receives a continuous tuning closed-loop PhaseOK signal in a low-power tuning state, the CPU state machine sends an s2 signal to the digital controller, the digital controller sends a pulse with a constant duty ratio to the high-frequency switch 3, the high-frequency switch 3 connects one path of a 3db attenuator at a high level of the pulse according to the pulse with the constant duty ratio, and connects one path of a 14db attenuator at a low level of the pulse, and at this time, the numerical control attenuator is constant; in the power boosting state, after the CPU receives a pulse tuning closed-loop signal PhaseOK in the pulse searching state, a state machine of the CPU sends a signal s3 to a digital controller, the digital controller sends pulses with a certain duty ratio to a high-frequency switch 3, the high-frequency switch 3 is connected with a 3db attenuator at the pulse high level and connected with a 14db attenuator at the pulse low level according to the pulse with the constant duty ratio, meanwhile, the digital controller controls the numerical control attenuator to continuously reduce attenuation, and then the power is continuously boosted until an amplitude modulation comparator of an amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU, and at the moment, the power boosting stage is completed and the normal operation stage is entered.

Furthermore, the PID tuning algorithm unit of the digital controller based on the continuous closed-loop or pulse closed-loop mode is arranged in the digital controller, and a PID operation module, a data arithmetic logic module and a multi-bus architecture are used; the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and realizes the synchronous operation of a plurality of operation instructions by utilizing parallel processing instructions under a multi-bus architecture, thereby accelerating the PID operation speed and avoiding the cavity detuning.

Further, the PID operation module is provided with a PID operation output y (n) sub-module for driving the accelerator cavity motor, a PID operation output y (n-1) sub-module at the last moment of PID, PID adjustment coefficient K0, K1, K2 sub-modules, and x (n), x (n-1) and x (n-2) PID input sub-modules at the current moment, the last moment and the previous two moments, as shown in fig. 2; the data arithmetic logic module comprises a DSP5600 series digital signal processor, the DSP5600 series digital signal processor stores the inputs x (n), x (n-1) and x (n-2) of the PID at the current time, the previous time and the previous two times into a register R0, stores PID adjustment coefficients k0, k1 and k2 into a register R3, reads and writes the two registers by using a global bus, and uses the DSP to perform the arithmetic logic operation

The accumulator and multiplication functions in (1) are realized by assembly instructions

y(n)＝y(n-1)+k0*x(n)+k1*x(n-1)+k2*x(n-2)。

Supplementary notes 6

The parallel assembly instruction effectively improves the operation rate of a PID algorithm, changes the resonant frequency of a cavity by tuning the motion of a motor through the output result of a y (n) submodule so as to influence the phase difference between a cavity sampling signal and a forward signal, and enables the output voltage of the phase discriminator to approach the setting voltage of a parameter setting module, the setting voltage of the parameter setting module is the voltage of the phase difference between the cavity sampling signal and the cavity forward signal when the preset cavity frequency and the high-frequency signal frequency are consistent, and the output voltage of the phase discriminator is the voltage of the actual phase difference between the cavity sampling signal and the cavity forward signal.

where C12 is the coupling capacitance between the two sets of cavities, divided into two parts C12' andc12', wherein C12' is the capacitance of the D1 cavity and C12' is the capacitance of the D2 cavity; the voltage balance adjusting unit can adjust the voltage of the plate D of the cavity by changing the ratio of C12 'to C12'.

Example one

Based on the above cyclotron optimized starting device, the invention also designs a cyclotron optimized starting method based on a continuous closed-loop mode, which is shown in fig. 3-1 and is characterized by comprising the following steps:

a cyclotron optimal starting method based on a continuous closed-loop mode comprises the following steps:

step one, initializing preparation work

1) Establishing a one-key starting process of a low-level system of the cyclotron;

2) Establishing a CPU state machine, wherein the state of the state machine is S0-S4;

step two, entering a low-power tuning state in a continuous closed-loop mode and realizing a tuning closed loop in the low-power state;

entering a pulse searching state in a continuous closed-loop mode and realizing a tuning closed loop in the pulse searching state;

entering a power lifting state in a continuous closed-loop mode and realizing amplitude closed-loop in the power lifting state;

and step five, entering a normal operation state under a continuous closed-loop mode and realizing cavity pressure balance under the normal operation state.

Further, the second step of entering the low power tuning state in the continuous closed-loop mode and implementing the tuning closed loop in the low power state includes the following specific steps:

1) The low level modulation output module inputs a low level continuous signal to the cavity of the accelerator, the low level continuous signal drives the cavity of the accelerator, and a cavity Forward signal Forward, a cavity sampling signal Pickup1 and a cavity sampling signal Pickup2 of the tuning module are obtained from the accelerator through sampling cables;

2) After the cavity sampling signal Pickup2 is divided into three centimeters, one path of the cavity sampling signal Pickup is used for ignition detection judgment through a differential circuit, the other path of the cavity sampling signal Pickup is used for amplitude closed loop judgment after being detected by a detector, the other path of the cavity sampling signal Pickup is used for amplitude closed loop judgment after being detected by the detector, the other path of the cavity sampling signal Pickup outputs a continuous signal after passing through the detector 1 and a pulse-to-continuous circuit, the continuous signal is input to an AND gate and a CPU for AND operation, and an operation result outputs a low level;

3) Low level signals are sent to a high frequency switch 1, a high frequency switch 2 and a high frequency switch 3;

4) The high-frequency switch 1 and the high-frequency switch 2 are selectively connected with one path of the amplifier, so that the signal can enter the phase discrimination range of the phase discriminator; the high-frequency switch 3 is selectively connected with one path of the 14db attenuator to ensure that the voltage output by the low-level continuous signal does not reach the secondary electron multiplication effect area of the cavity;

5) Performing subtraction operation on an ADC (analog to digital converter) analog signal led out from the phase discriminator and the tuning parameter setting value, and sending an operation result to the digital controller through the ADC in one path, and sending the operation result to the tuning comparator in the other path;

6) And when the tuning comparator judges that the cavity frequency is consistent with the high-frequency signal frequency, outputting a tuning closed-loop signal PhaseOK to the CPU, realizing tuning closed-loop under a low-power tuning state, and entering a pulse searching stage.

Further, the third step of entering the pulse search state in the continuous closed-loop mode and implementing the tuning closed-loop in the pulse search state includes the following specific steps:

1) After receiving a tuning closed-loop signal PhaseOK in a low-power tuning state, the CPU forcibly converts a signal ForceCW output into 1;

2) After the cavity sampling signal Pickup2 is divided into three centimeters, one path is used for ignition detection judgment through a differential circuit, the other path is used for amplitude closed loop judgment after being detected by a detector, the other path of signal outputs pulses with gradually widened duty ratios after passing through a detector 1 and a pulse transfer continuous circuit, the pulse signals with gradually widened duty ratios are input into an AND gate and a CPU for AND operation, and the operation result outputs pulse signals with gradually widened duty ratios;

3) The pulse signal with the gradually widened duty ratio is sent to the high-frequency switch 3 and simultaneously sent to the high-

frequency switches

1 and 2;

4) The high-frequency switch 3 correspondingly selects one path of a 3db attenuator at a pulse high level and one path of a 14db attenuator at a pulse low level according to the pulse signal with the duty ratio gradually widened, so that the widening of the low-level output pulse signal is realized; the high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one path of the attenuator in a pulse high-level signal according to the pulse signal with the duty ratio gradually widened, and select and amplify one path in a pulse low-level signal; due to the fact that power is improved in a pulse searching state, a cavity Forward signal Forward and a cavity sampling signal Pickup1 with improved power enter a phase discriminator through an attenuator;

5) Performing subtraction operation on an ADC (analog to digital converter) analog signal led out by the phase discriminator and the tuning parameter setting value, and sending one path of an operation result to the digital controller through the ADC and sending the other path of the operation result to the tuning comparator;

6) And when the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, outputting a tuning closed-loop signal PhaseOK to the CPU, realizing the tuning closed-loop in a pulse search state, entering a power boost state, and closing the tuning comparator.

Further, the step four of entering the power boost state in the continuous closed-loop mode and implementing the amplitude closed loop in the power boost state includes the following specific processes:

1) After receiving a tuning closed-loop signal PhaseOK in a power searching state, the CPU forces a conversion signal ForceCW to output 1;

2) After the cavity sampling signal Pickup2 is divided into three centimeters, one path is used for ignition detection judgment through a differential circuit, the other path is used for amplitude closed loop judgment after being detected by a detector, the other path is used for outputting a high-level continuous signal after passing through a detector 1 and a pulse-to-continuous circuit, the continuous signal is input to an AND gate and a CPU for AND operation, and the high-level continuous signal is output with an operation result;

3) The high-level continuous signal is sent to the high-frequency switch 3, and meanwhile, the high-level continuous signal is sent to the high-

frequency switches

1 and 2;

4) The high-frequency switch 3 selects a 3db attenuator according to the high-frequency signal; the high-

frequency switches

1 and 2 of the tuning module select one path of the attenuator according to the high-frequency signal;

5) The digital controller controls the numerical control attenuator to continuously reduce attenuation and further continuously increase power until an amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed loop VDeeOK signal to the CPU, and at the moment, the power increase stage is completed, amplitude closed loop is achieved, and the normal operation state is entered.

Further, the step five enters a normal operation state in the continuous closed-loop mode and realizes cavity pressure balance in the normal operation state, and the specific process is as follows:

1) After receiving an amplitude closed-loop signal VDee _ OK in a power boosting state, the CPU forces a conversion signal ForceCW to output 1;

2) After the cavity sampling signal Pickup2 is divided into three centimeters, one path is used for ignition detection judgment through a differential circuit, the other two paths are used for amplitude closed loop judgment after being detected by a wave detector, the other path of signal is used for outputting a high-level continuous signal after passing through a wave detector 1 and a pulse switching continuous circuit, the continuous signal is input into an AND gate and a CPU for AND operation, and the high-level continuous signal is output with an operation result;

frequency switches

1 and 2;

frequency switches

5) The numerical control attenuator is constant in constant value;

6) And the digital controller starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities.

Further, the digital controller in the process 6) starts the DSP balance algorithm unit to perform the cavity pressure balance between the two cavities, which specifically includes the following steps:

1) The specific relation of the voltage unbalance condition of two groups of cavities caused by factors such as processing design and the like when the two groups of cavities of the accelerator are in capacitive coupling is shown as the following formula [1]:

wherein, C12 is the coupling capacitance value between two groups of cavities, and is divided into two parts, C12 'and C12', wherein C12 'is the capacitance of the D1 cavity, and C12' is the capacitance of the D2 cavity;

2) The D voltage can be adjusted by changing the ratio of C12 'to C12', and the balance control algorithm is as follows: the phase discriminator outputs a result Tphase which determines the motion frequency of the capacitor motor, and the motor motion step number setting value Dsteps determines the motion step number of the motor. When Dsteps is more than 0 and Tphase is more than 0, the motor of the D1 cavity group moves towards the positive direction at the speed of 2 times, and the motor of the D2 cavity group stops; when Dsteps is more than 0 and Tphase is woven as a cloth cover 0, the motor of the D2 cavity group moves in the reverse direction at the speed of 2 times, and the motor of the D1 cavity group does not move; when dps is less than 0 and TPhase >; when dstps <0, tphase, and straw 0, the motors for the D1 chamber group were moved in the reverse direction at twice the speed, and the motors for the D2 chamber group were unchanged.

Further, the tuning closed loop of the second step and the third step is realized by a PID tuning algorithm unit of the digital controller as follows:

1) The digital PID algorithm is expressed as:

y(n)＝y(n-1)+K ₀ x(n)+K ₁ x(n-1)+K ₂ (n-2)；

wherein y (n) is PID operation output, y (n-1) is PID operation output at the last moment, K0, K1 and K2 are PID adjusting coefficients, and x (n), x (n-1) and x (n-2) are PID input at the current moment, the last moment and the previous two moments;

2) R0 and R3 registers are used in an X memory of the DSP, and a global data bus is used for reading and writing;

3) Storing the inputs x (n), x (n-1) and x (n-2) of the PID at the current moment, the previous moment and the previous two moments into a register R0, and storing k0, k1 and k2 into a register R3;

4) And reading and writing the two registers by using a global bus, and realizing y (n) = y (n-1) + k0 x (n) + k1 x (n-1) + k2 x (n-2) by using an accumulator and a multiplication function in the DSP.

Example two

Based on the above-mentioned cyclotron optimized starting device, the present invention also relates to a cyclotron optimized starting method based on a pulse closed-loop mode, as shown in fig. 3-2, which is characterized by comprising the following steps:

step one, initialization preparation work

step two, entering a low-power tuning state in a pulse closed-loop mode and realizing a tuning closed loop in the low-power tuning state;

entering a pulse searching state in a pulse closed-loop mode and realizing a tuning closed loop in the pulse searching state;

entering a power lifting state in a pulse closed-loop mode and realizing amplitude closed-loop in the power lifting state;

and step five, entering a normal operation state under a pulse closed-loop mode and realizing cavity pressure balance under the normal operation state.

Further, the second step of entering the low power tuning state in the pulse closed loop mode and implementing the tuning closed loop in the low power tuning state includes the following specific steps:

1) The low-level modulation output module inputs a low-level pulse signal to the cavity of the accelerator, the low-level pulse signal drives the cavity of the accelerator, and a cavity Forward signal Forward, a cavity sampling signal Pickup1 and a cavity sampling signal Pickup2 of the tuning module are obtained from the accelerator through a sampling cable;

2) The CPU state machine goes from the off state s0 to the low power tuning state s1, and sends s1 to the digital controller,

3) The digital controller respectively provides a low level signal for a high frequency switch 1 and a high frequency switch 2 of the tuning module and a high voltage switch 3 of the low level modulation output module;

4) A Forward signal Forward of the cavity and a cavity sampling signal Pickup1 are selectively connected with one path of each amplifier through a high-frequency switch 1 and a high-frequency switch 2, so that a low-power signal can enter a phase discrimination range of the phase discriminator; the high-voltage switch 3 selects one path of the 14db attenuator;

5) Performing subtraction operation on an ADC (analog to digital converter) analog signal led out from the phase discriminator and the tuning parameter setting value, and sending one path of an operation result to the digital controller through the ADC, and sending the other path of the operation result to the tuning comparator;

6) And the PID tuning algorithm unit performs tuning closed loop operation in a low-power tuning state: when the cavity frequency and the high-frequency signal frequency are judged to be consistent, outputting a tuning closed-loop signal PhaseOK to a CPU, realizing tuning closed-loop under a low-power tuning state, and entering a pulse searching stage; in the low power tuning state, the tuning comparator determines a tuning closed loop under a continuous signal.

Further, the third step of entering the pulse search state in the pulse closed-loop mode and implementing the tuning closed-loop in the pulse search state includes the following specific processes:

1) After receiving a tuning closed-loop signal PhaseOK in a low-power tuning state, the CPU sends an s2 signal to the digital controller;

2) The digital controller sends the pulse signal with fixed duty ratio to the high-frequency switch 3 and simultaneously sends the pulse signal to the high-

frequency switches

1 and 2;

3) The high-frequency switch 1 and the high-frequency switch 2 of the tuning module select one path of the attenuator according to the high-level signal of the pulse signal with the fixed duty ratio, and due to the fact that the power is improved in the pulse searching state, the cavity Forward signal Forward and the cavity sampling signal Pickup1 with the improved power enter the phase discriminator through the attenuator; the high-frequency switch 3 selects one path of a 3db attenuator at a high pulse level and one path of a 14db attenuator at a low pulse level according to a pulse signal with a fixed duty ratio, so that equal-width pulses in a power search state are realized;

4) Performing subtraction operation on an ADC (analog to digital converter) analog signal led out by the phase discriminator and the tuning parameter setting value, and sending one path of an operation result to the digital controller through the ADC and sending the other path of the operation result to the tuning comparator;

5) The PID tuning algorithm unit carries out tuning closed-loop operation under a pulse searching state: when the cavity frequency and the high-frequency signal frequency are judged to be consistent, outputting a pulse tuning closed-loop signal PhaseOK to the CPU, realizing a pulse tuning closed loop in a pulse searching state, closing a tuning comparator, and entering a power boosting state; in the pulse seek state, the tuning comparator determines the tuning point at a pulse high level.

Further, the fourth step of entering a power boost state in a pulse closed-loop mode and implementing an amplitude closed-loop in the power boost state includes the following specific steps:

1) After receiving the pulse tuning closed-loop signal PhaseOK in the power searching state, the CPU sends an s3 signal to the digital controller;

frequency switches

1 and 2;

3) The high-frequency switch 3 selects one path of a 3db attenuator at a high pulse level and one path of a 14db attenuator at a low pulse level according to a pulse signal with a fixed duty ratio, so that equal-width pulse in a power boosting state is realized; a high-frequency switch 1 and a high-frequency switch 2 of the tuning module select one path of the attenuator according to a high-level signal of a pulse signal with a constant duty ratio, and select and amplify one path of the attenuator according to a low level.

4) The digital controller controls the numerical control attenuator to continuously reduce attenuation and further continuously increase power until an amplitude modulation comparator of the amplitude demodulation module outputs a pulse amplitude closed-loop VDeeOK signal to the CPU, and at the moment, the power increase stage is completed, amplitude closed-loop is achieved, and the normal operation state is entered.

Further, the step five enters a normal operation state in a pulse closed-loop mode and realizes cavity pressure balance in the normal operation state, and the specific process is as follows:

1) After receiving a pulse amplitude closed-loop signal VDee _ OK in a power boosting state, the CPU sends an s4 signal to the digital controller;

2) The digital controller sends pulse signals with equal width to the high-frequency switch 3 and simultaneously sends the pulse signals to the high-

frequency switches

1 and 2;

3) The high-frequency switch 3 selects one path of a 3db attenuator at the high level of the pulse and one path of a 14db attenuator at the low level of the pulse according to the pulse signal with the constant duty ratio, so that the pulse with the constant duty ratio under the normal operation state is realized; a high-frequency switch 1 and a high-frequency switch 2 of the tuning module select one path of the attenuator according to a high-level signal of the pulse signal with the same width, and select and amplify one path at low level.

4) The numerical control attenuator is constant in constant value;

5) And the digital controller starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities.

Further, the digital controller of the process 5) starts the DSP balance algorithm unit to perform the cavity pressure balance between the two cavities, and the specific steps are as follows:

1) When the two groups of cavities of the accelerator are capacitively coupled, the condition that the two groups of cavities have voltage unbalance due to factors such as processing design and the like is expressed by a ratio relation:

wherein, C ₁₂ Is the coupling capacitance value between two groups of cavities and is divided into two parts C ₁₂ "and C ₁₂ ', wherein C ₁₂ "is the capacitance of the D1 cavity, C ₁₂ ' is the capacitance of the D2 cavity;

2) Change of C ₁₂ "and C ₁₂ ' the ratio can adjust the voltage D, and the balance control algorithm is as follows: the phase detector outputs result Tphase to determine the motion frequency of the capacitor motor, the motor motion step number setting value Dsteps determines the motion step number of the motor, when Dsteps>0,Tphase>When 0, the D1 cavity group motor moves towards the positive direction at the speed of 2 times, and the D2 cavity group motor stops moving; when Dsteps exists>0,Tphase<When 0, the D2 cavity group motor moves in the reverse direction at 2 times of speed, and the D1 cavity group motor does not move; when Dsteps exists<0,TPhase>When 0, the D2 cavity group motor moves towards the positive direction at double speed, and the D1 cavity group motor does not move; when Dsteps exists<0,TPhase<At 0, the D1 chamber group motor moves in the reverse direction at twice the speed, and the D2 chamber group motor is unchanged.

Further, the PID tuning algorithm unit performs tuning closed loop operation, and the implementation process is as follows:

1) The digital PID algorithm is expressed as:

y(n)＝y(n-1)+K ₀ x(n)+K ₁ x(n-1)+K ₂ (n-2)；

4) And reading and writing the two registers by using a global bus, and realizing y (n) = y (n-1) + k0 x (n) + k1 x (n-1) + k2 x (n-2) by using an accumulator and a multiplication function in the DSP and assembly language.

It should be emphasized that the above-described embodiments are merely illustrative of the present invention and are not limiting, since modifications and variations of the above-described embodiments, which are not inventive, may occur to those skilled in the art upon reading the specification, are possible within the scope of the appended claims.

Claims

1. A cyclotron optimization starting device comprises a tuning module for searching a tuning point based on a continuous closed loop or pulse closed loop mode, a low-level modulation output module based on the continuous closed loop or pulse closed loop mode, an amplitude demodulation module based on the continuous closed loop or pulse closed loop mode, a CPU based on the continuous closed loop or pulse closed loop mode, and a digital controller based on the continuous closed loop or pulse closed loop mode; the CPU based on the continuous closed loop or the pulse closed loop mode is provided with a state machine used for controlling the starting process of the high-frequency cavity, wherein the state machine comprises a closing state s0, a low-power tuning state s1, a pulse searching state s2, a power boosting state s3 and a normal running state s4 in the starting process of the high-frequency cavity; the digital controller based on the continuous closed loop or pulse closed loop mode is provided with a PID tuning algorithm unit, a DSP balance algorithm unit, a Digital Signal Processor (DSP) and a digital signal processor (CPU), receives signals from an analog circuit and realizes communication with the CPU; the PID tuning algorithm unit avoids cavity detuning by accelerating the PID operation rate; the DSP balance algorithm unit ensures the pressure balance of the two groups of cavities by adjusting the capacitor motor;

2. The optimum starting device of the cyclotron according to claim 1, wherein: the continuous closed-loop mode is characterized in that a low-power tuning state, a power lifting state and a normal operation state are set as a continuous signal operation mode, a pulse searching state is set as a pulse signal operation mode, and a tuning closed loop in the low-power tuning state, a tuning closed loop in the power searching state and an amplitude modulation closed loop in the power lifting state are closed loops under continuous signals; the pulse closed-loop mode is characterized in that only the low-power tuning state is set to be a continuous signal operation mode, the power searching state, the power boosting state and the normal operation state are all pulse signal operation modes, only the tuning closed loop in the low-power tuning state is a closed loop in the continuous signal operation mode, the tuning closed loop in the power searching state and the amplitude modulation closed loop in the power boosting state are closed loops in the pulse signals, and the closed loop in the pulse signals is a closed loop judged at the high pulse level.

3. The cyclotron optimized start-up device of claim 2, wherein: the tuning module for searching tuning points based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a cavity Forward signal, a cavity sampling signal Pickup1, a high-frequency switch 2, an amplifier, an attenuator, a phase discriminator, a tuning parameter setting module and a tuning comparator between an accelerator cavity and a CPU; performing subtraction operation on an ADC (analog to digital converter) analog signal led out from the phase discriminator and the tuning parameter setting value, and sending one path of an operation result to a digital controller through the ADC, and sending the other path of the operation result to a tuning comparator; in the low-power tuning and pulse searching states, the tuning comparator adopts continuous signals to judge a tuning closed loop, and when the tuning comparator judges that the cavity frequency and the high-frequency signal frequency are consistent, the tuning closed loop signals PhaseOK are respectively output and sent to the CPU through the digital controller; the cavity Forward signal Forward and the cavity sampling signal Pickup1 are obtained by sampling through a sampling cable after the accelerator cavity is driven by the low level modulation output module in the continuous closed loop or pulse closed loop mode.

4. The cyclotron optimized start-up device of claim 3, wherein: under the low-power tuning state of a continuous closed-loop mode, a pulse-to-continuous circuit of an amplitude demodulation module outputs a pulse signal with 10% duty ratio, a CPU controls a forceCW signal to output a low-level signal, and the output of the pulse-to-continuous circuit is subjected to AND operation, the result is still a low-level signal, and the result is output to a high-frequency switch 1 and a high-frequency switch 2 of the tuning module and a high-voltage switch 3 of a low-level modulation output module through the low-level signal, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of a 25db amplifier of each through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects one path of a 14db attenuator; in a power searching state of a continuous closed-loop mode, a pulse transfer continuous circuit of an amplitude demodulation module outputs a pulse signal with continuously widened duty ratio from 10% -50%, a CPU controls a forceCW signal to output a high-level signal, and the pulse signal output by the pulse transfer continuous circuit is subjected to AND operation, the result is still the pulse signal with continuously widened duty ratio, high-frequency switches 1 and 2 select back and forth between an amplifier and an attenuator according to the pulse signal, and a high-frequency switch 3 also selects back and forth between 3db attenuation and 14db attenuation at the same time, namely when the pulse is high level, the switch 1 and the switch 2 select 23db attenuators, the switch 3 selects 3db attenuation, when the pulse is low level, the switch 1 and the switch 2 select 25db amplifiers, and the switch 3 selects 14db attenuation; under the power boost state and the normal operation state of the continuous closed-loop mode, the output of a pulse continuous circuit of an amplitude demodulation module is a high-level continuous signal, a CPU controls a forceCW signal to output a high-level signal, and the output result of the pulse continuous circuit is subjected to AND operation to obtain a high-level signal, the high-level signal and the operation output result are sent to a high-frequency switch 1, a high-frequency switch 2 and a high-frequency switch 3 of a low-level modulation output module, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of each attenuator through the high-frequency switch 1 and the high-frequency switch 2, and the high-frequency switch 3 is connected with one path of a 3db attenuator.

5. The cyclotron optimized start-up device of claim 3, wherein: under the low-power tuning state of a pulse closed-loop mode, a CPU state machine turns to a low-power tuning state s1 from an off state s0 and sends s1 to a digital controller, the digital controller sends a low-level signal to a high-frequency switch 1 and a high-frequency switch 2 of a tuning module and a high-voltage switch 3 of a low-level modulation output module, a Forward signal Forward and a cavity sampling signal Pickup1 of a cavity are selectively connected with one path of each amplifier through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 selects one path of a 14db attenuator; in a power searching state, a power boosting state and a normal running state of a pulse closed-loop mode, a CPU state machine respectively sends s2, s3 and s4 signals to a digital controller in the pulse closed-loop mode according to a continuous tuning closed-loop signal PhaseOK in a low-power tuning state, a pulse amplitude closed-loop signal PhaseOK in the pulse searching state and a pulse amplitude closed-loop signal VDeeOK in the power boosting state, the digital controller in the pulse closed-loop mode provides a high level for a high-frequency switch 1 and a high-frequency switch 2 of a tuning module and a high-voltage switch 3 of a low-level modulation output module, a Forward signal Forward of a cavity and a cavity sampling signal Pickup1 are selectively connected with one path of each attenuator through the high-frequency switch 1 and the high-frequency switch 2, and the high-voltage switch 3 is connected with one path of a 3db attenuator.

6. The cyclotron optimized start-up device of claim 1, wherein: the amplitude demodulation module based on the continuous closed-loop or pulse closed-loop mode is sequentially provided with a cavity sampling signal Pickup2, a detector, a pulse-to-continuous circuit, an amplitude modulation parameter setting module and an amplitude comparator between the accelerator cavity and the CPU; in a continuous closed-loop mode, after the cavity sampling signal Pickup2 is divided into three centimeters, one path of signal is used for ignition detection and judgment through a differential circuit, and the other two paths of signal are used for inputting a pulse signal or a continuous signal to an AND gate and a CPU (central processing unit) for AND operation after one path of signal passes through a detector 1 and a pulse transfer continuous circuit; one path is used for amplitude closed loop judgment after being detected by the detector 2; under the power boosting state, when the voltage value of the detection result of the detector 1 is different from the amplitude modulation parameter setting, judging that the detection result is in an allowable range, judging that the detection result is amplitude closed loop, and outputting a continuous amplitude closed loop signal VDee _ OK signal to a CPU (central processing unit); in a pulse closed-loop mode, after the cavity sampling signal Pickup is divided into two centimeters by 2, one path is used for ignition detection judgment through a differential circuit, and the other path is used for amplitude closed-loop judgment after being detected by a detector; under the power boosting state, after the voltage value of the detection result of the detector is different from the amplitude modulation parameter setting, if the voltage value is judged to be within the allowable range, the amplitude closed loop is judged, and a pulse amplitude closed loop signal VDee _ OK is output to the CPU.

7. The optimum starting device for cyclotron according to claim 6, wherein: in the pulse to continuous circuit in the continuous closed-loop mode, in the low-power tuning stage, the input of the pulse to continuous circuit is a low-power signal, the output of the pulse to continuous circuit is a signal with a 10% duty ratio, the signal is sent to an AND gate and is subjected to AND operation with a ForceCW controlled by a CPU, and the AND operation result is a low level; in the pulse searching stage, the pulse transfer continuous circuit judges that the current power reaches the power of a low-power tuning closed loop, then the pulse with gradually widened duty ratio is output to an AND gate and is subjected to AND operation with ForceCW controlled by a CPU, the AND gate sends the pulse with gradually widened duty ratio to a high-frequency switch 3, a 14db attenuator is selected and connected when the pulse is in a low level, and a 3db attenuator is selected when the pulse is in a high level, so that pulse widening is realized; in the power boosting stage, the pulse transfer continuous circuit judges that the current power reaches the power of the amplitude closed loop in the pulse searching state, then a continuous signal is output to an AND gate and is subjected to AND operation with a CPU, the output of the AND gate is a continuous high level and is output to a high-frequency switch 3, and the high-frequency switch 3 is connected with one path of a 3db attenuator according to the continuous high level signal.

8. The optimum starting device of the cyclotron according to claim 1, wherein: the low level modulation output module based on the continuous closed loop or pulse closed loop mode is sequentially provided with a high-frequency signal digital-to-analog module, an amplitude-phase modulation module, a 3db attenuator, a 14db attenuator, a high-frequency switch 3, a numerical control attenuator and a low level output signal along the direction from the digital controller to the accelerator cavity; and in a low-power tuning state, the low-level output signal drives the accelerator cavity, so that a cavity Forward signal Forward and a cavity sampling signal Pickup1 of the tuning module are obtained through the sampling cable.

9. The cyclotron optimized start-up device of claim 1, wherein: in the power searching state of the continuous closed-loop mode, after the CPU receives a continuous tuning closed-loop PhaseOK signal in the low-power tuning state, the time that the high-frequency switch 3 is connected with the 3db attenuator and the time that the high-frequency switch 14db attenuator are connected with each other are controlled to be unequal through an AND gate operation result to realize pulse width broadening, and at the moment, the numerical control attenuator is constant; in the power boosting state of the continuous closed-loop mode, after the CPU receives a continuous tuning closed-loop signal PhaseOK in the pulse searching stage, the high-frequency switch 3 is controlled to be connected with the 3db attenuator through an AND gate operation result, and the digital controller is instructed to control the numerical control attenuator to continuously reduce the attenuation, so that the power is continuously boosted until an amplitude modulation comparator of the amplitude demodulation module outputs a continuous amplitude closed-loop VDeeOK signal to the CPU, and at the moment, the power boosting stage is finished, and the normal operation state is entered.

10. The optimum starting device of the cyclotron according to claim 1, wherein: in a power searching state of a pulse closed-loop mode, after a CPU receives a continuous tuning closed-loop PhaseOK signal in a low-power tuning state, a CPU state machine sends a s2 signal to a digital controller, the digital controller sends a pulse with a certain duty ratio to a high-frequency switch 3, the high-frequency switch 3 is connected with one path of a 3db attenuator at the high level of the pulse according to the pulse with the fixed duty ratio, and is connected with one path of a 14db attenuator at the low level of the pulse, and the numerical control attenuator is constant at the moment; in a power boosting state, after receiving a pulse tuning closed-loop signal PhaseOK in a pulse searching state, a CPU (Central processing Unit) sends a signal s3 to a digital controller, the digital controller sends a pulse with a certain duty ratio to a high-frequency switch 3, the high-frequency switch 3 is connected with a 3db attenuator at a pulse high level and connected with a 14db attenuator at a pulse low level according to a pulse with a fixed duty ratio, and meanwhile, the digital controller controls the numerical control attenuator to continuously reduce attenuation and further continuously boost power until an amplitude modulation comparator of an amplitude demodulation module outputs a pulse amplitude closed-loop signal VDeeOK to the CPU, and at the moment, the power boosting stage is completed and a normal operation stage is entered.

11. The cyclotron optimized start-up device of claim 1, wherein: and when the CPU based on the continuous closed loop or pulse closed loop mode receives an amplitude closed loop signal VDeeOK of the amplitude demodulation module and enters a normal operation state, the digital controller starts the DSP balance algorithm unit to balance the cavity pressure between the two cavities.

12. The cyclotron optimized start-up device of claim 1, wherein: the PID tuning algorithm unit of the digital controller based on the continuous closed-loop or pulse closed-loop mode is arranged in the digital controller, and a PID operation module, a data arithmetic logic module and a multi-bus framework are used; the PID tuning algorithm unit describes the PID digital operation algorithm in the assembly language of DSP and realizes the synchronous operation of a plurality of operation instructions by utilizing parallel processing instructions under a multi-bus architecture, thereby accelerating the PID operation speed and avoiding the cavity detuning.

13. The cyclotron optimized start-up device of claim 13, wherein: the PID operation module is provided with a PID operation output y (n) sub-module for driving an accelerator cavity motor, a PID operation output y (n-1) sub-module at the last moment of PID, PID adjustment coefficients K0, K1 and K2 sub-modules, and an x (n), an x (n-1) and an x (n-2) PID input sub-module at the current moment and the last moment and the previous two moments; the data arithmetic logic module comprises a DSP5600 series digital signal processor, the DSP5600 series digital signal processor stores the inputs x (n), x (n-1) and x (n-2) of the PID of the current time, the previous time and the previous two times into a register R0, stores PID adjusting coefficients k0, k1 and k2 into a register R3, reads and writes the two registers by using a global bus, and adopts an assembly instruction to realize y (n) = y (n-1) + k0 x (n) + k1 x (n-1) + k2 x (n-2) by using an accumulator and a multiplication function in the DSP.

14. The cyclotron optimized start-up device of claim 14, wherein: the DSP balance algorithm unit is provided with a voltage balance ratio calculation unit and a voltage balance adjustment unit; the voltage balance ratio calculation unit is used for a ratio relation formula:

15. The cyclotron optimized start-up device of claim 1, wherein: according to the CPU based on the continuous closed loop mode, when in a low-power tuning state, a forcible conversion signal ForceCW of the CPU is 0 value, and when in a power searching, power boosting and normal running state, the forcible conversion signal ForceCW of the CPU is 1 value.