CN115425969B - Method and device for designing compensation filter of phase-locked loop and computer equipment - Google Patents
Method and device for designing compensation filter of phase-locked loop and computer equipment Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The application relates to a method, a device, a computer readable storage medium and a computer program product for designing a compensation filter of a phase-locked loop. The compensating filter design method of the phase-locked loop comprises the following steps: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used to determine a compensation filter that performs compensation filtering on the phase-locked loop. The compensation filter obtained by the method is generated based on the phase-locked loop design, so that the defects in the phase-locked loop filtering process can be fully compensated, the integral filtering effect of the compensation filter and the phase-locked loop after cascading is obviously improved, and the application requirement is fully met.
Description
Technical Field
The present application relates to the field of electronic information technology and wireless communication technology, and in particular, to a method, an apparatus, a computer device, a computer readable storage medium and a computer program product for designing a compensation filter of a phase-locked loop.
Background
The PLL (Phase Locked Loop ) circuit can control the frequency and phase of an oscillation signal in a loop by using an externally input reference signal, so as to realize automatic tracking of the frequency of an output signal to the frequency of an input signal, and is widely applied to communication devices such as a frequency generator and a wireless transceiver.
In PLL loop applications, the filtering effect of the PLL loop itself is poor, and it is difficult to meet the application requirements. Therefore, there is a need to develop a compensation filter that can compensate for the filtering effect of the PLL loop, so that the PLL loop can meet the application requirements.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, apparatus, computer device, computer readable storage medium and computer program product for designing a compensation filter of a phase locked loop to obtain a compensation filter capable of meeting the application requirements of the PLL loop.
In a first aspect, the present application provides a method of compensating filter design for a phase locked loop. The design method comprises the following steps:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form an objective function of a compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop.
In one embodiment, the converting and order supplementing the transfer function to form an objective function of the compensation filter includes:
converting the transfer function to form an initial expression of a compensation filter;
and supplementing a pole expression in the initial expression to obtain an objective function of the compensation filter.
In one embodiment, the converting the transfer function to form an initial expression of the compensation filter includes: and reversing the molecular terms and denominator terms of the transfer function to form an initial expression of the compensation filter.
In one embodiment, the supplementing the pole expression in the initial expression includes:
determining the number to be supplemented of poles to be supplemented of denominators of the initial expression;
determining vector modulus values corresponding to the poles of the number to be supplemented according to the initial expression to obtain each pole to be supplemented;
determining pole expressions corresponding to the poles to be supplemented respectively;
each of the pole expressions is supplemented to a denominator term of the initial expression.
In one embodiment, the determining the number of poles to be supplemented for which the denominator term of the initial expression needs to be supplemented includes:
acquiring the zero number and the pole number of a transfer function of the phase-locked loop;
and determining the number to be supplemented of poles of the denominator term of the initial expression to be supplemented according to the difference value between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the determining, according to the initial expression, a vector modulus value corresponding to the pole of the number to be supplemented includes:
obtaining a model value of each zero point of the initial expression;
and respectively obtaining vector modulus values corresponding to the poles of the number to be supplemented based on the modulus values of the zeros of the initial expression.
In a second aspect, the present application further provides a compensating filter design apparatus for a phase locked loop. The device comprises:
a transfer function acquisition module for determining a transfer function of the phase-locked loop;
the objective function generating module is used for converting and supplementing the transfer function in order to form an objective function of the compensation filter; the objective function is used for compensating and filtering the phase-locked loop by the compensating filter.
In a third aspect, the present application also provides a computer device. The computer device comprises a memory storing a computer program and a processor which when executing the computer program performs the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form an objective function of a compensation filter; the objective function is used for compensating and filtering the phase-locked loop by the compensating filter.
In a fourth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form an objective function of a compensation filter; the objective function is used for compensating and filtering the phase-locked loop by the compensating filter.
In a fifth aspect, the present application also provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form an objective function of a compensation filter; the objective function is used for compensating and filtering the phase-locked loop by the compensating filter.
The method, apparatus, computer device, storage medium and computer program product for designing a compensation filter for a phase-locked loop by determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used to determine a compensation filter that performs compensation filtering on the phase-locked loop. The compensation filter is generated based on the phase-locked loop design, so that the defects in the phase-locked loop filtering process can be fully compensated, the integral filtering effect of the compensation filter and the phase-locked loop after cascading is obviously improved, and the application requirement is fully met.
Drawings
FIG. 1 is an application environment diagram of a compensation filter design method of a phase locked loop in one embodiment;
FIG. 2 is a flow chart of a method of designing a compensation filter of a phase locked loop according to an embodiment;
FIG. 3 is a schematic diagram of an exemplary configuration of a phase locked loop;
FIG. 4 is a schematic diagram of a low pass filter in the phase locked loop of FIG. 3;
FIG. 5 is a partial flow diagram of a method of compensating filter design in one embodiment;
FIG. 6 is a schematic diagram of a cascade connection of a compensation filter and a PLL in an embodiment;
FIG. 7 is a partial flow chart of a method of designing a compensation filter according to another embodiment;
FIG. 8 is a schematic diagram of a filtered DSM-VCO frequency response for the phase locked loop of FIG. 3;
FIG. 9 is a schematic diagram of a compensation filter frequency response of a phase locked loop in one embodiment;
FIG. 10 is a schematic diagram of an overall frequency response of a compensation filter cascaded with a phase locked loop in one embodiment;
FIG. 11 is a block diagram of a compensation filter design apparatus for a phase locked loop in one embodiment;
fig. 12 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The compensation filter design method provided by the embodiment of the application can be applied to an application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104 or may be located on a cloud or other network server. The server 104 determines a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used to determine a compensation filter that performs compensation filtering on the phase-locked loop. The terminal 102 may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things devices, etc. The server 104 may be implemented as an integrated service program in a personal computer terminal, as a stand-alone server, or as a server cluster of multiple servers.
In one embodiment, as shown in fig. 2, a compensation filter design method is provided, and the method is applied to the server 104 in fig. 1 for illustration, and includes the following steps:
step 100, a transfer function of a phase locked loop is determined.
In practical applications, once the phase-locked loop is determined, its transfer function is obtained according to the structure of the phase-locked loop. The method can be that the structural parameters of the phase-locked loop are obtained through the terminal and uploaded to the server, and the transfer function of the phase-locked loop is determined through the server according to the structural parameters of the phase-locked loop. In particular, the step of determining the transfer function of the phase locked loop may comprise: determining a transfer function expression from an input to an output and a low-pass filter transfer function based on the structural parameters of the phase-locked loop; the transfer function of the phase-locked loop is determined by substituting the transfer function of the low-pass filter into the transfer function of the input to the output.
When the phase locked loop is determined, its input to output transfer function can be represented and its internal low pass filter is also determined; and then the transfer function of the low-pass filter is obtained and substituted into the expression of the transfer function of the phase-locked loop input to output containing the transfer function of the low-pass filter, and the corresponding operations such as flux expansion and the like are carried out, so that the transfer function of the phase-locked loop is obtained.
It can be understood that in other embodiments, the transfer function of the phase-locked loop may be directly determined by the terminal according to the structural parameters of the phase-locked loop input by the operator, and then uploaded to the server for subsequent compensation filter design. Alternatively, the terminal may be used to upload the transfer function of the phase-locked loop to the server for subsequent compensation filter design according to the transfer function of the phase-locked loop input by the operator.
The following describes an example of a structural model of a phase locked loop shown in fig. 3, which mainly comprises a low pass filter LPF, a phase and frequency detector PFD, a charge pump CP, a voltage controlled oscillator VCO, a frequency divider MMD and a converter DSM. The converter DSM is configured to convert an input signal to be modulated into a frequency division adjustment signal; the frequency divider MMD divides a clock of a target frequency generated by the voltage controlled oscillator VCO to a reference clock frequency; fref is the reference clock of phase-locked loop operation, and the low-pass filter LPF is an RC low-pass filter composed of a resistor and a capacitor, and its transfer function is H(s).
The transfer function of the phase-locked loop is then the transfer function expression H of DSM input to VCO output dsm-vco The method comprises the following steps:
wherein H is dsm-vco Represents the transfer function of the phase-locked loop, H(s) represents the transfer function of the low pass filter LPF, I CP Representing the charge pump CP current, K VCO Representing the gain of a voltage controlled oscillator VCO, F ref The reference clock representing the phase-locked loop operation, N represents the division ratio, and s represents the laplace operator.
In the phase-locked loop, the low-pass filter LPF is an RC filter, and its specific structure is shown in fig. 4, and the expression of the 3 rd order low-pass filter transfer function H(s) may be determined according to its structure:
wherein a is 1 ＝R 2 C 2 ；b 3 ＝C 1 C 2 C 3 R 2 R 3 ；b 2 ＝C 1 C 2 R 2 +C 1 C 3 R 3 +C 2 C 3 R 2 +C 2 C 3 R 3 ；b 1 ＝C 1 +C 2 +C 3 S represents the Laplace operator, R 2 Represents the resistance value of the resistor R2, R 3 Represents the resistance value of the resistor R3, C 1 Representing the capacitance value of capacitor C1, C 2 Representing the capacitance value of capacitor C2, C 3 Representing the capacitance value of capacitor C3.
When the phase-locked loop is determined, the parameters of each resistor and capacitor are also determined values, so that the transfer function H(s) of the low-pass filter can be obtained, and then H(s) is substituted into the transfer function H of the phase-locked loop dsm-vco . Thereby, the s-domain transfer function of the phase-locked loop is obtained through the phase-locked loop, and a basis is provided for the design of a compensation filter facing the phase-locked loop.
Step 200, converting and order supplementing the transfer function to form an objective function of the compensation filter.
Wherein the objective function is used to determine a compensation filter to compensate for the phase locked loop. Converting the transfer function of the phase-locked loop may include inverting the numerator and denominator terms, and coefficient adjustmentEtc. Since the order in the numerator and denominator of the transfer function of the phase locked loop is different, the order supplement may specifically be to supplement the degree of the low-order polynomial to a degree greater than or equal to the degree of the high-order polynomial. Still with the transfer function H of the loop filter shown in FIG. 3 dsm-vco For example, the expression with the numerator and denominator term reversed contains a single pole p1 and 4 zeroes z 1-z 4, i.e., the denominator term is 1 degree and the numerator term is 4 degrees, and the degree of the 1 degree term of the expression needs to be supplemented to be not less than 4 degrees.
In particular, the transfer function may be converted and supplemented in order in various possible ways, and two of these ways are described below.
In one embodiment, as shown in FIG. 5, step 200 includes step 210 and step 220.
Step 210, converting the transfer function to form an initial expression of the compensation filter.
Wherein step 210 may comprise: the numerator and denominator terms of the transfer function are inverted to form an initial expression of the compensation filter. Specifically, after the numerator term and the denominator term are inverted, that is, the numerator and the denominator of the transfer function are respectively used as the denominator and the numerator of the initial expression of the compensation filter, the step 210 may further include a process of performing coefficient adjustment on the numerator term or the denominator term, and the like.
And 220, supplementing a pole expression in the initial expression to obtain an objective function of the compensation filter.
Because the number of poles and the number of zeros of the expression obtained by inverting the numerator of the transfer function of the phase-locked loop are opposite to the number of poles and the number of zeros of the transfer function of the phase-locked loop, the number of zeros of the initial expression of the compensation filter obtained by inverting the numerator is more than the number of poles, the high-frequency input can be excessively amplified to generate noise, the number of poles needs to be supplemented, the pole expression contains poles needing to be supplemented, and the specific form of the pole expression can be designed according to practical conditions.
Again with the transfer function H of loop filtering shown in fig. 3 dsm-vco For example, the molecular terms andthe initial expression of the compensation filter obtained after the denominator term is reversed is a single-pole point p1 and 4 zero points z 1-z 4; the number of poles to be supplemented, which are needed to be supplemented by the denominator terms, is not less than 3, and the specific number can be designed in combination with the actual implementation, for example, the number of the supplemented poles is 3, namely P-add1, P-add2 and P-add3, and the pole expressions can be (s-P-add 1), (s-P-add 2) and (s-P-add 3). It will be appreciated that the pole expression is only an example, and different coefficients may be designed according to the needs in actual design.
In another embodiment, step 200 comprises: supplementing a zero expression in the transfer function to form an initial expression of the compensation filter; and converting the initial expression to obtain an objective function of the compensation filter.
In the embodiment, a zero expression is supplemented in a transfer function to obtain an initial expression of a supplemental filter; and converting the initial expression to form an objective function of the compensation filter. The number of zero points in the initial expression of the compensation filter is not less than the number of the original points by supplementing zero points in the transfer function of the phase-locked loop, so that the number of the molecular terms is the same as the number of the denominator terms, and the number of poles of the objective function of the compensation filter is not less than the number of the original points after the molecular terms and the denominator terms are subjected to inversion processing. The specific supplementary modes can refer to the above examples, and are not repeated here.
Thus, the objective function of the compensation filter is obtained, after the compensation filter is determined, the compensation filter and the phase-locked loop may be cascaded, referring to fig. 6, in a specific manner, the compensation filter is inserted between the input signal of the converter DSM and the DSM, the compensation filter compensates and filters the low sampling rate signal input by the front-end module to be modulated, and then inputs the low sampling rate signal to the DSM, and the DSM converts the low sampling rate signal into a frequency division adjustment signal with a high sampling rate. Thereby implementing a compensation filter in cascade with the phase locked loop filter.
The compensation filter design method of the phase-locked loop comprises the steps of determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used for compensation filtering of the phase-locked loop by the compensation filter. Because the compensation filter is generated based on the phase-locked loop design, the defect in the phase-locked loop filtering process can be fully compensated, the integral filtering effect of the compensation filter and the phase-locked loop after cascading is obviously improved, the application requirement is fully met, and the accuracy of information transmission is improved.
In one embodiment, as shown in FIG. 7, supplementing the pole expression in the initial expression in step 220 includes:
step 221, determining the number of poles to be supplemented for which the denominator of the initial expression needs to be supplemented.
It can be understood that, in the initial expression of the compensation filter formed by inverting the numerator term and the denominator term of the transfer function of the phase-locked loop, the number of times of the numerator term and the denominator term can be known, and the number of times of the denominator term corresponds to the number of poles, and the number of times of the numerator term corresponds to the number of zeros, so that the number of poles and the number of zeros of the initial expression can be known correspondingly; therefore, in this embodiment, when it is determined that the number of poles is not less than the number of zeros, the denominator term needs the number of poles to be supplemented.
In another embodiment, step 221 may include: acquiring the zero number and the pole number of a transfer function of a phase-locked loop; and determining the number to be supplemented of poles required to be supplemented by the denominator term of the initial expression according to the difference value between the zero number and the pole number of the transfer function of the phase-locked loop. In this way, the number of poles to be supplemented is determined according to the difference between the number of zeros and the number of poles of the transfer function, in particular the number of poles to be supplemented is greater than or equal to the difference between the number of zeros and the number of poles.
And step 222, determining vector modulus values corresponding to poles of the number to be supplemented according to the initial expression, and obtaining the poles to be supplemented.
When the number of poles to be supplemented is determined, the value of each pole to be supplemented needs to be determined. In order to improve the stability of the system, the positions of poles to be supplemented are all positioned on the left half plane of the s plane, and the vector mode of the poles to be supplemented is a plurality of times of the zero vector mode value of the initial compensation filter. Specifically, the refinement step of determining the vector mode of the number of poles to be supplemented includes: obtaining a model value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to poles of the number to be supplemented based on the modulus values of the zeros of the initial expression. Thereby obtaining each pole to be supplemented on the left half plane of the s plane.
Specifically, each zero point of the initial expression can be determined according to the pole of the transfer function of the phase-locked loop, so that the modulus value of each zero point can be obtained. There may be a certain multiple correspondence between the pole vector module to be supplemented and the zero vector module value in the initial expression, for example, the first pole to be supplemented corresponds to a first multiple preset value, the second pole to be supplemented corresponds to a second multiple preset value, the third pole to be supplemented corresponds to a third multiple preset value, and so on. The first multiple preset value, the second multiple preset value, the third multiple preset value and the like can be equal or unequal, and the setting is needed to be carried out according to actual conditions. In the concrete calculation, the modulus value of the first pole to be supplemented (the second pole should be supplemented) is the product of the modulus value of the second zero point of the initial expression and the preset value of the first multiple; the modulus of the second pole to be supplemented (the third pole after supplementation) is the product of the modulus of the third zero of the initial expression and the preset value of the second multiple; the third pole to be supplemented (the fourth pole should be supplemented) has a modulus value which is the product of the modulus value of the fourth zero point of the initial expression and the third preset value; and so on.
Still with the transfer function H in the embodiment of FIG. 3 dsm-vco For example, H dsm-vco The initial expression is a single-pole point p1 and 4 zero points z 1-z 4 when the single-pole point p1 is the single-pole point p1 and the 4 poles z 1-z 4 are the single-pole points; assuming that three poles are added to the power supply, the value of the first multiple preset value can be-192 to-64, the value of the second multiple preset value can be-32 to-16, and the value of the third multiple preset value can be-4. The first pole module to be supplemented may be-96 abs (z 2), the second pole module to be supplemented may be-16 abs (z 3), and the third pole module to be supplemented may be-4 abs (z 4). Where z2, z3, z4 are the second, third, and fourth zeros of the initial expression, and abs () function represents the calculated absolute value or vector modulus.
Step 223, determining pole expressions corresponding to the poles to be supplemented respectively. After the pole is determined, the pole expression can be designed correspondingly according to the requirement.
In step 224, each pole expression is supplemented to the denominator term of the initial expression. The supplementing mode can be that each pole expression is directly multiplied with the original denominator, or multiplied with the original denominator after being multiplied by a preset multiple, so that the target function formula of the compensation filter is determined, and the design of the compensation filter is completed.
It should be noted that the transfer function H of the loop filter shown in FIG. 3 dsm-vco For a single zero p1,4 poles z 1-z 4 are distributed in the s-plane corresponding to low to high frequencies. Reference is made to figure 8,H dsm-vco The pass signal bandwidth (flat section) of the amplitude-frequency response of the loop filter is small, and the phase delay of the phase-frequency response is large.
The compensation filter design of the application can achieve two purposes: 1) High-frequency boosting, so that a compensation filter and a phase-locked loop cascade filtering amplitude-frequency characteristic flat section extends to high frequency; 2) Phase compensation such that the phase delay of the compensation filter and phase locked loop cascading filtering effect is minimized (less than Tsymbol/50) and nearly linearized.
The frequency response curve of the compensation filter designed by the application is shown in fig. 9, the overall filter frequency response curve of the compensation filter and the phase-locked loop after the cascade connection is shown in fig. 10, and it can be determined that the overall filter effect of the compensation filter and the phase-locked loop after the cascade connection achieves amplitude-frequency response planarization, phase response quasi-linearization and delay minimization. The compensation filter can achieve two effects of high-frequency lifting and phase compensation, the filtering amplitude-frequency characteristic flat section after cascading with the phase-locked loop extends to high frequency, the overall filtering phase delay is obviously reduced, and the phase-frequency curve from low frequency to high frequency passband section is close to linear phase, so that the application requirement is satisfied.
It should be further noted that, after the objective function of the compensation filter is obtained, the compensation filter design method provided by the embodiment of the application can be implemented by using an analog circuit, or can be implemented by using a digital circuit through converting bilinear transformation into z-domain.
For a better understanding of the above embodiments, the following detailed explanation is made in connection with a specific embodiment. The embodiment still refers to the phase-locked loop structure shown in fig. 3, and takes the phase-locked loop as shown in fig. 3 as an example, the compensation filter designed by the compensation filter design method includes the following steps:
(1) Determining a transfer function H of a phase locked loop dsm-vco ；
(2) Will H dsm-vco The transfer function numerator and denominator are reversed, so that an initial expression of the compensation filter consisting of the single pole p1 and the 4 zero points z 1-z 4 is obtained;
(3) Supplementing 3 poles such that the number of poles equals the number of zeros;
(4) And determining the value of a supplementary pole, wherein the supplementary poles are all positioned on the left half plane of the s plane, and the vector mode of the supplementary pole is a plurality of times of the vector mode value of the zero point of the initial compensation filter. Taking p_add 1= -96 x abs (z 2), p_add 2= -16 x abs (z 3), p_add 3= -4 x abs (z 4);
(5) And determining a pole expression comprising each pole, and supplementing the pole expression to a denominator term of the initial expression to obtain an objective function of the supplementing filter.
The compensation filter designed as above is used for being inserted between an input signal of a DSM and the DSM in a phase-locked loop, and is in filter cascade connection with the phase-locked loop, the total filter phase delay after cascade connection is obviously reduced, and the phase-frequency curve from low frequency to high frequency passband is close to linear phase. Referring to fig. 8 to 10, the compensated overall amplitude-frequency response flat portion is extended to 1MHz, and the overall phase response is adjusted to: the phase frequency response of 0-10 khz is 0degree, 6degree is 1Mhz, and 20 k-1 Mhz is close to the linear phase, and the integral delay of the cascade filtering after compensation is not more than Tsymbol/60 (6 degree/360degree corresponds to Tsymbol/60), namely the integral filtering effect achieves a plurality of targets of high-frequency lifting expansion low-pass filtering bandwidth, linearization of phase response and minimum delay. The method can meet the time domain synchronization requirements of modulating the amplitude and the phase of input signals when adopting a polar coordinate transmitting mode in wideband communication such as GSM-EDGE (Global System for Mobile Communications-Enhanced Data Rate for GSM Evolution, global System for Mobile communication-enhanced data rate GSM evolution technology), wide area Internet of things, spread spectrum communication and the like.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a compensation filter design device for realizing the above-mentioned compensation filter design method. The implementation of the solution provided by the device is similar to that described in the above method, so the specific limitations in the embodiments of the compensation filter design device or devices provided below can be referred to above for the limitations of the compensation filter design method, which are not repeated here.
In one embodiment, there is provided a compensating filter design apparatus of a phase locked loop, as shown in fig. 11, including: a transfer function acquisition module 10 and an objective function generation module 20, wherein: the transfer function obtaining module 10 is used for determining a transfer function of the phase-locked loop; the objective function generating module 20 is configured to convert and supplement the transfer function to form an objective function of the compensation filter.
The compensation filter obtained by the compensation filter design device of the phase-locked loop can achieve two effects of high-frequency lifting and phase compensation, the flat section of the filtering amplitude-frequency characteristic after cascading with the phase-locked loop extends to high frequency, the overall filtering phase delay is obviously reduced, the phase-frequency curve from low frequency to high-frequency passband section is close to linear phase, the overall filtering effect is obviously improved, and application requirements are met.
In one embodiment, the objective function generation module includes a conversion unit and an order supplementation unit; the conversion unit is used for converting the transfer function to form an initial expression of the compensation filter; the order supplementing unit is used for supplementing the pole expression in the initial expression to obtain the objective function of the compensation filter.
The respective modules in the compensation filter design apparatus described above may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a server, and the internal structure of which may be as shown in fig. 12. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used for storing compensation filter design related data of the phase locked loop. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a compensation filter design method for a phase locked loop.
It will be appreciated by those skilled in the art that the structure shown in FIG. 12 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor when executing the computer program performing the steps of: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used to determine a compensation filter that performs compensation filtering on the phase-locked loop.
In one embodiment, the processor when executing the computer program further performs the steps of: converting the transfer function to form an initial expression of the compensation filter; and supplementing the pole expression in the initial expression to obtain the objective function of the compensation filter.
In one embodiment, the processor when executing the computer program further performs the steps of: the numerator and denominator terms of the transfer function are inverted to form an initial expression of the compensation filter.
In one embodiment, the processor when executing the computer program further performs the steps of: determining the number to be supplemented of poles to be supplemented of denominators of the initial expression; determining vector modulus values corresponding to poles of the number to be supplemented according to the initial expression to obtain poles to be supplemented; determining pole expressions corresponding to poles to be supplemented respectively; each pole expression is supplemented to the denominator term of the initial expression.
In one embodiment, the processor when executing the computer program further performs the steps of: acquiring the zero number and the pole number of a transfer function of a phase-locked loop; and determining the number to be supplemented of poles required to be supplemented by the denominator term of the initial expression according to the difference value between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the processor when executing the computer program further performs the steps of: obtaining a model value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to poles of the number to be supplemented based on the modulus values of the zeros of the initial expression.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used to determine a compensation filter that performs compensation filtering on the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: converting the transfer function to form an initial expression of the compensation filter; and supplementing the pole expression in the initial expression to obtain the objective function of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: the numerator and denominator terms of the transfer function are inverted to form an initial expression of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining the number to be supplemented of poles to be supplemented of denominators of the initial expression; determining vector modulus values corresponding to poles of the number to be supplemented according to the initial expression to obtain poles to be supplemented; determining pole expressions corresponding to poles to be supplemented respectively; each pole expression is supplemented to the denominator term of the initial expression.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring the zero number and the pole number of a transfer function of a phase-locked loop; and determining the number to be supplemented of poles required to be supplemented by the denominator term of the initial expression according to the difference value between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: obtaining a model value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to poles of the number to be supplemented based on the modulus values of the zeros of the initial expression.
In one embodiment, a computer program product is provided comprising a computer program which, when executed by a processor, performs the steps of: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form an objective function of the compensation filter; the objective function is used to determine a compensation filter that performs compensation filtering on the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: converting the transfer function to form an initial expression of the compensation filter; and supplementing the pole expression in the initial expression to obtain the objective function of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: the numerator and denominator terms of the transfer function are inverted to form an initial expression of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining the number to be supplemented of poles to be supplemented of denominators of the initial expression; determining vector modulus values corresponding to poles of the number to be supplemented according to the initial expression to obtain poles to be supplemented; determining pole expressions corresponding to poles to be supplemented respectively; each pole expression is supplemented to the denominator term of the initial expression.
In one embodiment, the computer program when executed by the processor further performs the steps of: acquiring the zero number and the pole number of a transfer function of a phase-locked loop; and determining the number to be supplemented of poles required to be supplemented by the denominator term of the initial expression according to the difference value between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: obtaining a model value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to poles of the number to be supplemented based on the modulus values of the zeros of the initial expression.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (6)
1. A method of designing a compensation filter for a phase locked loop, the method comprising the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form an objective function of a compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop;
the conversion and order supplementation of the transfer function form an objective function of a compensation filter, comprising:
converting the transfer function to form an initial expression of a compensation filter;
supplementing a pole expression in the initial expression to obtain an objective function of the compensation filter;
said converting said transfer function to form an initial expression of a compensation filter, comprising: inverting the molecular term and the denominator term of the transfer function to form an initial expression of the compensation filter;
the supplementing the pole expression in the initial expression comprises:
determining the number to be supplemented of poles to be supplemented of denominators of the initial expression; the number of poles of the expression of the compensation filter formed after the poles are supplemented is not smaller than the number of zero points;
determining pole values corresponding to poles of the number to be supplemented according to the initial expression to obtain poles to be supplemented;
determining pole expressions corresponding to the poles to be supplemented respectively;
supplementing each pole expression to a denominator term of the initial expression;
the determining the pole value corresponding to the poles of the number to be supplemented according to the initial expression comprises the following steps:
obtaining a model value of each zero point of the initial expression;
based on the modulus value of each zero point of the initial expression, pole values corresponding to the poles of the number to be supplemented are obtained respectively; the pole value of the pole to be supplemented is located in the negative value interval of the horizontal axis of the Laplace transformation s plane, and the modulus value of the pole to be supplemented is 4 times, 16 to 32 times or 64 to 192 times of the modulus value of the zero point in the corresponding initial expression.
2. The method of designing a compensation filter for a phase locked loop according to claim 1, wherein said determining the number of poles to be supplemented by the denominator term of the initial expression includes:
acquiring the zero number and the pole number of a transfer function of the phase-locked loop;
and determining the number to be supplemented of poles of the denominator term of the initial expression to be supplemented according to the difference value between the zero number and the pole number of the transfer function of the phase-locked loop.
3. The method of designing a compensation filter for a phase locked loop of claim 1, wherein said determining a transfer function of the phase locked loop comprises:
determining a transfer function expression from an input to an output and a low-pass filter transfer function based on the structural parameters of the phase-locked loop;
the transfer function of the phase-locked loop is determined by substituting the transfer function of the low-pass filter into the transfer function of the input to the output.
4. A compensation filter design apparatus for a phase locked loop, the apparatus comprising:
a transfer function acquisition module for determining a transfer function of the phase-locked loop;
the objective function generating module is used for converting and supplementing the transfer function in order to form an objective function of the compensation filter; the objective function is used for the compensation filter to carry out compensation filtering on the phase-locked loop;
the objective function generation module comprises a conversion unit and an order supplementing unit; the conversion unit is used for converting the transfer function to form an initial expression of the compensation filter; the order supplementing unit is used for supplementing a pole expression in the initial expression to obtain an objective function of the compensation filter;
said converting said transfer function to form an initial expression of a compensation filter, comprising: inverting the molecular term and the denominator term of the transfer function to form an initial expression of the compensation filter;
the supplementing the pole expression in the initial expression comprises:
determining the number to be supplemented of poles to be supplemented of denominators of the initial expression; the number of poles of the expression of the compensation filter formed after the poles are supplemented is not smaller than the number of zero points;
determining pole values corresponding to poles of the number to be supplemented according to the initial expression to obtain poles to be supplemented;
determining pole expressions corresponding to the poles to be supplemented respectively;
supplementing each pole expression to a denominator term of the initial expression;
the determining the pole value corresponding to the poles of the number to be supplemented according to the initial expression comprises the following steps:
obtaining a model value of each zero point of the initial expression;
based on the modulus value of each zero point of the initial expression, pole values corresponding to the poles of the number to be supplemented are obtained respectively; the pole value of the pole to be supplemented is located in the negative value interval of the horizontal axis of the Laplace transformation s plane, and the modulus value of the pole to be supplemented is 4 times, 16 to 32 times or 64 to 192 times of the modulus value of the zero point in the corresponding initial expression.
5. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any one of claims 1 to 3 when the computer program is executed.
6. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 3.
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