CN115425969A - Method and device for designing compensation filter of phase-locked loop and computer equipment - Google Patents
Method and device for designing compensation filter of phase-locked loop and computer equipment Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/40—Arrangements for reducing harmonics
Abstract
The application relates to a method, an apparatus, a computer device, a computer readable storage medium and a computer program product for designing a compensation filter of a phase locked loop. The design method of the compensation filter of the phase-locked loop comprises the following steps: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop. The compensation filter obtained by the method is generated based on the design of the phase-locked loop, can fully compensate the defects in the filtering process of the phase-locked loop, obviously improves the overall filtering effect after the compensation filter and the phase-locked loop are cascaded, and fully meets the application requirements.
Description
Technical Field
The present application relates to the field of electronic information technology and wireless communication technology, and in particular, to a method and an apparatus for designing a compensation filter of a phase-locked loop, a computer device, a computer-readable storage medium, and a computer program product.
Background
A PLL (Phase Locked Loop) circuit can control the frequency and Phase of an oscillation signal inside a Loop by using an externally input reference signal, thereby realizing automatic tracking of an output signal frequency to an input signal frequency, and is often applied to communication devices such as a frequency generator and a wireless transceiver.
In the application of the PLL loop, the filtering effect of the PLL loop is poor, and the application requirement is difficult to meet. Therefore, it is desirable to develop a compensation filter capable of compensating the filtering effect of the PLL loop, so that the PLL loop can meet the application requirements.
Disclosure of Invention
In view of the above, it is necessary to provide a method, an apparatus, a computer device, a computer readable storage medium, and a computer program product for designing a compensation filter of a phase-locked loop to obtain a compensation filter capable of meeting the application requirements of a PLL loop.
In a first aspect, the present application provides a method for designing a compensation filter of a phase-locked loop. The design method comprises the following steps:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form a target function of a compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop.
In one embodiment, the converting and order supplementing the transfer function to form an objective function of a compensation filter includes:
converting the transfer function to form an initial expression of a compensation filter;
and supplementing a pole expression in the initial expression to obtain an objective function of the compensation filter.
In one embodiment, the converting the transfer function to form an initial expression of a compensation filter includes: and carrying out inversion processing on the numerator item and the denominator item of the transfer function to form an initial expression of the compensation filter.
In one embodiment, said supplementing the pole expression in the initial expression includes:
determining the number to be supplemented of poles to be supplemented of denominator terms of the initial expression;
determining vector module values corresponding to the number to be supplemented according to the initial expression to obtain each pole to be supplemented;
determining a pole expression corresponding to each pole to be supplemented;
and supplementing each pole expression to a denominator term of the initial expression.
In one embodiment, the determining the number to be supplemented of poles to be supplemented to the denominator term of the initial expression includes:
acquiring the number of zero points and the number of poles of a transfer function of the phase-locked loop;
and determining the number of poles to be supplemented of the denominator term of the initial expression according to the difference between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the determining, according to the initial expression, a vector modulus value corresponding to the number to be supplemented includes:
obtaining the modulus value of each zero point of the initial expression;
and respectively obtaining vector module values corresponding to the number to be supplemented based on the module values of all the zero points of the initial expression.
In a second aspect, the present application further provides a device for designing a compensation filter of a phase-locked loop. The device comprises:
the transfer function acquisition module is used for determining the transfer function of the phase-locked loop;
the target function generating module is used for converting and supplementing orders of the transfer function to form a target function of the compensation filter; the objective function is used for the compensation filter to perform compensation filtering on the phase-locked loop.
In a third aspect, the application also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the following steps when executing the computer program:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form a target function of a compensation filter; the objective function is used for the compensation filter to perform compensation filtering on the phase-locked loop.
In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form a target function of a compensation filter; the objective function is used for the compensation filter to perform compensation filtering on the phase-locked loop.
In a fifth aspect, the present application further provides a computer program product. The computer program product comprising a computer program which when executed by a processor performs the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form a target function of a compensation filter; the objective function is used for the compensation filter to perform compensation filtering on the phase-locked loop.
The method, apparatus, computer device, storage medium and computer program product for designing a compensation filter of a phase-locked loop described above, by determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop. The compensation filter is generated based on the design of the phase-locked loop, so that the defects in the filtering process of the phase-locked loop can be fully compensated, the integral filtering effect of the compensation filter after the compensation filter is cascaded with the phase-locked loop is obviously improved, and the application requirements are fully met.
Drawings
FIG. 1 is a diagram of an exemplary implementation of a method for designing a compensation filter for a phase locked loop;
FIG. 2 is a flow diagram illustrating a method for designing a compensation filter for a phase locked loop according to one embodiment;
FIG. 3 is a diagram illustrating an exemplary structure of a phase-locked loop;
fig. 4 is a schematic diagram of a low pass filter in the phase locked loop of fig. 3;
FIG. 5 is a schematic flow chart diagram of a portion of a method for designing a compensation filter in one embodiment;
FIG. 6 is a schematic diagram of a cascade of a compensation filter and a PLL according to one embodiment;
FIG. 7 is a schematic flow chart diagram of a portion of a method for designing a compensation filter in accordance with another embodiment;
FIG. 8 is a schematic diagram of a filtered DSM-VCO frequency response of the phase locked loop of FIG. 3;
FIG. 9 is a schematic diagram of a compensation filter frequency response of a phase locked loop according to an embodiment;
FIG. 10 is a schematic diagram of the overall frequency response of the cascade of the compensation filter and the phase-locked loop in one embodiment;
FIG. 11 is a block diagram of an apparatus for designing a compensation filter for a phase locked loop in one embodiment;
FIG. 12 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
The method for designing the compensation filter provided by the embodiment of the application can be applied to the application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104, or may be located on the cloud or other network server. The server 104 determines a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop. The terminal 102 may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things devices, and the like. The server 104 may be implemented as an integrated service program in a personal computer terminal, a stand-alone server, or a server cluster consisting of a plurality of servers.
In one embodiment, as shown in fig. 2, a method for designing a compensation filter is provided, which is described by taking the method as an example applied to the server 104 in fig. 1, and includes the following steps:
In practical applications, once the phase-locked loop is determined, the transfer function of the phase-locked loop can be obtained according to the structure of the phase-locked loop. The method includes that a terminal acquires and uploads structural parameters of a phase-locked loop to a server, and the server analyzes and determines a transfer function of the phase-locked loop according to the structural parameters of the phase-locked loop. Specifically, the step of determining the transfer function of the phase-locked loop may include: determining a transfer function expression and a low-pass filter transfer function from input to output of the phase-locked loop based on the structural parameters of the phase-locked loop; the low pass filter transfer function is substituted into the input to output transfer function to determine the transfer function of the phase locked loop.
When the phase-locked loop is determined, the transfer function from the input to the output can be expressed, and the low-pass filter in the phase-locked loop is also determined; and then, the transfer function of the low-pass filter is calculated and substituted into the expression of the input-output transfer function of the phase-locked loop containing the transfer function of the low-pass filter, and corresponding calculations such as division expansion are carried out to obtain the transfer function of the phase-locked loop.
It is to be understood that, in other embodiments, the transfer function of the phase-locked loop may also be directly determined by the terminal according to the structural parameters of the phase-locked loop input by the operator, and then the transfer function of the phase-locked loop is uploaded to the server for subsequent design of the compensation filter. Or, the terminal may upload the transfer function of the phase-locked loop to the server for subsequent compensation filter design according to the transfer function of the phase-locked loop input by the operator.
The following description will be given by taking a structural model of the phase-locked loop shown in fig. 3 as an example, where the phase-locked loop mainly includes a low-pass filter LPF, a phase detection discriminator PFD, a charge pump CP, a voltage-controlled oscillator VCO, a frequency divider MMD, and a converter DSM. The converter DSM is used for converting an input signal to be modulated into a frequency division adjusting signal; the frequency divider MMD divides the clock of the target frequency generated by the voltage-controlled oscillator VCO to a reference clock frequency; fref is a reference clock for the operation of the phase-locked loop, and the low-pass filter LPF is an RC low-pass filter consisting of a resistor and a capacitor and has a transfer function of H(s).
The transfer function of the phase-locked loop is expressed by the transfer function expression H of DSM input to VCO output dsm-vco Comprises the following steps:
wherein H dsm-vco Representing the transfer function of the phase locked loop, H(s) representing the transfer function of the low pass filter LPF, I CP Representing the charge pump CP current, K VCO Representing the gain, F, of a voltage-controlled oscillator VCO ref The reference clock at which the phase locked loop operates is indicated, N denotes the division ratio, and s denotes the laplacian operator.
In the phase-locked loop, the low-pass filter LPF is an RC filter, and the specific structure thereof is as shown in fig. 4, and the expression of the transfer function H(s) of the 3 rd order low-pass filter can be determined according to the structure:
wherein, a 1 ＝R 2 C 2 ；b 3 ＝C 1 C 2 C 3 R 2 R 3 ；b 2 ＝C 1 C 2 R 2 +C 1 C 3 R 3 +C 2 C 3 R 2 +C 2 C 3 R 3 ；b 1 ＝C 1 +C 2 +C 3 S represents the Laplace operator, R 2 Denotes the resistance of the resistor R2, R 3 Represents the resistance value of the resistor R3, C 1 Represents the capacity value of the capacitor C1, C 2 Represents the capacity value of the capacitor C2, C 3 Representing the value of the capacity of the capacitor C3.
When phase-locked loopWhen the parameters are determined, the parameters of each resistor and each capacitor are also determined values, so that the transfer function H(s) of the low-pass filter can be obtained, and then the transfer function H(s) is substituted into the transfer function H which can obtain a phase-locked loop dsm-vco . Therefore, the s-domain transfer function of the phase-locked loop is obtained through the phase-locked loop, and a basis is provided for the design of a compensation filter facing the phase-locked loop.
Step 200, the transfer function is converted and supplemented with orders to form the target function of the compensation filter.
The objective function is used for determining a compensation filter to perform compensation filtering on the phase-locked loop. Converting the transfer function of the phase-locked loop may include numerator and denominator term inversion, coefficient adjustment, and the like. Since the order in the numerator term and the denominator term of the transfer function of the phase-locked loop is different, the order supplementation may specifically be to supplement the order of the low-order polynomial to be greater than or equal to the order of the high-order polynomial. The transfer function H of the loop filter is still as shown in FIG. 3 dsm-vco For example, the expression with the numerator and denominator terms reversed includes a unipolar point p1 and 4 zero points z1 to z4, that is, the denominator term is 1 time, and the numerator term is 4 times, and the number of the expression of the 1-time term needs to be supplemented to be not less than 4 times.
In particular, when the transfer function is converted and order supplemented, it can be obtained in various possible ways, and the following description is made in combination with two ways.
In one embodiment, as shown in FIG. 5, step 200 includes steps 210 and 220.
Step 210, the transfer function is converted to form an initial expression of the compensation filter.
Wherein, step 210 may include: and inverting the numerator term and the denominator term of the transfer function to form an initial expression of the compensation filter. Specifically, after the numerator and denominator terms are inverted, that is, the numerator and denominator of the transfer function are respectively used as the denominator and the numerator of the initial expression of the compensation filter, the step 210 may further include performing coefficient adjustment and other processing procedures on the numerator terms or the denominator terms.
And step 220, supplementing the pole expression in the initial expression to obtain the target function of the compensation filter.
The pole number and the zero number of the expression obtained by inverting the numerator of the transfer function of the phase-locked loop are opposite to the pole number and the zero number of the transfer function of the phase-locked loop, the zero number of the initial expression of the compensation filter obtained by inverting the numerator is more than the pole number, noise is generated by excessively amplifying high-frequency input, the pole number needs to be supplemented, the pole expression comprises poles needing to be supplemented, and the specific form of the pole expression can be designed according to actual conditions.
Again with the transfer function H of the loop filter shown in fig. 3 dsm-vco For example, the initial expression of the compensation filter obtained by inverting the numerator term and the denominator term is a single pole p1 and 4 zeros z1 to z4; the number of poles to be supplemented, the denominator term of which needs to be supplemented, is not less than 3, the specific number can be designed by combining with the reality, for example, the number of supplemented poles is 3, which are respectively P-add1, P-add2 and P-add3, and the pole expressions can be (s-P-add 1), (s-P-add 2) and (s-P-add 3). It is understood that the pole expression is only an example, and different coefficients and the like can be designed according to needs in actual design.
In another embodiment, step 200 comprises: supplementing a zero expression in the transfer function to form an initial expression of the compensation filter; and converting the initial expression to obtain the target function of the compensation filter.
In the embodiment, a zero expression is supplemented in a transfer function to obtain an initial expression of a supplementary filter; and converting the initial expression to form an objective function of the compensation filter. The zero in the transfer function of the phase-locked loop is supplemented, so that the number of times of a numerator term is the same as that of a denominator term, the number of the zero in an initial expression of the compensation filter is not less than that of an origin, and the numerator term and the denominator term are reversed, so that the number of poles of an objective function of the compensation filter is not less than that of the origin. For a specific supplementary manner, reference may be made to the above example, which is not described herein again.
The target function of the compensation filter is thus obtained, after the compensation filter is determined, the compensation filter may be cascaded with the phase-locked loop, referring to fig. 6, the cascade mode may specifically be that the compensation filter is inserted between the input signal of the converter DSM, the compensation filter performs compensation filtering on the low-sampling-rate signal input by the front-end module to be modulated, and then inputs the low-sampling-rate signal to the DSM, and the DSM converts the low-sampling-rate signal into a frequency division adjustment signal with a high sampling rate. Therefore, the filter cascade of the compensation filter and the phase-locked loop is realized.
The design method of the compensation filter of the phase-locked loop determines the transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for the compensation filter to perform compensation filtering on the phase-locked loop. The compensation filter is generated based on the design of the phase-locked loop, so that the defects in the filtering process of the phase-locked loop can be fully compensated, the integral filtering effect after the compensation filter and the phase-locked loop are cascaded is remarkably improved, the application requirements are fully met, and the accuracy of information transmission is improved.
In one embodiment, as shown in fig. 7, step 220 complements the pole expression in the initial expression, including:
step 221, determining the number of poles to be supplemented to which the denominator term of the initial expression needs to be supplemented.
It can be understood that, in the initial expression of the compensation filter formed by inverting the numerator term and the denominator term of the transfer function of the phase-locked loop, the times of the numerator term and the denominator term are known, and because the times of the denominator term correspond to the number of poles and the times of the numerator term correspond to the number of zeros, the numbers of the poles and the zeros of the initial expression are known; therefore, in the embodiment, when the number of poles is determined to be not less than the number of zeros, the number of poles to be supplemented, which needs to be supplemented by the denominator term, can be determined.
In another embodiment, step 221 may comprise: acquiring the number of zero points and the number of poles of a transfer function of a phase-locked loop; and determining the number of poles to be supplemented of the denominator term of the initial expression according to the difference between the zero number and the pole number of the transfer function of the phase-locked loop. In this way, the number of poles to be compensated is determined from the difference between the number of zeros and the number of poles of the transfer function, in particular, the number of poles to be compensated is greater than or equal to the difference between the number of zeros and the number of poles.
Step 222, determining vector module values corresponding to the number to be supplemented according to the initial expression to obtain each pole to be supplemented.
After the number of poles to be supplemented is determined, the value of each pole to be supplemented needs to be determined. In order to improve the stability of the system, the positions of poles to be compensated are all located on the left half plane of the s plane, and the vector module of the poles to be compensated is several times of the module value of the zero vector of the initial compensation filter. Specifically, the step of refining the vector mode for determining the number of poles to be supplemented comprises the following steps: obtaining the modulus value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to the number to be supplemented based on the modulus values of the zero points of the initial expression. Thereby obtaining each pole to be supplemented on the left half plane of the s plane.
Specifically, each zero of the initial expression may be determined according to a pole of a transfer function of the phase-locked loop, so that a modulus of each zero may be obtained. A certain multiple correspondence relationship may exist between the pole vector norm to be supplemented and the zero vector norm value in the initial expression, for example, a first pole to be supplemented corresponds to a first multiple preset value, a second pole to be supplemented corresponds to a second multiple preset value, a third pole to be supplemented corresponds to a third multiple preset value, and so on. The first multiple preset value, the second multiple preset value, the third multiple preset value and the like can be equal or unequal, and need to be set in combination with actual conditions. During specific calculation, the module value of the first pole to be supplemented (the second pole after the supplementation) is the product of the module value of the second zero of the initial expression and the first multiple preset value; the modulus of the second pole to be supplemented (the third pole after the supplementation) is the product of the modulus of the third zero of the initial expression and a second multiplier preset value; the modulus of the third pole to be supplemented (the fourth pole after the supplementation) is the product of the modulus of the fourth zero of the initial expression and a third multiple preset value; and so on.
Still with the transfer function H in the embodiment of FIG. 3 dsm-vco For example, H dsm-vco The initial expression is a single zero point p1 and 4 pole points z 1-z 4, and the initial expression is a single pole point p1 and 4 zero points z 1-z 4; assuming that three poles are supplemented, the value of the first multiple preset value can be-192 to-64, the value of the second multiple preset value can be-32 to-16, and the value of the third multiple preset value can be-4. The first pole norm to be supplemented may be-96 × abs (z 2), the second pole norm to be supplemented may be-16 × abs (z 3), and the third pole norm to be supplemented may be-4 × abs (z 4). Wherein z2, z3, z4 are the second, third, and fourth zeros of the initial expression, and the abs () function represents the calculation of the absolute value or vector modulo value.
And step 223, determining pole expressions corresponding to the poles to be supplemented respectively. After the pole is determined, the pole expression can be designed accordingly as needed.
In step 224, the pole expressions are supplemented to the denominator terms of the initial expression. The compensation mode can be that each pole expression is directly multiplied by the original denominator item, or multiplied by the original denominator item after being multiplied by a preset multiple, so that the target function of the compensation filter is determined, and the design of the compensation filter is completed.
It should also be noted that the transfer function H of the loop filter shown in fig. 3 dsm-vco The single zero point p1,4 poles z 1-z 4, and 4 poles z 1-z 4 are distributed on the s-plane corresponding to low frequency to high frequency. Referring to FIG. 8, H dsm-vco The bandwidth (flat segment) of the signal passing through the loop filter is small, and the phase delay of the phase-frequency response is large.
The compensation filter design of the present application can achieve two objectives: 1) The high frequency is improved, so that the compensation filter and the cascaded filtering amplitude-frequency characteristic flat section of the phase-locked loop extend to the high frequency; 2) And phase compensation, so that the phase delay of the cascaded filtering effect of the compensation filter and the phase-locked loop is minimized (less than Tsymbol/50) and is close to linearization.
The frequency response curve of the compensation filter designed by the application is shown in fig. 9, and the overall filtering frequency response curve after the compensation filter and the phase-locked loop are in filtering cascade connection is shown in fig. 10, so that the overall filtering effect after the compensation filter and the phase-locked loop are in cascade connection can be determined to achieve amplitude-frequency response flattening, phase response quasi-linearization and delay minimization. The compensation filter can achieve two effects of high-frequency promotion and phase compensation, the flat section of the amplitude-frequency characteristic of the filtering after the compensation filter is cascaded with a phase-locked loop extends to high frequency, the total filtering phase delay is obviously reduced, and the phase-frequency curve of the low-frequency to high-frequency passband section is close to a linear phase, so that the application requirement is sufficiently met.
It should be further noted that, after the objective function of the compensation filter is obtained by the compensation filter design method provided in the embodiment of the present application, the compensation filter can be designed by using an analog circuit, and can also be designed by using a digital circuit after being converted into a z-domain through bilinear transformation.
For a better understanding of the above embodiments, the following detailed description is given in conjunction with a specific embodiment. Referring to the phase-locked loop structure shown in fig. 3, the present embodiment will be described by taking the compensation filter designed by the compensation filter design method facing the phase-locked loop shown in fig. 3 as an example, and the compensation filter design method includes the following steps:
(1) Determining a transfer function H of a phase locked loop dsm-vco ；
(2) H is to be dsm-vco Inverting the numerator and denominator of the transfer function to obtain an initial expression of the compensation filter consisting of the unipolar point p1 and the zero points z 1-z 4 of the 4;
(3) Supplementing 3 poles so that the number of poles is equal to the number of zeros;
(4) And determining values of the supplementary poles, wherein the supplementary poles are all positioned on the left half plane of the s plane, and the vector mode of the supplementary poles is a plurality of times of the zero vector mode value of the initial compensation filter. Taking p _ add1= -96 abs (z 2), p _ add2= -16 abs (z 3), p _ add3= -4 abs (z 4);
(5) And determining a pole expression comprising each pole, and supplementing the pole expression to a denominator term of the initial expression to obtain an objective function of the supplementary filter.
The compensation filter designed above is used for being inserted between an input signal of the DSM in the phase-locked loop and the DSM, and is in filtering cascade connection with the phase-locked loop, the overall filtering phase delay is obviously reduced after the cascade connection, and a phase-frequency curve from a low frequency to a high frequency passband section is close to a linear phase. Referring to fig. 8-10, the flat portion of the overall amplitude-frequency response after compensation is extended to 1MHz, and the overall phase response is adjusted to: the phase frequency response of 0-10 khz, 0degree,1Mhz, 6degree,2 k-1 Mhz is close to the linear phase, the integral delay of the cascade filtering after compensation does not exceed Tsymbol/60 (Tsymbol/60 corresponds to 6degree/360 degree), namely the integral filtering effect achieves the aims of high-frequency promotion and expansion of low-pass filtering bandwidth, phase response linearization and minimum delay. The method can meet the requirements on the time domain synchronization of the amplitude and the phase of the modulation input signal when a polar coordinate transmission mode is adopted in broadband communication such as GSM-EDGE (Global System for Mobile Communications-Enhanced Data Rate for GSM Evolution), wide area Internet of things, spread spectrum communication and the like.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
Based on the same inventive concept, the embodiment of the present application further provides a compensation filter design apparatus for implementing the above-mentioned compensation filter design method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so the specific limitations in one or more embodiments of the compensation filter design apparatus provided below may refer to the limitations on the compensation filter design method in the foregoing, and details are not described here again.
In one embodiment, there is provided a compensation filter design apparatus of a phase locked loop, as shown in fig. 11, the compensation filter design apparatus including: a transfer function obtaining module 10 and an objective function generating module 20, wherein: the transfer function obtaining module 10 is configured to determine a transfer function of the phase-locked loop; the objective function generating module 20 is used for converting and order supplementing the transfer function to form the objective function of the compensation filter.
The compensation filter obtained by the compensation filter design device of the phase-locked loop can achieve two effects of high-frequency promotion and phase compensation, the flat section of the filtering amplitude-frequency characteristic extends to high frequency after being cascaded with the phase-locked loop, the total filtering phase delay is obviously reduced, the phase-frequency curve from the low frequency to the high-frequency passband section is close to a linear phase, the integral filtering effect is obviously promoted, and the application requirement is sufficiently met.
In one embodiment, the objective function generation module includes a conversion unit and an order supplementation unit; the conversion unit is used for converting the transfer function to form an initial expression of the compensation filter; and the order supplementing unit is used for supplementing the pole expression in the initial expression to obtain an objective function of the compensation filter.
The various modules in the compensation filter design apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 12. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The database of the computer device is used for storing data related to the design of the compensating filter of the phase-locked loop. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of compensating filter design for a phase locked loop.
Those skilled in the art will appreciate that the architecture shown in fig. 12 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory having a computer program stored therein and a processor that when executing the computer program performs the steps of: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop.
In one embodiment, the processor when executing the computer program further performs the steps of: converting the transfer function to form an initial expression of the compensation filter; and supplementing the pole expression in the initial expression to obtain an objective function of the compensation filter.
In one embodiment, the processor when executing the computer program further performs the steps of: and inverting the numerator term and the denominator term of the transfer function to form an initial expression of the compensation filter.
In one embodiment, the processor, when executing the computer program, further performs the steps of: determining the number of poles to be supplemented which need to be supplemented by the denominator term of the initial expression; determining vector module values corresponding to the number to be supplemented according to the initial expression to obtain each pole to be supplemented; determining pole expressions corresponding to poles to be supplemented respectively; the pole expressions are supplemented to the denominator terms of the initial expression.
In one embodiment, the processor, when executing the computer program, further performs the steps of: acquiring the number of zero points and the number of poles of a transfer function of a phase-locked loop; and determining the number of poles to be supplemented of the denominator term of the initial expression according to the difference between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the processor, when executing the computer program, further performs the steps of: obtaining the modulus value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to the number to be supplemented based on the modulus values of all the zero points of the initial expression.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: converting the transfer function to form an initial expression of the compensation filter; and supplementing the pole expression in the initial expression to obtain an objective function of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: and inverting the numerator term and the denominator term of the transfer function to form an initial expression of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining the number of poles to be supplemented which need to be supplemented by the denominator item of the initial expression; determining vector module values corresponding to the number to be supplemented according to the initial expression to obtain each pole to be supplemented; determining pole expressions corresponding to poles to be supplemented respectively; the pole expressions are supplemented to the denominator terms of the initial expression.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring the number of zero points and the number of poles of a transfer function of a phase-locked loop; and determining the number of poles to be supplemented of the denominator term of the initial expression according to the difference between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: obtaining the modulus value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to the number to be supplemented based on the modulus values of the zero points of the initial expression.
In one embodiment, a computer program product is provided, comprising a computer program which when executed by a processor performs the steps of: determining a transfer function of the phase-locked loop; converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: converting the transfer function to form an initial expression of the compensation filter; and supplementing the pole expression in the initial expression to obtain an objective function of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: and inverting the numerator term and denominator term of the transfer function to form an initial expression of the compensation filter.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining the number of poles to be supplemented which need to be supplemented by the denominator term of the initial expression; determining vector module values corresponding to the number to be supplemented according to the initial expression to obtain each pole to be supplemented; determining pole expressions corresponding to poles to be supplemented respectively; the pole expressions are supplemented to the denominator terms of the initial expression.
In one embodiment, the computer program when executed by the processor further performs the steps of: acquiring the number of zeros and the number of poles of a transfer function of a phase-locked loop; and determining the number of poles to be supplemented of the denominator term of the initial expression according to the difference between the zero number and the pole number of the transfer function of the phase-locked loop.
In one embodiment, the computer program when executed by the processor further performs the steps of: obtaining the modulus value of each zero point of the initial expression; and respectively obtaining vector modulus values corresponding to the number to be supplemented based on the modulus values of all the zero points of the initial expression.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in the embodiments provided herein can include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), for example. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A method for designing a compensation filter for a phase locked loop, the method comprising the steps of:
determining a transfer function of the phase-locked loop;
converting and order supplementing the transfer function to form a target function of a compensation filter; the objective function is used for determining a compensation filter and performing compensation filtering on the phase-locked loop.
2. The method as claimed in claim 1, wherein the converting and order supplementing the transfer function to form an objective function of the compensation filter comprises:
converting the transfer function to form an initial expression of a compensation filter;
and supplementing a pole expression in the initial expression to obtain an objective function of the compensation filter.
3. The method of claim 2, wherein said converting the transfer function to form an initial expression of a compensation filter comprises:
and carrying out inversion processing on the numerator item and the denominator item of the transfer function to form an initial expression of the compensation filter.
4. The method of claim 3, wherein said supplementing the pole expression in the initial expression comprises:
determining the number to be supplemented of poles to be supplemented of denominator terms of the initial expression;
determining vector module values corresponding to the number to be supplemented according to the initial expression to obtain each pole to be supplemented;
determining a pole expression corresponding to each pole to be supplemented;
each pole expression is supplemented to the denominator term of the initial expression.
5. The method of claim 4, wherein said determining the number of poles to be compensated for which the denominator term of the initial expression needs to be compensated comprises:
acquiring the number of zero points and the number of poles of a transfer function of the phase-locked loop;
and determining the number of poles to be supplemented of the denominator term of the initial expression according to the difference between the zero number and the pole number of the transfer function of the phase-locked loop.
6. The method as claimed in claim 5, wherein said determining the vector mode value corresponding to the number to be compensated according to the initial expression comprises:
obtaining the modulus value of each zero point of the initial expression;
and respectively obtaining vector modulus values corresponding to the number to be supplemented based on the modulus values of all the zero points of the initial expression.
7. An apparatus for designing a compensation filter for a phase locked loop, the apparatus comprising:
the transfer function acquisition module is used for determining the transfer function of the phase-locked loop;
the target function generating module is used for converting and order supplementing the transfer function to form a target function of the compensation filter; the objective function is used for the compensation filter to perform compensation filtering on the phase-locked loop.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 6.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.
10. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 6 when executed by a processor.
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