CN115425953A - Parameter measuring circuit, parameter measuring method, chip and equipment of digital signal - Google Patents
Parameter measuring circuit, parameter measuring method, chip and equipment of digital signal Download PDFInfo
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Abstract
The application discloses a parameter measuring circuit, a parameter measuring method, a chip and equipment of digital signals, and belongs to the technical field of chips. Respectively converting each path of digital signals input simultaneously into a path of pulse signals along a conversion module; the logic operation module performs logic operation on each path of pulse signal to obtain a logic operation pulse signal, wherein each pulse in the logic operation pulse signal represents signal turnover meeting preset conditions in each path of digital signal; the first measurement component controls the parameter calculation module to sample the timer according to the logical operation pulse signal to obtain a reference time value; the second measurement component samples each digital signal according to the logic operation pulse signal control parameter calculation module to obtain a reference signal value; and the parameter calculation module calculates the parameter of each digital signal according to the reference time value and the reference signal value. This application has reduced the measurement cost through two measuring component measurement multichannel digital signal's parameter.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a parameter measuring circuit, a parameter measuring method, a chip and equipment of digital signals.
Background
In industrial control, motor control and on-board system applications, a large number of digital signals need to be measured. For example, in an ultrasonic radar application, a plurality of digital signals with different frequencies and different duty ratios are input, and the frequency and the duty ratio of the digital signals need to be measured.
In the related art, a digital signal parameter measuring circuit includes a measuring component, and the measuring component can only measure one digital signal. When a plurality of sets of digital signals need to be measured, a plurality of measuring components need to be arranged, and the measuring cost is high.
Disclosure of Invention
The embodiment of the application provides a parameter measurement circuit, a parameter measurement method, a chip and equipment of digital signals, which are used for solving the problem of overhigh measurement cost caused by the fact that a plurality of measurement components are required to be arranged when a plurality of groups of digital signals are measured. The technical scheme is as follows:
in one aspect, a parameter measurement circuit for a digital signal is provided, the parameter measurement circuit comprising:
the edge conversion module is used for converting each path of digital signals input simultaneously into a path of pulse signals respectively;
the logic operation module is used for performing logic operation on each path of pulse signal to obtain a logic operation pulse signal, wherein each pulse in the logic operation pulse signal represents one signal turnover meeting a preset condition in each path of digital signal;
the first measurement component is used for sampling the timer according to the logic operation pulse signal control parameter calculation module to obtain a reference time value;
the second measurement component is used for controlling the parameter calculation module to sample each path of digital signals according to the logic operation pulse signals to obtain reference signal values;
the parameter calculating module is further configured to calculate a parameter of each digital signal according to the reference time value and the reference signal value.
In a possible implementation manner, when the pulse signal is a positive pulse signal, the logical operation module is configured to perform an or operation on each path of positive pulse signal to obtain a logical operation pulse signal;
and when the pulse signal is a negative pulse signal, the logic operation module is used for performing AND operation on each negative pulse signal to obtain a logic operation pulse signal.
In a possible implementation manner, the parameter calculation module is further configured to obtain a reference signal value and a reference time value that have the same sampling time, assign the reference time value to a digital signal corresponding to the reference signal value, and calculate a parameter of the digital signal according to the reference time value.
In a possible implementation manner, the first measurement component is further configured to send a first interrupt request to the parameter calculation module every time one pulse in the logic operation pulse signal is received;
the parameter calculating module is further configured to sample the timer according to the first interrupt request to obtain a reference time value.
In a possible implementation manner, the second measurement component is further configured to send a second interrupt request to the parameter calculation module every time one pulse in the logic operation pulse signal is received;
and the parameter calculation module is further configured to sample each path of digital signals according to the second interrupt request to obtain a reference signal value.
In a possible implementation manner, the edge conversion module is further configured to convert each rising edge in each path of digital signal into a pulse, so as to obtain a path of pulse signal; or,
the edge conversion module is further used for converting each falling edge in each path of digital signal into a pulse to obtain a path of pulse signal; or,
the edge conversion module is further configured to convert each rising edge in each path of digital signal into a pulse, and convert each falling edge in each path of digital signal into a pulse, so as to obtain a path of pulse signal.
In one possible implementation, when the pulse signal is converted from a rising edge and a falling edge, the parameter includes at least one of a period, a frequency, and a duty cycle of the digital signal.
In one aspect, a method for measuring parameters of a digital signal is provided, and is applied to a circuit for measuring parameters of a digital signal, and the method includes:
converting each path of digital signals input simultaneously into a path of pulse signals respectively;
performing logic operation on each path of pulse signals to obtain logic operation pulse signals, wherein each pulse in the logic operation pulse signals represents signal turnover meeting preset conditions in each path of digital signals;
sampling a timer according to the logic operation pulse signal to obtain a reference time value;
sampling each path of digital signals according to the logic operation pulse signals to obtain reference signal values;
and calculating the parameter of each digital signal according to the reference time value and the reference signal value.
In one aspect, a system-on-chip is provided, which includes the digital signal parameter measurement circuit as described above.
In one aspect, an in-vehicle device is provided, and the in-vehicle device includes the system chip as described above.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
the method comprises the steps of carrying out logic operation on pulse signals converted from various paths of digital signals to obtain logic operation pulse signals, then sampling a timer according to the logic operation pulse signals to obtain reference time values, sampling each path of digital signals according to the logic operation pulse signals to obtain reference signal values, and because each pulse in the logic operation pulse signals represents signal turnover meeting preset conditions in the various paths of digital signals once, the reference time values sampled simultaneously can be distributed to the paths of digital signals when the reference signal values are sampled, the reference time values of the digital signals can be obtained, and therefore the parameters of the digital signals can be calculated according to the reference time values.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a circuit for measuring a parameter of a digital signal according to the related art;
FIG. 2 is a timing diagram of a parameter measurement circuit according to the related art;
FIG. 3 is a schematic diagram of a circuit for measuring a parameter of a digital signal according to an embodiment of the present application;
FIG. 4 is a timing diagram illustrating measurement of a parameter measurement circuit according to an embodiment of the present application;
FIG. 5 is a flow chart of a method for measuring a parameter of a digital signal according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a system chip provided by an embodiment of the present application;
FIG. 7 is a schematic diagram of an in-vehicle device provided in an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
In the related art, a parameter measuring circuit of a digital signal only includes a measuring component, and the measuring component can only measure one path of digital signal. Specifically, the parameter measuring circuit includes an edge conversion module, a measurement component (capture), a timer (timer) and a Central Processing Unit (CPU)/Direct Memory Access (DMA). The edge conversion module is connected with a first input end of the measurement component, the timer is connected with a second input end of the measurement component, and the CPU/DMA is respectively connected with a first output end and a second output end of the measurement component.
The edge conversion module is used for converting one path of input digital signals into one path of pulse signals. For example, when the frequency and the duty ratio of the digital signal need to be measured, the edge conversion module converts each rising edge of an input path of digital signal into a pulse, and converts each falling edge of the digital signal into a pulse, so as to obtain a path of pulse signal. The measurement component is used for sending an interrupt request to the CPU/DMA when receiving one pulse in one path of pulse signals. The CPU/DMA is used for sampling the timer through the measuring component when the interrupt request is received to obtain a reference time value.
Taking the parameter measurement circuit shown in fig. 1 as an example, the parameter measurement process of the digital signal is as follows:
1. the edge conversion module converts the input digital signal cpt _ in into a pulse signal cpt _ edge _ in, and the pulse signal cpt _ edge _ in is output to the measurement component through a first input end of the measurement component;
2. the measurement component generates an interrupt request when receiving one pulse in the pulse signal cpt _ edge _ in, and outputs the interrupt request to the CPU/DMA through the first output end;
3. and when the CPU/DMA receives an interrupt request, the timer is sampled through the second output port of the measurement component to obtain a reference time value.
4. The CPU/DMA calculates the frequency and duty ratio of the digital signal cpt _ in from the obtained series of reference time values.
Taking the measurement timing chart shown in fig. 2 as an example, a pulse is generated at the rising edge of the first period of the digital signal cpt _ in, and at this time, the timer is sampled to obtain a first reference time value t1; a pulse is generated at the falling edge of the first period of the digital signal cpt _ in, at this time, the timer is sampled to obtain a second reference time value t2, and the high level time of the digital signal cpt _ in is obtained by subtracting the first reference time value t1 from the second reference time value t 2. Then, a pulse is generated at the rising edge of the second period of the digital signal cpt _ in, at this time, the timer is sampled to obtain a third reference time value t3, the third reference time value t3 is subtracted by the second reference time value t2 to obtain the low level time of the digital signal cpt _ in, and the third reference time value t3 is subtracted by the first reference time value t1 to obtain the period of the digital signal cpt _ in. The frequency of the digital signal cpt _ in = 1/(t 3-t 1), and the duty ratio of the digital signal cpt _ in = (t 2-t 1)/(t 3-t 1).
When the parameter measuring circuit is used for measuring the parameters of the digital signals, the parameter measuring circuit can only measure one path of digital signals, and if the parameters of a plurality of paths of digital signals need to be measured, a measuring component needs to be respectively arranged in the parameter measuring circuit for each path of digital signals. For example, when the parameters of 24 digital signals need to be measured, 24 measurement components need to be arranged in the parameter measurement circuit, thereby increasing the measurement cost.
In order to solve the above technical problem, the present embodiment discloses a parameter measurement circuit for digital signals, which can measure parameters of multiple paths of digital signals through two measurement components, thereby reducing measurement cost.
Referring to fig. 3, a schematic diagram of a digital signal parameter measurement circuit according to an embodiment of the present disclosure is shown, where the digital signal parameter measurement circuit can be applied to a system on a chip. The parameter measuring circuit can comprise an edge conversion module, a logic operation module, a first measuring component, a second measuring component and a parameter calculation module.
Since the application scenario of this embodiment is to measure the parameters of multiple paths of digital signals input simultaneously, and each path of digital signal needs to be edge-converted by one edge conversion module, the number of edge conversion modules in the parameter measurement circuit can be set as required, so that the number of edge conversion modules is greater than or equal to the number of paths of digital signals input simultaneously. For example, when the parameters of N digital signals need to be measured, the number of edge conversion modules in the parameter measurement circuit can be set to be greater than or equal to N, wherein N is greater than or equal to 2.
And the edge conversion module is used for converting each path of digital signals input simultaneously into a path of pulse signals respectively. Taking the N +1 paths of digital signals as an example for description, the N +1 edge converting modules convert the input N +1 paths of digital signals into N +1 paths of pulse signals. For example, the parameter measurement circuit receives N +1 paths of digital signals cpt _ in [ N: 0] at the same time, the 0 th edge conversion module converts the input 0 th path of digital signals cpt _ in0 into the 0 th path of pulse signals cpt _ edge _ in0, the 1 st edge conversion module converts the input 1 st path of digital signals cpt _ in1 into the 1 st path of pulse signals cpt _ edge _ in1, \8230, the nth edge conversion module converts the input nth path of digital signals cpt _ inN into the nth path of pulse signals cpt _ edge _ inN, and finally obtains the N +1 paths of pulse signals cpt _ edge _ in [ N: 0].
The digital signal comprises two edges, namely a rising edge and a falling edge, the edge conversion module can set an edge conversion strategy for only converting the rising edge in the digital signal when converting the digital signal into the pulse signal, and at the moment, the edge conversion module is also used for converting each rising edge in each path of digital signal into a pulse to obtain a path of pulse signal; or, an edge conversion strategy for only converting the falling edge in the digital signal may be set, and at this time, the edge conversion module is further configured to convert each falling edge in each path of digital signal into a pulse to obtain a path of pulse signal; or, an edge conversion strategy for converting rising edges and falling edges in the digital signals may be set, and at this time, the edge conversion module is further configured to convert each rising edge in each path of digital signals into one pulse, and convert each falling edge in each path of digital signals into one pulse, so as to obtain one path of pulse signals.
The edge inversion strategy is the same for all edge inversion modules during one measurement. That is, all edge conversion modules convert only rising edges of the digital signal, or all edge conversion modules convert only falling edges of the digital signal, or all edge conversion modules convert both rising edges and falling edges of the digital signal.
Before each measurement, the edge inversion strategy of the edge inversion module may be set according to the parameters that need to be measured. In one example, when the parameter to be measured includes at least one of a period, a frequency, and a duty cycle of the digital signal, the edge conversion strategy of the edge conversion module is to convert a rising edge and a falling edge of the digital signal.
The pulse signal comprises a positive pulse signal and a negative pulse signal, and when the edge conversion module converts the digital signal into the pulse signal, a pulse conversion strategy for converting the digital signal into the positive pulse signal can be set, or a pulse conversion strategy for converting the digital signal into the negative pulse signal can be set.
The pulse inversion strategy is the same along all inversion modules at each measurement run. That is, all edge conversion modules convert the digital signal into a positive pulse signal, or all edge conversion modules convert the digital signal into a negative pulse signal.
And the logic operation module is used for performing logic operation on each path of pulse signal to obtain a logic operation pulse signal, and each pulse in the logic operation pulse signal represents signal inversion meeting a preset condition in each path of digital signal.
The logical operation is one of an and operation and an or operation. When the pulse signal is a positive pulse signal, the logic operation module is used for performing OR operation on each path of positive pulse signal to obtain a logic operation pulse signal; when the pulse signal is a negative pulse signal, the logic operation module is used for performing AND operation on each negative pulse signal to obtain a logic operation pulse signal.
Each pulse in the logic operation pulse signal represents a signal inversion which meets a preset condition in each path of digital signals. For example, when the edge inversion strategy is to invert a rising edge in the digital signal, the preset condition is to flip from a low level to a high level, and each pulse represents a rising edge in each path of the digital signal; when the edge conversion strategy is to convert a falling edge in the digital signal, the preset condition is that the digital signal is converted from a high level to a low level, and each pulse represents a falling edge in each path of digital signal; when the edge inversion strategy is to invert rising and falling edges in the digital signal, the preset conditions are to flip from low to high and from high to low, and each pulse represents a rising or a falling edge in each digital signal.
And the first measurement component is used for sampling the timer according to the logic operation pulse signal control parameter calculation module to obtain a reference time value. Specifically, the first measurement component is further configured to send a first interrupt request to the parameter calculation module every time a pulse in the logic operation pulse signal is received; and the parameter calculation module is also used for sampling the timer according to the first interrupt request to obtain a reference time value.
And the second measurement component is used for sampling each path of digital signals according to the logic operation pulse signal control parameter calculation module to obtain a reference signal value. Specifically, the second measurement component is further configured to send a second interrupt request to the parameter calculation module every time a pulse in the logic operation pulse signal is received; and the parameter calculation module is also used for sampling each path of digital signals according to the second interrupt request to obtain a reference signal value.
And the parameter calculation module is also used for calculating the parameter of each path of digital signal according to the reference time value and the reference signal value. The parameter calculation module referred to herein may be a CPU/DMA.
In one example, the parameter calculating module is further configured to obtain a reference signal value and a reference time value at the same sampling time, assign the reference time value to the digital signal corresponding to the reference signal value, and calculate the parameter of the digital signal according to the reference time value.
For easy understanding, taking the parameters of 3 digital signals to be measured as an example, the parameter measurement process is as follows:
1. the 3 edge conversion modules convert the 3 paths of digital signals cpt _ in [2] input simultaneously into pulse signals cpt _ edge _ in [2], and output the pulse signals cpt _ edge _ in [2] to an OR logic operation module (OR).
It should be noted that, here, the pulse signal is taken as a positive pulse signal for example, and the logical operation module is an or logical operation module.
2. The or logic operation module performs or operation on the pulse signal cpt _ edge _ in [2] to obtain a path of logic operation pulse signal cpt _ or _ in, and outputs the logic operation pulse signal cpt _ or _ in to the first measurement component (capture 0) and the second measurement component (capture 1) respectively.
3. The first measurement component generates a first interrupt request each time a pulse in the logic operation pulse signal cpt _ or _ in is received, and outputs the first interrupt request to a parameter calculation module (CPU/DMA).
4. And the parameter calculation module (CPU/DMA) samples the timer through the first measurement component to obtain a reference time value when receiving each first interrupt request.
5. The second measurement component generates a second interrupt request each time a pulse in the logic operation pulse signal cpt _ or _ in is received, and outputs the second interrupt request to a parameter calculation module (CPU/DMA).
6. And the parameter calculation module (CPU/DMA) samples the 3-path digital signal cpt _ in [2 ].
6. The CPU/DMA acquires a reference signal value and a reference time value with the same sampling time, assigns the reference time value to a digital signal corresponding to the reference signal value, and calculates the frequency and the duty ratio of the 3-channel digital signal cpt _ in [0] according to the reference time value.
Taking the timing chart of fig. 4 as an example, a pulse is generated at the rising edge of the first period of the digital signal cpt _ in [1], and the timer is sampled to obtain a first reference time value t1; generating a pulse at the rising edge of the first period of the digital signal cpt _ in [0], and sampling the timer to obtain a second reference time value t2; generating a pulse at the falling edge of the first period of the digital signal cpt _ in [1], and sampling the timer to obtain a third reference time value t3; generating a pulse at the rising edge of the first period of the digital signal cpt _ in [2], and sampling the timer to obtain a fourth reference time value t4; generating a pulse at the rising edge of the second period of the digital signal cpt _ in [1], at which time the timer is sampled to obtain a fifth reference time value t5; generating a pulse at the falling edge of the first period of the digital signal cpt _ in [0], and sampling the timer to obtain a sixth reference time value t6; generating a pulse at the falling edge of the second period of the digital signal cpt _ in [1], and sampling the timer to obtain a seventh reference time value t7; generating a pulse at the falling edge of the first period of the digital signal cpt _ in [2], and sampling the timer to obtain an eighth reference time value t8; generating a pulse at the rising edge of the third period of the digital signal cpt _ in [1], and sampling the timer to obtain a ninth reference time value t9; generating a pulse at the rising edge of the second period of the digital signal cpt _ in [0], at which time the timer is sampled to obtain a tenth reference time value t10; generating a pulse at the falling edge of the third period of the digital signal cpt _ in [1], and sampling the timer to obtain an eleventh reference time value t11; generating a pulse at the falling edge of the second period of the digital signal cpt _ in [0], and sampling the timer to obtain a twelfth reference time value t12; a pulse is generated at the rising edge of the second cycle of the digital signal cpt _ in [2], when the timer is sampled to obtain a thirteenth reference time value t13.
The CPU/DMA allocates reference time values t2, t6, t10, and t12 to the digital signal cpt _ in [0], the period = t10-t2, the frequency = 1/(t 10-t 2), and the duty = (t 6-t 2)/(t 10-t 2) of the digital signal cpt _ in [ 0].
The CPU/DMA allocates reference time values t1, t3, t5, t7, t9, and t11 to the digital signal cpt _ in [1], a period = t5-t1, a frequency = 1/(t 5-t 1), and a duty = (t 3-t 1)/(t 5-t 1) of the digital signal cpt _ in [1 ].
The CPU/DMA allocates reference time values t4, t8, and t13 to the digital signal cpt _ in [2], the period of the digital signal cpt _ in [2] = t13-t4, the frequency = 1/(t 13-t 4), and the duty = (t 8-t 4)/(t 13-t 4).
In the embodiment, when the parameters of the N paths of digital signals need to be measured, the measurement can be realized by only N-2 measurement components, so that the hardware overhead can be saved, and the measurement cost is reduced.
To sum up, the parameter measuring circuit for digital signals according to the embodiment of the present application obtains a logic operation pulse signal by performing logic operation on a pulse signal into which each digital signal is converted, and then samples a timer according to the logic operation pulse signal to obtain a reference time value, and samples each digital signal according to the logic operation pulse signal to obtain a reference signal value.
Referring to fig. 5, a flowchart of a method for measuring parameters of a digital signal according to an embodiment of the present application is shown. The parameter measurement method of the digital signal can comprise the following steps:
The digital signal comprises two edges of a rising edge and a falling edge, when the digital signal is converted into the pulse signal, an edge conversion strategy only converting the rising edge in the digital signal can be set, and at the moment, each rising edge in each path of digital signal is converted into a pulse to obtain a path of pulse signal; or, an edge conversion strategy for only converting the falling edge in the digital signal may be set, and at this time, each falling edge in each path of digital signal is converted into a pulse to obtain a path of pulse signal; or, an edge conversion strategy for converting the rising edge and the falling edge in the digital signal may be set, where each rising edge in each digital signal is converted into a pulse, and each falling edge in each digital signal is converted into a pulse, so as to obtain one pulse signal.
During one measurement, the edge conversion strategies corresponding to all the digital signals are the same. That is, only the rising edges of all the digital signals are inverted, or only the falling edges of all the digital signals are inverted, or both the rising edges and the falling edges of all the digital signals are inverted.
Before each measurement, the edge transition strategy may be set according to the parameters that need to be measured. In one example, when the parameter to be measured includes at least one of a period, a frequency, and a duty cycle of the digital signal, the edge inversion strategy is to invert rising and falling edges of the digital signal.
The pulse signal includes both a positive pulse signal and a negative pulse signal, and when converting a digital signal into a pulse signal, a pulse conversion strategy for converting the digital signal into a positive pulse signal may be set, or a pulse conversion strategy for converting the digital signal into a negative pulse signal may be set.
The pulse conversion strategy corresponding to all digital signals is the same during each measurement process. That is, all digital signals are converted into positive pulse signals, or all digital signals are converted into negative pulse signals.
The logical operation is one of an and operation and an or operation. When the pulse signal is a positive pulse signal, performing OR operation on each path of positive pulse signal to obtain a logic operation pulse signal; and when the pulse signal is a negative pulse signal, performing AND operation on each negative pulse signal to obtain a logic operation pulse signal.
Each pulse in the logic operation pulse signal represents a signal inversion which meets a preset condition in each path of digital signal. For example, when the edge inversion strategy is to invert a rising edge in the digital signal, the preset condition is to flip from a low level to a high level, and each pulse represents a rising edge in each path of the digital signal; when the edge conversion strategy is to convert a falling edge in the digital signal, the preset condition is that the digital signal is converted from a high level to a low level, and each pulse represents a falling edge in each path of digital signal; when the edge inversion strategy is to invert rising edges and falling edges in the digital signals, the preset conditions are to invert from low level to high level and from high level to low level, and each pulse represents a rising edge or a falling edge in each digital signal.
And 503, sampling the timer according to the logic operation pulse signal to obtain a reference time value.
Specifically, each time one pulse in the logic operation pulse signal is received, the timer is sampled to obtain a reference time value.
And step 504, sampling each path of digital signals according to the logic operation pulse signals to obtain reference signal values.
Specifically, each channel of digital signals is sampled to obtain a reference signal value when one pulse in the logic operation pulse signal is received.
And 505, calculating the parameter of each digital signal according to the reference time value and the reference signal value.
Specifically, a reference signal value and a reference time value with the same sampling time are obtained, the reference time value is assigned to the digital signal corresponding to the reference signal value, and the parameter of the digital signal is calculated according to the reference time value.
In the embodiment, when the parameters of the N paths of digital signals need to be measured, the measurement can be realized only by N-2 measurement components, so that the hardware overhead can be saved, and the measurement cost is reduced.
To sum up, in the method for measuring parameters of digital signals provided in the embodiments of the present application, a logic operation pulse signal is obtained by performing a logic operation on a pulse signal converted from each digital signal, and then a reference time value is obtained by sampling a timer according to the logic operation pulse signal, and each digital signal is sampled according to the logic operation pulse signal to obtain a reference signal value.
Referring to fig. 6, a block diagram of a system chip 100 including the digital signal parameter measurement circuit 10 according to the embodiment is shown.
Referring to fig. 7, a block diagram of a vehicle-mounted device 1000 including the system chip 100 of the foregoing embodiment according to an embodiment of the present disclosure is shown.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description should not be taken as limiting the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.
Claims (10)
1. A parameter measurement circuit for a digital signal, said parameter measurement circuit comprising:
the edge conversion module is used for converting each path of digital signals input simultaneously into a path of pulse signals respectively;
the logic operation module is used for performing logic operation on each path of pulse signal to obtain a logic operation pulse signal, wherein each pulse in the logic operation pulse signal represents one signal turnover meeting a preset condition in each path of digital signal;
the first measurement component is used for sampling the timer according to the logic operation pulse signal control parameter calculation module to obtain a reference time value;
the second measurement component is used for controlling the parameter calculation module to sample each path of digital signals according to the logic operation pulse signals to obtain reference signal values;
and the parameter calculation module is also used for calculating the parameter of each path of digital signal according to the reference time value and the reference signal value.
2. The digital signal parameter measuring circuit according to claim 1,
when the pulse signal is a positive pulse signal, the logic operation module is used for performing OR operation on each path of positive pulse signal to obtain a logic operation pulse signal;
and when the pulse signal is a negative pulse signal, the logic operation module is used for performing AND operation on each negative pulse signal to obtain a logic operation pulse signal.
3. The circuit of claim 1, wherein the parameter calculating module is further configured to obtain a reference signal value and a reference time value with the same sampling time, assign the reference time value to the digital signal corresponding to the reference signal value, and calculate the parameter of the digital signal according to the reference time value.
4. The digital signal parameter measuring circuit according to claim 1,
the first measurement component is further configured to send a first interrupt request to the parameter calculation module every time a pulse in the logical operation pulse signal is received;
the parameter calculating module is further configured to sample the timer according to the first interrupt request to obtain a reference time value.
5. The digital signal parameter measuring circuit according to claim 1,
the second measurement component is further configured to send a second interrupt request to the parameter calculation module every time a pulse in the logical operation pulse signal is received;
and the parameter calculation module is further configured to sample each path of digital signals according to the second interrupt request to obtain a reference signal value.
6. The digital signal parameter measurement circuit according to any one of claims 1 to 5,
the edge conversion module is also used for converting each rising edge in each path of digital signal into a pulse to obtain a path of pulse signal; or,
the edge conversion module is further used for converting each falling edge in each path of digital signal into a pulse to obtain a path of pulse signal; or,
the edge conversion module is further configured to convert each rising edge in each path of digital signal into a pulse, and convert each falling edge in each path of digital signal into a pulse, so as to obtain a path of pulse signal.
7. The circuit according to claim 6, wherein the parameter comprises at least one of a period, a frequency, and a duty ratio of the digital signal when the pulse signal is converted from a rising edge and a falling edge.
8. A method for measuring parameters of a digital signal, the method being applied to a circuit for measuring parameters of a digital signal, the method comprising:
converting each path of digital signals input simultaneously into a path of pulse signals respectively;
performing logic operation on each path of pulse signals to obtain logic operation pulse signals, wherein each pulse in the logic operation pulse signals represents signal turnover meeting preset conditions in each path of digital signals;
sampling a timer according to the logic operation pulse signal to obtain a reference time value;
sampling each path of digital signals according to the logic operation pulse signals to obtain reference signal values;
and calculating the parameters of each digital signal according to the reference time value and the reference signal value.
9. A system-on-chip comprising a digital signal parametric measurement circuit according to any of claims 1 to 7.
10. An in-vehicle apparatus characterized by comprising the system chip according to claim 9.
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| CN112242842A (en) * | 2019-07-18 | 2021-01-19 | 三星电子株式会社 | Phase Locked Loop (PLL) circuit including sub-sampling circuit and clock generator |
| CN114090361A (en) * | 2022-01-20 | 2022-02-25 | 南京芯驰半导体科技有限公司 | IO signal monitoring circuit and implementation method |
| CN114441860A (en) * | 2022-04-07 | 2022-05-06 | 南京芯驰半导体科技有限公司 | Digital pulse width capturing system and method |
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| CN112242842A (en) * | 2019-07-18 | 2021-01-19 | 三星电子株式会社 | Phase Locked Loop (PLL) circuit including sub-sampling circuit and clock generator |
| CN114090361A (en) * | 2022-01-20 | 2022-02-25 | 南京芯驰半导体科技有限公司 | IO signal monitoring circuit and implementation method |
| CN114441860A (en) * | 2022-04-07 | 2022-05-06 | 南京芯驰半导体科技有限公司 | Digital pulse width capturing system and method |
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