CN105245203A - System and method for duty ratio detection employing high precision and low speed clock - Google Patents
System and method for duty ratio detection employing high precision and low speed clock Download PDFInfo
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- CN105245203A CN105245203A CN201510777916.2A CN201510777916A CN105245203A CN 105245203 A CN105245203 A CN 105245203A CN 201510777916 A CN201510777916 A CN 201510777916A CN 105245203 A CN105245203 A CN 105245203A
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Abstract
The present invention relates to a system and method for duty ratio detection employing a high precision and low speed clock. The system for duty ratio detection employing the high precision and low speed clock comprises: a synchronization unit configured to perform synchronous processing of asynchronous input duty ratio signals and output a processing result to a pulse transition unit; the pulse transition unit configured to perform pulse transition of the inputted duty ratio signals; a frequency decision unit configured to divide the inputted duty ratio signals into high-frequency signals and low-frequency signals; a duty ratio sampling unit configured to sample the duty ratio signals according to the inputted duty ratio signals which are the high-frequency signals or the low-frequency signals; a divider configured to obtain and output a duty ratio value; and a clock division unit configured to provide clock signals for the system for duty ratio detection employing the high precision and low speed clock. Through the adoption of the system and method for duty ratio detection employing a high precision and low speed clock, the large-scale frequency input may be accurately and effectively detected by employing the low speed clock, and the signal duty ratio of the target frequency may be accurately outputted, therefore the faults in the prior art, such as low detection precision, small frequency range, high cost and the like, are overcome.
Description
Technical field
The present invention relates to signal controlling field, particularly relate to signal detection technique, specifically refer to a kind of high accuracy low-speed clock duty ratio detection system and method.
Background technology
For the existing driving method of motor, pulse period modulation technique is commonplace method, and it reaches by the duty ratio of change pulse-period signal the object controlling drive motors.In concrete implementation procedure, after often input pulse periodic signal synchronously being processed, directly carry out duty ratio sampling, use low-speed clock to count high level and total pulse width period, utilize two ratio meters counted to calculate the value of duty ratio, as shown in Figure 1, its existing defects is exactly: under low-speed clock, can only sample to signal frequency interior among a small circle, the precision exported after sampling is low, needs to change high-frequency clock into and turn increases cost.
Summary of the invention
The object of the invention is the shortcoming overcoming above-mentioned prior art, provide a kind of accurately more large-scale frequency input of effective detection under low-speed clock, high accuracy low-speed clock duty ratio detection system and the method for the signal dutyfactor of target frequency can be exported simultaneously accurately.
To achieve these goals, high accuracy low-speed clock duty ratio detection system of the present invention and method have following formation:
This high accuracy low-speed clock duty ratio detection system, its main feature is, described system comprises:
Lock unit, in order to synchronously to process the duty cycle signals of asynchronous input, and exports result to pulses switch unit;
Pulses switch unit, in order to carry out pulses switch to the duty cycle signals of input;
Frequency judging unit, in order to be divided into high-frequency signal and low frequency signal by the duty cycle signals of input;
Duty ratio sampling unit, in order to be high-frequency signal or low frequency signal according to the duty cycle signals of input, samples to described duty cycle signals;
Divider, obtains dutyfactor value in order to the sampled result according to described duty ratio sampling unit, and exports;
And clock division unit, provide clock signal in order to give described system.
Further, described pulses switch unit comprises:
Whether the first signal edge detection subelement, exist signal edge in order to the duty cycle signals detecting input;
5th counter, in order to count according to the Output rusults of the first described signal edge detection subelement and clock division unit;
First result exports subelement, in order to export corresponding signal according to the count results of the 5th described counter.
Further, described frequency judging unit comprises:
Secondary signal Edge check subelement, whether the signal exporting the output of subelement in order to detect the first described result exists edge;
First counter, in order to count according to the Output rusults of described secondary signal Edge check subelement and clock division unit;
Second result exports subelement, in order to export corresponding result according to the count results of the first described counter.
Further, described duty ratio sampling unit comprises:
Second counter, the high level in order to the duty cycle signals to input counts, and exports count results to divider;
3rd counter, the total cycle in order to the duty cycle signals to input counts, and exports count results to divider;
Four-counter, in order to count the duty ratio number of samples of high-frequency signal, and exports count results to divider.
The invention still further relates to a kind of high accuracy low-speed clock duty ratio detection method, its main feature is, described method comprises the following steps:
(1) duty cycle signals of the lock unit described in asynchronous input synchronously processes, and exports result to pulses switch unit;
(2) duty cycle signals of the pulses switch unit described in input carries out pulses switch;
(3) duty cycle signals of input is divided into high-frequency signal and low frequency signal by the frequency judging unit described in;
(4) the duty ratio sampling unit described in is high-frequency signal or low frequency signal according to the duty cycle signals of input, samples to described duty cycle signals;
(5) divider described in obtains dutyfactor value according to the sampled result of described duty ratio sampling unit, and exports.
Further, described pulses switch unit comprises the first signal edge detection subelement, the 5th counter and the first result and exports subelement; Described step (2) specifically comprises the following steps:
(2.1) whether the duty cycle signals that the first signal edge detection subelement described in detects input exists signal edge;
(2.2) if the duty cycle signals of described input exists edge, then by the 5th described counter O reset;
(2.3) if the duty cycle signals of described input does not exist edge, then the count value of the 5th described counter adds 1, and the clock signal of the 5th wherein said counter is the 1ms pulse enable signal that described clock division unit exports;
(2.4) after the first described signal edge detection subelement has detected the duty cycle signals of input, whether the count value of the 5th counter that the first described result exports described in subelement judgement equals the first preset value;
(2.5) if the count value of the 5th described counter equals the first preset value, then the pulse signal of 16ms is exported;
(2.6) if the count value of the 5th described counter is not equal to the first preset value, then the duty cycle signals of the input described in exporting.
Further, described frequency judging unit comprises secondary signal Edge check subelement, the first counter and the second result and exports subelement; Described step (3) is specially:
(3.1) whether the signal that the first result described in the secondary signal Edge check subelement described in detects exports the output of subelement exists edge;
(3.2) if the signal that the first described result exports the output of subelement exists edge, then the first described counter O reset;
(3.3) if the signal that the first described result exports the output of subelement does not exist edge, the count value of the first then described counter adds 1, and the clock signal of the first wherein said counter is the 33us pulse enable signal that described clock division unit exports;
(3.4), detected the signal of output of the first described result output subelement at described secondary signal Edge check subelement after, whether the count value of the first counter that the second described result exports described in subelement judgement has been greater than the second preset value;
(3.5) if the count value of the first described counter is greater than the second preset value, then output low frequency enable signal is to described duty ratio sampling unit;
(3.6) if the count value of the first described counter is not more than the second preset value, then high frequency enable signal is exported to described duty ratio sampling unit.
Again further, described step (4) specifically comprises the following steps:
(4.1) Output rusults that the second result described in the duty ratio sampling unit described in judges exports subelement is high frequency enable signal or low frequency enable signal;
(4.2) if the Output rusults that the second described result exports subelement is high frequency enable signal, then described the second counter, the 3rd counter and four-counter count described high-frequency signal;
(4.3) if the Output rusults that the second described result exports subelement is low frequency enable signal, then the second described counter, the 3rd counter count described low frequency signal.
Again further, described step (4.2) specifically comprises the following steps:
(4.2.1) duty cycle signals of the input described in the duty ratio sampling unit described in judges is as high level signal, low level signal or edge signal;
If the duty cycle signals of (4.2.2) described input is high level signal, then the count value of the second described counter adds 1, and the count value of the 3rd described counter adds 1;
If the duty cycle signals of (4.2.3) described input is low level signal, then the count value of the 3rd described counter adds 1;
If the duty cycle signals of (4.2.4) described input is rising edge signal, then the count value of described four-counter adds 1;
(4.2.5) whether the count value of the four-counter described in the duty ratio detecting unit described in judges equals the 3rd preset value;
If the count value of (4.2.6) described four-counter equals the 3rd preset value, then described the second counter, the 3rd counter and four-counter all reset, and the ratio of the output value of the second counter and the value of the 3rd described counter is to divider;
If the count value of (4.2.7) described four-counter is not equal to the 3rd preset value, then described the second counter, the 3rd counter and four-counter all add 1, then continue step (4.2.1).
Again further, described step (4.3) specifically comprises the following steps:
(4.3.1) duty cycle signals of the input described in the duty ratio sampling unit described in judges is as high level signal, low level signal or edge signal;
If the duty cycle signals of (4.3.2) described input is high level signal, then the second described counter and the count value of the 3rd described counter all add 1;
If the duty cycle signals of (4.3.3) described input is low level signal, then the count value of the 3rd described counter adds 1;
If the duty cycle signals of (4.3.4) described input is trailing edge signal, then the count value of the 3rd described counter is assigned to the second described counter;
If the duty cycle signals of (4.3.5) described input is rising edge signal, then the second described counter and the second counter are all reset, and the ratio of the output value of the second counter and the value of the 3rd described counter is to divider.
Have employed the high accuracy low-speed clock duty ratio detection system in this invention and method, on the basis of original detection method, add two special elements, pulses switch unit and frequency judging unit, make the present invention accurately effectively under low-speed clock can detect the input of more large-scale frequency, the signal dutyfactor of target frequency can be exported accurately simultaneously, can overcome in prior art that accuracy of detection is low, frequency range is narrow and high in cost of production defect.
Accompanying drawing explanation
Fig. 1 is pulse-period signal duty ratio detection method structure chart in prior art.
Fig. 2 is the structured flowchart of the pulse-period signal duty ratio detection method of the embodiment of the present invention.
Fig. 3 is the flow chart of the pulse-period signal duty ratio detection method of the embodiment of the present invention.
Fig. 4 is the pulse-period signal duty ratio lock unit schematic diagram of the embodiment of the present invention.
Fig. 5 is the flow chart of the pulse-period signal duty cycle pulse conversion method of the embodiment of the present invention.
Fig. 6 is the flow chart of the pulse-period signal duty ratio frequency interpretation method of the embodiment of the present invention.
Fig. 7 is the pulse-period signal duty ratio method of sampling flow chart of the embodiment of the present invention.
Embodiment
In order to more clearly describe technology contents of the present invention, conduct further description below in conjunction with specific embodiment.
Detect about signal dutyfactor during embodiments of the present invention, the signal dutyfactor particularly under low-speed clock detects; Below in conjunction with the accompanying drawing in the embodiment of the present invention, carry out clear, complete description to the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to scope.
In order to more concrete description discloses the feature of execution mode, incorporated by reference to describing in detail with reference to figure 2 ~ Fig. 7 once.
Detection method as shown in Figure 2, on the basis of original detection method, add two special elements, pulses switch unit and frequency judging unit, make the present invention accurately effectively under low-speed clock can detect the input of more large-scale frequency, the signal dutyfactor of target frequency can be exported accurately simultaneously, can overcome in prior art that accuracy of detection is low, frequency range is narrow and high in cost of production defect.
Figure 2 shows that pulse-period signal duty ratio detection architecture block diagram, it includes synchronous logic unit, pulses switch unit, frequency judging unit, signal dutyfactor sampling unit and divider; The signal dutyfactor that the present invention is particularly conducive under low-speed clock is accurately sampled, and the system clock of illustrating in such as embodiment is 4M low-speed clock, and the frequency band for sampled input signal is 0 ~ 100KHz.
Figure 3 shows that the flow chart of pulse-period signal duty ratio detection method of the present invention, synchronous process done to input signal duty ratio, at its rising edge of pulses switch unit inspection and trailing edge, have edge transition just to keep former synchronizing signal to export; Do not have edge transition, expression is input as permanent high or permanent low; That is, according to system clock, within a period of time, input signal be permanent high or for permanent low when, the output that a clock pulse signal replaces permanent height and permanent low signal can be produced.Such as under 4M low-speed clock, within the 16ms time, input signal is high level always or is low level always, just produces a pulse signal as output.The signal of frequency judging unit received pulse converting unit exports, and carries out cycle count, when counter T1 is greater than a certain value, judge that input signal is as low frequency signal to signal; During a certain values such as T1 is less than, judge that input signal is as high-frequency signal; Such as signal is carried out to the cycle count of 1ms, by the rolling counters forward of 4, when Counter Value is greater than 7, judge that input signal is low frequency signal, when Counter Value is less than or equal to 7, judge that input signal is high-frequency signal.Result of determination exports to signal dutyfactor sampling unit together with signal.Signal dutyfactor sampling unit counts the high level of signal and total cycle, and low-frequency signals enables counter T2 sum counter T3, and high-frequency signal enables counter T2 sum counter T3, records the sampling number of high-frequency signal and low frequency signal with counter T4.The sampling period number of times that such as can arrange low frequency signal is 1 time, and the sampling period number of times of high-frequency signal can be set to 128 times.The output of signal dutyfactor sampling unit does computing in divider, obtains final signal duty ratio and exports.
Figure 4 shows that the signal three grades synchronously process of signal dutyfactor detection method of the present invention, be made up of 3 d type flip flops, effectively can reduce metastable state, export synchronizing signal Data_d3;
Figure 5 shows that the pulses switch unit of signal dutyfactor detection method of the present invention, comprise a counter T5,4 digit counters such as, arranged in embodiment, first carry out Edge check to input signal duty ratio, signal edge detected, and counter T5 resets; Signal edge do not detected, counter T5 carries out cycle count to signal, is such as cycle count with 1ms; According to counter T5, when T5 is not equal to certain value, such as this value is 16, output signal Data_d3; As T5=16, export a clock pulse and export as signal; This function is convenient to the carrying out of height frequency sampling, reduces the generation of error detection event and improves ensuing sampling precision, specifically can illustrate in the description of Fig. 6.
Figure 6 shows that the frequency judging unit of signal dutyfactor detection method of the present invention, the output signal of this unit received pulse converting unit, Edge check is done to signal, counter T1 is utilized to carry out cycle count to signal, it is such as the cycle with 33us, calculate the duration of signal, when signal rising edge being detected, counter T1 resets New count of laying equal stress on; Arrange frequency separation, such as a 5K, what frequency was more than or equal to 5K is referred to as high band, and what frequency was less than 5K is referred to as low-frequency range.For counter T1, such as 4 digit counters, when T1 is less than or equal to 7, input signal is high band, and when T1 is greater than 7, input signal is low-frequency range.But such as when input signal is the high-frequency signal of 100% duty ratio, do not have edge transition, counter T1 counting can be greater than 7, can be considered to low frequency signal; And when the height point in the signal dutyfactor inputted is flat or low-level pulse width is less than 250ns, such as 100KHZ frequency duty ratio is 99% signal, its low-level pulse width is 100ns, 4M low-speed clock is sampled, the input signal of 99% duty ratio has the situation of the low level signal adopted less than it, export change 100%, permanent high; When low level is sampled then, output becomes 97.5%, there will be edge transition, export meeting in both saltus steps, and when now frequency judging unit receives the input of this type of signal, enable and the enable meeting of the low frequency saltus step back and forth of high frequency, be unfavorable for ensuing sampling element, in like manner for 100KHZ frequency duty ratio be the sampling situations of 1% signal too, so the present invention devises this link of pulses switch unit to eliminate the problems referred to above, distinguish height frequency band more accurately, be convenient to sampling.
Figure 7 shows that the signal dutyfactor sampling unit of signal dutyfactor detection method of the present invention, comprise the enable input of height frequency, Edge check, three counter T2, T3, T4.When low frequency signal is enable, be switched to low-frequency sampling method, signal is sampled, such as only samples during low-frequency sampling method a signal period, when signal high level, counter T3 counts, when signal trailing edge being detected, the value of T3 is assigned to T2, T3 continues counting, when signal rising edge being detected, the value of counter T3 sum counter T2 latches and exports and reset; When high-frequency signal is enable, be switched to the high frequency method of sampling, signal is sampled, such as distinguish and sample with low frequency signal, high-frequency signal can be set and sample 128 signal periods, during signal high level, counter T2 sum counter T3 counts+1, when signal trailing edge being detected, T2 counter keeps, and T3 continues counting+1; When signal rising edge being detected, during counter T4<128, counter T2 sum counter T3 continues counting+1, counter T4+1; As T4=128, the value of counter T2 sum counter T3 latches and exports and reset; The output of this unit is done division arithmetic and is outputed signal the value of duty ratio in divider.
Have employed the high accuracy low-speed clock duty ratio detection system in this invention and method, on the basis of original detection method, add two special elements, pulses switch unit and frequency judging unit, make the present invention accurately effectively under low-speed clock can detect the input of more large-scale frequency, the signal dutyfactor of target frequency can be exported accurately simultaneously, can overcome in prior art that accuracy of detection is low, frequency range is narrow and high in cost of production defect.
In this description, the present invention is described with reference to its specific embodiment.But, still can make various amendment and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (10)
1. a high accuracy low-speed clock duty ratio detection system, is characterized in that, described system comprises:
Lock unit, in order to synchronously to process the duty cycle signals of asynchronous input, and exports result to pulses switch unit;
Pulses switch unit, in order to carry out pulses switch to the duty cycle signals of input;
Frequency judging unit, in order to be divided into high-frequency signal and low frequency signal by the duty cycle signals of input;
Duty ratio sampling unit, in order to be high-frequency signal or low frequency signal according to the duty cycle signals of input, samples to described duty cycle signals;
Divider, obtains dutyfactor value in order to the sampled result according to described duty ratio sampling unit, and exports;
And clock division unit, provide clock signal in order to give described system.
2. high accuracy low-speed clock duty ratio detection system according to claim 1, it is characterized in that, described pulses switch unit comprises:
Whether the first signal edge detection subelement, exist signal edge in order to the duty cycle signals detecting input;
5th counter, in order to count according to the Output rusults of the first described signal edge detection subelement and clock division unit;
First result exports subelement, in order to export corresponding signal according to the count results of the 5th described counter.
3. high accuracy low-speed clock duty ratio detection system according to claim 2, it is characterized in that, described frequency judging unit comprises:
Secondary signal Edge check subelement, whether the signal exporting the output of subelement in order to detect the first described result exists edge;
First counter, in order to count according to the Output rusults of described secondary signal Edge check subelement and clock division unit;
Second result exports subelement, in order to export corresponding result according to the count results of the first described counter.
4. high accuracy low-speed clock duty ratio detection system according to claim 1, it is characterized in that, described duty ratio sampling unit comprises:
Second counter, the high level in order to the duty cycle signals to input counts, and exports count results to divider;
3rd counter, the total cycle in order to the duty cycle signals to input counts, and exports count results to divider;
Four-counter, in order to count the duty ratio number of samples of high-frequency signal, and exports count results to divider.
5., based on a high accuracy low-speed clock duty ratio detection method for the system described in any one of Claims 1-4, it is characterized in that, described method comprises the following steps:
(1) duty cycle signals of the lock unit described in asynchronous input synchronously processes, and exports result to pulses switch unit;
(2) duty cycle signals of the pulses switch unit described in input carries out pulses switch;
(3) duty cycle signals of input is divided into high-frequency signal and low frequency signal by the frequency judging unit described in;
(4) the duty ratio sampling unit described in is high-frequency signal or low frequency signal according to the duty cycle signals of input, samples to described duty cycle signals;
(5) divider described in obtains dutyfactor value according to the sampled result of described duty ratio sampling unit, and exports.
6. high accuracy low-speed clock duty ratio detection method according to claim 5, is characterized in that, described pulses switch unit comprises the first signal edge detection subelement, the 5th counter and the first result and exports subelement; Described step (2) specifically comprises the following steps:
(2.1) whether the duty cycle signals that the first signal edge detection subelement described in detects input exists signal edge;
(2.2) if the duty cycle signals of described input exists edge, then by the 5th described counter O reset;
(2.3) if the duty cycle signals of described input does not exist edge, then the count value of the 5th described counter adds 1, and the clock signal of the 5th wherein said counter is the 1ms pulse enable signal that described clock division unit exports;
(2.4) after the first described signal edge detection subelement has detected the duty cycle signals of input, whether the count value of the 5th counter that the first described result exports described in subelement judgement equals the first preset value;
(2.5) if the count value of the 5th described counter equals the first preset value, then the pulse signal of 16ms is exported;
(2.6) if the count value of the 5th described counter is not equal to the first preset value, then the duty cycle signals of the input described in exporting.
7. high accuracy low-speed clock duty ratio detection method according to claim 6, is characterized in that, described frequency judging unit comprises secondary signal Edge check subelement, the first counter and the second result and exports subelement; Described step (3) is specially:
(3.1) whether the signal that the first result described in the secondary signal Edge check subelement described in detects exports the output of subelement exists edge;
(3.2) if the signal that the first described result exports the output of subelement exists edge, then the first described counter O reset;
(3.3) if the signal that the first described result exports the output of subelement does not exist edge, the count value of the first then described counter adds 1, and the clock signal of the first wherein said counter is the 33us pulse enable signal that described clock division unit exports;
(3.4), detected the signal of output of the first described result output subelement at described secondary signal Edge check subelement after, whether the count value of the first counter that the second described result exports described in subelement judgement has been greater than the second preset value;
(3.5) if the count value of the first described counter is greater than the second preset value, then output low frequency enable signal is to described duty ratio sampling unit;
(3.6) if the count value of the first described counter is not more than the second preset value, then high frequency enable signal is exported to described duty ratio sampling unit.
8. high accuracy low-speed clock duty ratio detection method according to claim 7, is characterized in that, described step (4) specifically comprises the following steps:
(4.1) Output rusults that the second result described in the duty ratio sampling unit described in judges exports subelement is high frequency enable signal or low frequency enable signal;
(4.2) if the Output rusults that the second described result exports subelement is high frequency enable signal, then described the second counter, the 3rd counter and four-counter count described high-frequency signal;
(4.3) if the Output rusults that the second described result exports subelement is low frequency enable signal, then the second described counter, the 3rd counter count described low frequency signal.
9. high accuracy low-speed clock duty ratio detection method according to claim 8, is characterized in that, described step (4.2) specifically comprises the following steps:
(4.2.1) duty cycle signals of the input described in the duty ratio sampling unit described in judges is as high level signal, low level signal or edge signal;
If the duty cycle signals of (4.2.2) described input is high level signal, then the count value of the second described counter adds 1, and the count value of the 3rd described counter adds 1;
If the duty cycle signals of (4.2.3) described input is low level signal, then the count value of the 3rd described counter adds 1;
If the duty cycle signals of (4.2.4) described input is rising edge signal, then the count value of described four-counter adds 1;
(4.2.5) whether the count value of the four-counter described in the duty ratio detecting unit described in judges equals the 3rd preset value;
If the count value of (4.2.6) described four-counter equals the 3rd preset value, then described the second counter, the 3rd counter and four-counter all reset, and the ratio of the output value of the second counter and the value of the 3rd described counter is to divider;
If the count value of (4.2.7) described four-counter is not equal to the 3rd preset value, then described the second counter, the 3rd counter and four-counter all add 1, then continue step (4.2.1).
10. high accuracy low-speed clock duty ratio detection method according to claim 8, is characterized in that, described step (4.3) specifically comprises the following steps:
(4.3.1) duty cycle signals of the input described in the duty ratio sampling unit described in judges is as high level signal, low level signal or edge signal;
If the duty cycle signals of (4.3.2) described input is high level signal, then the second described counter and the count value of the 3rd described counter all add 1;
If the duty cycle signals of (4.3.3) described input is low level signal, then the count value of the 3rd described counter adds 1;
If the duty cycle signals of (4.3.4) described input is trailing edge signal, then the count value of the 3rd described counter is assigned to the second described counter;
If the duty cycle signals of (4.3.5) described input is rising edge signal, then the second described counter and the second counter are all reset, and the ratio of the output value of the second counter and the value of the 3rd described counter is to divider.
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| CN110798050A (en) * | 2019-10-31 | 2020-02-14 | 儒竞艾默生环境优化技术（上海）有限公司 | Duty ratio design method, system, medium and device for eliminating current sampling interference |
| CN111342851A (en) * | 2018-11-30 | 2020-06-26 | 宁波方太厨具有限公司 | High-accuracy receiving method of radio frequency signal |
| CN112084464A (en) * | 2020-09-11 | 2020-12-15 | 中国科学院微小卫星创新研究院 | Satellite electric heater duty ratio statistical method and system |
| CN113300692A (en) * | 2021-05-08 | 2021-08-24 | 黑芝麻智能科技(上海)有限公司 | System and method for monitoring clock duty cycle |
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| US7642829B2 (en) * | 2005-02-03 | 2010-01-05 | Elpida Memory, Inc. | Duty detection circuit |
| US20080290920A1 (en) * | 2007-05-24 | 2008-11-27 | Nanya Technology Corporation | Duty cycle correction circuit and method thereof |
| CN102055443A (en) * | 2009-10-30 | 2011-05-11 | 无锡海威半导体科技有限公司 | Duty cycle detection circuit |
| CN103731151A (en) * | 2014-01-15 | 2014-04-16 | 南京矽力杰半导体技术有限公司 | Method and circuit for converting duty ratio into analog signal |
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| CN113300692A (en) * | 2021-05-08 | 2021-08-24 | 黑芝麻智能科技(上海)有限公司 | System and method for monitoring clock duty cycle |
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