CN100516898C - High precision clock detecting method and testing apparatus - Google Patents
High precision clock detecting method and testing apparatus Download PDFInfo
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- CN100516898C CN100516898C CNB2007101277045A CN200710127704A CN100516898C CN 100516898 C CN100516898 C CN 100516898C CN B2007101277045 A CNB2007101277045 A CN B2007101277045A CN 200710127704 A CN200710127704 A CN 200710127704A CN 100516898 C CN100516898 C CN 100516898C
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Abstract
The present invention relates to a high-precision clock detecting method and a detecting device. The method firstly measures an accumulated phase position error of a reference clock and a tested clock and a generation period of the accumulated error and then compares the generation period of the accumulated error with preset threshold precision value. As the generation period of the accumulated error is inferior to the threshold value, the method detects errors of the tested clock, thus confirming frequency precision of the tested clock. The high-precision clock detecting method and the detecting device of the present invention can measure slight frequency difference between the tested clock and the reference clock. As the frequency difference exceeds a specified scope, the present invention promptly discovers the nonconformance and outputs a signal, thus greatly improving precision and sensitivity compared with prior clock detecting methods. Moreover, the high-precision clock detecting method and the detecting device of the present invention not only adapts to synchronous source data transmission but also is widely applied to other fields needing high-precision clock detection.
Description
Technical field
The present invention relates to mechanics of communication, particularly a kind of high-precision clock detecting method and pick-up unit.
Background technology
In the communications field, relate to the data synchronization transmission through regular meeting.When the data synchronous transmission is particularly adopted source synchronous data transfer, the speed that many application scenarios all need to import data and the local clock of handling these data in long time window fully synchronously, data need two clocks synchronous fully when transmission, and asynchronous meeting produces error code.Though the generation of error code also has other reason, measure these two clocks and whether can determine or get rid of the problem that causes error code by clock fully synchronously.
Source-synchronous data is when data transmission, and data adopt identical path to transmit with transfer clock.When the clock of the clock of data source or local reception data and standard clock source losing lock, will produce the difference on the frequency of clock.This difference on the frequency is very small usually, and common detection method can not detect.Detection method to measured clock in the prior art mainly is to adopt in a period of time tested clock to be counted, utilize count value to calculate the frequency error of measured clock, this method accuracy of detection improves need be than the counter of multidigit, for requiring synchronous clock detection fully, both make the increase counter, can not satisfy the requirement of detection.
The present invention is directed to the demand,, can effectively detect the precision of input clock, be applicable to that also a lot of other needs the situation of high Precision Detection clock in the communications field by a series of processing to clock.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of detection method and pick-up unit of high precision clock is provided.Utilize the detection method of high precision clock of the present invention can effectively detect the input clock precision, when accuracy of detection improves, do not need to increase a lot of counters,, realize simplifying more for requiring synchronous clock detection fully.
Ultimate principle of the present invention:
By the accumulated phase error of measuring basis clock and measured clock and the generation cycle of this cumulative errors, the generation cycle of this cumulative errors is compared with predefined precision threshold, when the generation cycle of cumulative errors is not satisfied this threshold value, detect measured clock and make mistakes, and then determine the frequency accuracy of measured clock thus.
Technical scheme of the present invention:
A kind of high-precision clock detecting method, this method comprises the steps:
1. utilize frequency divider to carry out frequency division to measured clock with as the reference clock of standard respectively, make behind the frequency division frequency of reference clock and measured clock identical;
2. measured clock and reference clock after utilizing two accumulation of phase devices in the accumulation of phase unit to frequency division carry out accumulation of phase respectively;
3. utilize the relatively state of two accumulation of phase devices of matching unit, check whether mismatch of two accumulation of phase devices, initialization accumulation of phase device during mismatch, and carry out accumulation of phase again;
4. in the time interval of utilizing counter unit to calculate twice mismatch, promptly obtain generation cycle of cumulative errors;
5. utilize wrong output unit to compare the generation cycle of cumulative errors and the size of predetermined threshold value, be less than or equal to predetermined threshold value, by the mistake indication of wrong output unit output measured clock when the cumulative errors generation cycle.
The 1. middle employing first Clock dividers crossover frequency of step is f
0Reference clock, second clock frequency divider crossover frequency is f
xMeasured clock, wherein the frequency dividing ratio of first Clock dividers is m, the frequency dividing ratio of second clock frequency divider is n, satisfies:
f
x/n＝f
0/m。
The step 2. step of middle accumulation of phase is:
A. two accumulation of phase devices that adopted in definite accumulation of phase unit;
B. set the initial value of the accumulation of phase device that adopts;
C. utilize the clock behind the frequency division to drive two accumulation of phase devices respectively, two accumulation of phase devices carry out accumulation of phase respectively when clock is effective.
Step determines that the step of two phase place collecting apparatus phase mismatch is in 3.:
A. the reference clock behind the frequency division is identical with the measured clock frequency, two accumulation of phase devices and or difference for definite value;
B. default value scope in the matching unit, and with these two accumulation of phase devices and or difference compare with preset range, as if within the preset range, proceed accumulation, if surpass preset range, two accumulation of phase devices in then zero clearing counter unit, and the initialization accumulation of phase unit.
Step in 5. threshold value N, the scope p of matching unit and three numerical value of frequency dividing ratio n of second clock frequency divider satisfy formula:
N＝p*n/S
Wherein, S is the clock accuracy constant that presets.As 1ppm, the trueness error of its expression clock is 1,000,000/.
The method of step wrong output unit output measured clock mistake indication in 5. is:
A. when matching unit output clock mismatch, relatively the generation periodic quantity and the predetermined threshold value of the cumulative errors counted of counter unit, the indication of output measured clock mistake when the generation periodic quantity of cumulative errors is less than or equal to predetermined threshold value; Perhaps b. relatively the generation periodic quantity and the predetermined threshold value of the cumulative errors counted of counter unit in real time, the indication of output measured clock mistake when the generation periodic quantity of cumulative errors is less than or equal to predetermined threshold value.
A kind of high precision clock pick-up unit, this device comprises first Clock dividers, the second clock frequency divider, the first accumulation of phase device, the second accumulation of phase device, matching unit, counter unit and wrong output unit, one standard time clock inputs in the first accumulation of phase device after by the first Clock dividers frequency division, drive the operation of the first accumulation of phase device by this first Clock dividers output signal, one measured clock inputs in the second accumulation of phase device after by second clock frequency divider frequency division, drive the operation of the second accumulation of phase device by this second clock output signal of frequency divider, the described first accumulation of phase device and the second accumulation of phase device are formed an accumulation of phase unit, the data output end of the described first accumulation of phase device and the second accumulation of phase device is connected to the data input pin of described matching unit, subtracter in matching unit and comparer, output terminal is connected in the data input pin of described counter unit, another data output end of described matching unit is connected in the initialization input of accumulation of phase unit, described counter unit drives operation by reference clock, described counter unit input data are calculated the indicator signal of back output measured clock mistake to wrong output unit by the comparer in this mistake output unit.
Described accumulation of phase device is counter or is circular shift register.
The edge or the level of the reference clock of the described first accumulation of phase device after by frequency division drive operation, and the described second accumulation of phase device is to be driven by the edge of measured clock behind the frequency division or level.
The initialization value of described circular shift register is non-full zero and non-complete 1.
Technological merit of the present invention:
High-precision clock detecting method of the present invention and pick-up unit, be to compare after the phase differential accumulation with measured clock and reference clock, can record the small difference on the frequency between measured clock and the reference clock, when surpassing certain limit, this difference on the frequency can find in time and output signal that so more in the past clock detection method precision and sensitivity aspect are improved largely.High-precision clock detecting method of the present invention and pick-up unit not only can be applied to the source data synchronous transmission, can also be widely used in the field that other needs the high Precision Detection clock.
Description of drawings
Fig. 1 is the clock detection process flow diagram of a kind of high-precision clock detecting method of the present invention and pick-up unit.
Fig. 2 is embodiment 1 structural representation of a kind of high-precision clock detecting method of the present invention and pick-up unit.
Fig. 3 is the structural representation of embodiment 1 interior matching unit in a kind of high-precision clock detecting method of the present invention and the pick-up unit.
Among the figure,
The 101-first Clock dividers 102-second clock frequency divider
The 103-first counter 104-second counter
105-matching unit 106-counter unit 107-mistake output unit
301-subtracter 302-comparer
Embodiment
Come a kind of high-precision clock detecting method of the present invention and pick-up unit are described in further detail below in conjunction with Figure of description and specific embodiment, but should therefore not limit protection scope of the present invention.
Please see Figure 1, Fig. 1 is the clock detection process flow diagram of a kind of high-precision clock detecting method of the present invention and pick-up unit.As seen from the figure, a kind of high-precision clock detecting method, this method comprises the steps:
1. utilize frequency divider to carry out frequency division to measured clock with as the reference clock of standard respectively, make behind the frequency division frequency of reference clock and measured clock identical; By the first Clock dividers crossover frequency is f
0Reference clock, second clock frequency divider crossover frequency is f
xMeasured clock, wherein the frequency dividing ratio of first Clock dividers is m, the frequency dividing ratio of second clock frequency divider is n, satisfies:
f
x/n＝f
0/m。
2. measured clock and reference clock after utilizing two accumulation of phase devices in the accumulation of phase unit to frequency division carry out accumulation of phase respectively, and the step of accumulation of phase is:
A. two accumulation of phase devices that adopted in definite accumulation of phase unit;
B. set the initial value of the accumulation of phase device that adopts;
C. utilize reference clock and measured clock behind the frequency division respectively to drive an accumulation of phase device operation, two accumulation of phase devices carry out accumulation of phase respectively when clock is effective.
3. utilize the relatively state of two accumulation of phase devices of matching unit, check whether phase mismatch of two accumulation of phase devices, initialization accumulation of phase device and carry out accumulation of phase again during mismatch, determine that the step of two phase place collecting apparatus phase mismatch is:
A. the reference clock behind the frequency division is identical with the measured clock frequency, two accumulation of phase devices and or difference for definite value;
B. default value scope in the matching unit, and with these two accumulation of phase devices and or difference compare with preset range, as if within the preset range, proceed accumulation, if surpass preset range, two accumulation of phase devices in then zero clearing counter unit, and the initialization accumulation of phase unit.
4. in the time interval of utilizing counter unit to calculate twice mismatch, promptly obtain generation cycle of cumulative errors;
5. utilize wrong output unit to compare the generation periodic quantity of cumulative errors and the size of predetermined threshold value, when the cumulative errors generation cycle is less than or equal to predetermined threshold value, by the mistake indication of wrong output unit output measured clock, the method for mistake output unit output measured clock mistake indication is:
A. when matching unit output clock mismatch, relatively the generation periodic quantity and the predetermined threshold value of the cumulative errors counted of counter unit, the indication of output measured clock mistake when the generation periodic quantity of cumulative errors is less than or equal to predetermined threshold value; Perhaps b. relatively the generation periodic quantity and the predetermined threshold value of the cumulative errors counted of counter unit in real time, the indication of output measured clock mistake when the generation periodic quantity of cumulative errors is less than or equal to predetermined threshold value.
Please see Figure 2, Fig. 3, Fig. 2 is the structural representation of a kind of high-precision clock detecting method of the present invention and pick-up unit one embodiment.Fig. 3 is the structural representation of embodiment 1 interior matching unit in a kind of high-precision clock detecting method of the present invention and the pick-up unit.As seen from the figure, a kind of pick-up unit of high precision clock, this device comprises first Clock dividers 101, second clock frequency divider 102, the accumulation of phase unit of forming by first counter 103 and second counter 104, matching unit 105, counter unit 106 and wrong output unit 107, one standard time clock inputs in first counter 103 after by first Clock dividers, 101 frequency divisions, drive 103 operations of first counter by these first Clock dividers, 101 clock signals, one measured clock inputs in second counter 104 after by second clock frequency divider 102 frequency divisions, drive 104 operations of second counter by these second clock frequency divider 102 clock signals, described first counter 103 and second counter 104 are formed an accumulation of phase unit, the data output end of described first counter 103 and second counter 104 is connected to the data input pin of described matching unit 105, this matching unit 105 is made up of subtracter 301 and comparer 302, first counter 103 and the second counter 104 input institute signal that accumulates are to subtracter 301 interior computings, operation result inputs in the comparer 302 and compares with preset range, a data output terminal of this matching unit 105 is connected in the data input pin of described counter unit 106, another data output end of described matching unit 105 is connected in the initialization input of accumulation of phase unit, described counter unit 106 drives operation by reference clock, described counter unit 106 input data occur mistake by these mistake output unit 107 output indicator signals to show measured clock to wrong output unit 107.
Described first counter 103 drives operation by the level of the reference clock behind the frequency division, described second counter 104 is the level driving operations by measured clock behind the frequency division, first counter 103 and second counter 104 use one 3 digit counter respectively, when a clock is effective, first counter 103 and second counter 104 add 1, carrying out stored counts with this, is one 25 counter in the described counter unit 106.
In particular cases,, then can need not Clock dividers measured clock and reference clock are carried out frequency division, can directly drive the accumulation of phase device by measured clock and reference clock if the frequency of measured clock equals the frequency of reference clock; When if the frequency of measured clock is the integral multiple of reference clock, or reference clock is when being the integral multiple of measured clock, can be only carry out frequency division to the clock of big frequency with a Clock dividers.
High precision clock pick-up unit workflow in the present embodiment is:
The frequency of reference clock is f
0=30MHz, the frequency of measured clock is f
x=20MHz, the frequency dividing ratio m=3 of first Clock dividers 101, the frequency dividing ratio n=2 of second clock frequency divider 102, the relation between each numerical value satisfies formula:
f
x/n＝f
0/m＝10MHz。
That is, reference clock behind the frequency division and measured clock frequency equate, are 10MHz.
Reference clock behind first Clock dividers, 101 frequency divisions utilizes the level of this clock to drive the operation of first counter 103, whenever adds 1 through this first counter 103 of an effective clock; Measured clock behind second clock frequency divider 102 frequency divisions drives 104 operations of second counter with its level, every through an effective clock, this second counter 104 adds 1, first counter 103 and second counter 104 use one 3 counter respectively, the initial value of first counter of setting in the accumulation of phase unit 103 is 0, the initial value of second counter of setting 104 is 0, when reference clock behind frequency division and the measured clock frequency behind the frequency division equate, the phase differential of first counter 103 and second counter 104 is a definite value 0, if the measured clock frequency has deviation, this deviation can accumulate the error that phase place occurs, and error amount is with the increase gradually of accumulation of phase.
Level actuation counter unit 106 operations by reference clock, the time interval that this counter unit 106 calculates twice accumulation of phase unit phase mismatch, and count the numerical values recited in this time interval, obtain cumulative errors and generate the cycle, data zero clearing when counter unit 106 receives the mismatch signal of matching unit 105 output reaches the maximal value 2 of 25 digit counter numerical value when counter unit 106
25During-1=16777215, keep this maximum count value.
Counter unit 106 output cumulative errorss generate the data in cycle to wrong output unit 107, when matching unit 105 output mistermination signals, relatively the cumulative errors that obtains in the counter unit 106 generates the size of predetermined threshold value N in periodic quantity and this mistake output unit 107, and three numerical value of the frequency dividing ratio n of threshold value N wherein, the scope p of matching unit and second clock frequency divider satisfy formula:
N＝p*n/S＝4＊3/1ppm＝12000000
The clock accuracy of setting is 1ppm, the expression clocking error is 1,000,000/.
When cumulative errors generated periodic quantity greater than predetermined threshold value N, the precision of measured clock met the demands, when cumulative errors generation periodic quantity is less than or equal to predetermined threshold value N, and the signal indication of mistake output unit 107 output errors.
Two counters of the accumulation of phase unit in the high precision clock pick-up unit of the present invention can be substituted by circular shift register, workflow and counter are basic identical during as the accumulation of phase device, but want the initial value non-full zero and non-complete of two circular shift register.
The method that a kind of high precision clock disclosed by the invention detects.The invention has the advantages that the frequency difference that can detect trace, can preestablish accuracy of detection, implementation method is simple.
Undoubtedly, a kind of high-precision clock detecting method of the present invention and pick-up unit can also have other numerical value value and structure to substitute, and not only are confined to numerical value cited among the embodiment and structure.Generally speaking, the protection domain of a kind of high-precision clock detecting method of the present invention and pick-up unit also comprises other conversion that it will be apparent to those skilled in the art that and substitutes.
Claims (10)
1. a high-precision clock detecting method is characterized in that this method comprises the steps:
1. utilize frequency divider to carry out frequency division to measured clock with as the reference clock of standard respectively, make behind the frequency division frequency of reference clock and measured clock identical;
2. measured clock and reference clock after utilizing two accumulation of phase devices in the accumulation of phase unit to frequency division carry out accumulation of phase respectively;
3. utilize the relatively state of two accumulation of phase devices of matching unit, check whether mismatch of two accumulation of phase devices, initialization accumulation of phase device during mismatch, and carry out accumulation of phase again;
4. in the time interval of utilizing counter unit to calculate twice mismatch, promptly obtain generation cycle of cumulative errors;
5. utilize wrong output unit to compare the generation cycle of cumulative errors and the size of predetermined threshold value, be less than or equal to predetermined threshold value, by the indication of wrong output unit output measured clock mistake when the cumulative errors generation cycle.
2. high-precision clock detecting method according to claim 1 is characterized in that the 1. middle employing first Clock dividers crossover frequency of described step is f
0Reference clock, second clock frequency divider crossover frequency is f
xMeasured clock, wherein the frequency dividing ratio of first Clock dividers is m, the frequency dividing ratio of second clock frequency divider is n, satisfies:
f
x/n＝f
0/m。
3. high-precision clock detecting method according to claim 1 is characterized in that the step of accumulation of phase was during described step was 2.:
A. two accumulation of phase devices that adopted in definite accumulation of phase unit;
B. set the initial value of the accumulation of phase device that adopts;
C. utilize the clock behind the frequency division to drive two accumulation of phase devices respectively, two accumulation of phase devices carry out accumulation of phase respectively when clock is effective.
4. high-precision clock detecting method according to claim 2 is characterized in that the step of determining two phase place collecting apparatus phase mismatch during described step is 3. is:
A. the reference clock behind the frequency division is identical with the measured clock frequency, two accumulation of phase devices and or difference for definite value;
B. default value scope in the matching unit, and with these two accumulation of phase devices and or difference compare with preset range, as if within the preset range, proceed accumulation, if surpass preset range, two accumulation of phase devices in then zero clearing counter unit, and the initialization accumulation of phase unit.
5. high-precision clock detecting method according to claim 4 is characterized in that the threshold value N during described step is 5., the scope p of matching unit and three numerical value of frequency dividing ratio n of second clock frequency divider satisfy formula:
N＝p*n/S
Wherein, S is the clock accuracy constant that presets.
6. high-precision clock detecting method according to claim 1 is characterized in that the method for wrong output unit output measured clock mistake indication during described step is 5. is:
A. when matching unit output clock mismatch, relatively the generation periodic quantity and the predetermined threshold value of the cumulative errors counted of counter unit, the indication of output measured clock mistake when the generation periodic quantity of cumulative errors is less than or equal to predetermined threshold value;
Perhaps b. relatively the generation periodic quantity and the predetermined threshold value of the cumulative errors counted of counter unit in real time, the indication of output measured clock mistake when the generation periodic quantity of cumulative errors is less than or equal to predetermined threshold value.
7. pick-up unit that utilizes the described a kind of high-precision clock detecting method of claim 1, it is characterized in that this device comprises first Clock dividers (101), second clock frequency divider (102), the first accumulation of phase device (103), the second accumulation of phase device (104), matching unit (105), counter unit (105) and wrong output unit (106), one standard time clock inputs in the first accumulation of phase device (103) after by first Clock dividers (101) frequency division, drive the operation of the first accumulation of phase device (103) by this first Clock dividers (101) output signal, one measured clock inputs in the second accumulation of phase device (104) after by second clock frequency divider (102) frequency division, drive the operation of the second accumulation of phase device (104) by this second clock frequency divider (102) output signal, the described first accumulation of phase device (103) and the second accumulation of phase device (104) are formed an accumulation of phase unit, the data output end of the described first accumulation of phase device (103) and the second accumulation of phase device (104) is connected to the data input pin of described matching unit (105), a data output terminal of this matching unit (105) is connected in the data input pin of described counter unit (106), another data output end of described matching unit (105) is connected in the initialization input of accumulation of phase unit, described counter unit (106) input data are to wrong output unit (107), by the indicator signal of this mistake output unit (107) output measured clock mistake.
8. pick-up unit according to claim 7 is characterized in that described accumulation of phase device is counter or is circular shift register.
9. pick-up unit according to claim 7, it is characterized in that the described first accumulation of phase device (103) drives operation by the edge or the level of the reference clock behind the frequency division, the described second accumulation of phase device (104) is to be driven by the edge of measured clock behind the frequency division or level.
10. pick-up unit according to claim 7, it is characterized in that described matching unit (105) is to be connected to form by subtracter (301) and comparer (302), the first accumulation of phase device (103) and the second accumulation of phase device (104) access to subtracter (301) respectively, described comparer (302) output data is to counter unit (106), and output order is to the accumulation of phase unit.
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| CNB2007101277045A CN100516898C (en) | 2007-03-13 | 2007-06-18 | High precision clock detecting method and testing apparatus |
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| CN101431816B (en) * | 2008-11-19 | 2010-07-28 | 华为终端有限公司 | Frequency difference acquiring method and terminal |
| CN101908956B (en) * | 2009-06-08 | 2014-08-13 | 中兴通讯股份有限公司 | Timing signal based method and system thereof for improving clock precision |
| DE102010000962A1 (en) * | 2010-01-18 | 2011-07-21 | Robert Bosch GmbH, 70469 | Method and device for monitoring a frequency signal |
| CN102830750A (en) * | 2011-06-14 | 2012-12-19 | 赛酷特(北京)信息技术有限公司 | Real-time clock with high precision |
| CN102721865B (en) * | 2012-06-04 | 2015-06-17 | 惠州Tcl移动通信有限公司 | Method and system for measuring accuracy of crystal oscillators |
| CN105158557B (en) * | 2015-08-19 | 2018-05-04 | 河南科技大学 | A kind of frequency test method and corresponding frequency testing system |
| CN106707020B (en) * | 2016-12-22 | 2019-06-11 | 武汉盛帆电子股份有限公司 | Pulse detecting equipment and pulse detecting method |
| CN106656397B (en) * | 2017-03-01 | 2019-04-05 | 广州广哈通信股份有限公司 | Clock synchronizing method and device |
| KR20200081002A (en) * | 2018-12-27 | 2020-07-07 | 에스케이하이닉스 주식회사 | Semiconductor device |
| CN113093510B (en) * | 2021-02-26 | 2022-07-22 | 山东师范大学 | Clock frequency signal error measuring instrument and method |
| CN113108825B (en) * | 2021-03-26 | 2022-08-23 | 山东师范大学 | Atomic clock error measurement and correction method and error measurement and correction instrument |
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