CN100354636C - Method for testing clock duty cycle and test circuit - Google Patents

Method for testing clock duty cycle and test circuit Download PDF

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CN100354636C
CN100354636C CNB031500153A CN03150015A CN100354636C CN 100354636 C CN100354636 C CN 100354636C CN B031500153 A CNB031500153 A CN B031500153A CN 03150015 A CN03150015 A CN 03150015A CN 100354636 C CN100354636 C CN 100354636C
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clock
counter
measured
signal
reference clock
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CN1576863A (en
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张玉
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Honor Device Co Ltd
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Huawei Technologies Co Ltd
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Abstract

The present invention provides a testing method and a circuit for a clock duty ratio. After logical AND operation is made to a measured clock and a reference clock, a first signal is obtained. The first signal is delivered to a first counter. Logic NOT operation is made to the measured clock, and then, the logical AND operation is made to the measured clock and the reference clock to obtain a second signal. The second signal is delivered to a second counter. The first counter and the second counter are simultaneously counted to the first signal and the second signal under the control of the same reset signal. After a period of time, count values of the two counters are read out, and correlation parameters of the two clocks are combined to be counted for obtaining the duty ratio of the measured clock. When the method of the present invention is used for testing the clock duty ratio, the relative size of frequencies of the reference clock and the measured clock are not limited.

Description

A kind of method of testing of clock duty cycle and test circuit
Technical field
The present invention relates to the measuring technology in the moving communicating field, refer to a kind of method of testing and test circuit of clock duty cycle especially.
Background technology
The method of test clock dutycycle is in the prior art: utilize reference clock to come respectively high level and the low level time of measured clock in one-period to be counted respectively, then by calculating.
Suppose: high level is carried out test count, and to obtain count value be C 1, low level is carried out test count, and to obtain count value be C 2
So: the dutycycle of calculating the measured clock of gained is: D x = C 1 C 1 + C 2
The error that produces in the test mainly comes from the count value C of counter 1And C 2± 1 error.
Obviously compare when the frequency of reference clock and the frequency of measured clock, low more then test ± influence that 1 error is brought is just big more, on the contrary more little.
If when the frequency of reference clock during less than the frequency of measured clock, that is: f r<f xThe time, the influence that test error brings is just very big, to such an extent as to can not stand, thus the meaning of testing lost.
Therefore, under the lower situation of the frequency of the relative measured clock of testing of reference clock frequency, can not count the high level and the low level time of measured clock in one-period again, so can not adopt traditional dutycycle method of testing.
Summary of the invention
The invention provides a kind of method of testing and test circuit of the hard-core clock duty cycle of frequency size to reference clock and measured clock.
Method of testing of the present invention comprises:
After measured clock and reference clock carried out the logical operation, obtain first signal, this first signal is delivered to first counter;
After measured clock carried out the logic NOT operation, carry out the logical operation with reference clock again, obtain secondary signal, this secondary signal is delivered to second counter;
First counter and second counter are counted first signal and secondary signal under same reset signal control simultaneously;
After waiting for a period of time, read the count value of first counter and second counter, and, calculate the dutycycle of measured clock in conjunction with the frequency of frequency, dutycycle and the measured clock of reference clock.
The dutycycle of described calculating measured clock is: read the count value of two counters, the following formula of substitution calculates:
D x = A ( T ) + ( T r T x ) × [ A ( T ) - 1 ] × D r A ( T ) + 1 = A ( T ) + ( f x f r ) × [ A ( T ) - 1 ] × D r A ( T ) + 1
In the formula, D xBe the dutycycle of asking measured clock, A (T) is the ratio of the count value of the count value of first counter and second counter, T rBe the cycle of reference clock, T xBe the cycle of measured clock, f rBe the frequency of reference clock, D rBe the dutycycle of reference clock, f xFrequency for measured clock.
The described stand-by period, can calculate the time value of the maximum when getting counter and can not overflow according to the size and the clock frequency of counter.
The big I of described counter is selected according to the requirement of measuring accuracy.
The invention provides a kind of test circuit of clock duty cycle, comprising: first with door, second and door, not gate, first counter and second counter:
Described first with the door two input ends connect measured clock and reference clock respectively, its output terminal is connected to first counter;
The input termination measured clock of described not gate, output terminal be connected to second with the door an input end;
Described second with another input termination reference clock of door, output terminal is connected to second counter;
Described first and second counters are connected with same reseting controling signal, under the control of this reseting controling signal, begin counting simultaneously, the output count value;
Behind the certain interval of time, read the count value of first counter and second counter, and, can try to achieve the dutycycle of measured clock in conjunction with the frequency of frequency, dutycycle and the measured clock of reference clock.
The dutycycle of described measured signal can be tried to achieve according to following formula:
D x = A ( T ) + ( T r T x ) × [ A ( T ) - 1 ] × D r A ( T ) + 1 = A ( T ) + ( f x f r ) × [ A ( T ) - 1 ] × D r A ( T ) + 1
In the formula, D xBe the dutycycle of asking measured clock, A (T) is the ratio of the count value of the count value of first counter and second counter, T rBe the cycle of reference clock, T xBe the cycle of measured clock, f xBe the frequency of reference clock, D rBe the dutycycle of reference clock, f xFrequency for measured clock.
Described counter can adopt the rising edge of clock to count.
Described counter can adopt the negative edge of clock to count.
Compare with traditional dutycycle method of testing, the present invention can solve when reference clock frequency lower than measured clock frequency, and can't carry out the difficulty that dutycycle is tested.In fact the present invention also is applicable to the situation that reference clock frequency is higher than measured clock frequency, therefore, when using method of testing of the present invention and test circuit test clock dutycycle, to the frequency relative size of reference clock and measured clock without limits, but two clocks must satisfy no correlativity.
Description of drawings
Fig. 1 is the logic circuit structure synoptic diagram that the inventive method adopted.
Fig. 2 is a test circuit connection diagram of the present invention.
Fig. 3 is the test flow chart of the inventive method.
Embodiment
One, the realization principle of the inventive method
1, the logical circuit of the inventive method is realized
Suppose to have a reference clock Clk_R and a measured clock Clk_X, utilize clock Clk_R as a reference, the dutycycle that needs test clock Clk_X, we utilize logic circuit structure shown in Figure 1 to test, and process is as follows: after two clocks directly carry out the logical operation, obtain signal Clk_M1, deliver to counter 1, simultaneously measured clock is carried out the logic NOT operation earlier after, carry out logical operation with reference clock again, the signal Clk_M2 that obtains delivers to counter 2.Two counters are counted signal Clk_M1 and signal Clk_M2 under the extra control that resets simultaneously.After having arrived certain hour, read the count value of two counters, calculate in conjunction with two clock associated arguments by software algorithm or hardware circuit again, just can draw the dutycycle of measured clock Clk_X.
2, concrete calculating formula
The cycle of hypothetical reference clock Clk_R is T r, frequency is f r, dutycycle is D r
The cycle of supposing measured clock Clk_X is T x, frequency is f x, dutycycle is D x
T wherein x, f x, D r, T r, f rAll be known quantity, can obtain by additive method, and D xThe unknown, its method of testing is exactly a technical problem to be solved in the present invention.
Be located at certain constantly, the initial rising edge of reference clock and measured clock differs+T 0, behind T after a while, the rising edge of two clocks differs again+T for the n time 0
In above-mentioned time T, respectively signal Clk_M1 and signal Clk_M2 are counted respectively, can obtain with two counters:
To signal Clk_M1=Clk_X ﹠amp; The counter 1 that Clk_R counts, obtaining calculated value is C 1(T).
According to logical theory, count value C 1(T) can obtain like this: in the number+number of the rising edge of Clk_X between the Clk_R high period of the rising edge of Clk_R between the Clk_X high period.
Attention: when the frequency of reference clock Clk_R is the nonterminating and non-recurring decimal times of measured clock Clk_X frequency, the number of the rising edge of Clk_R between the Clk_X high period:
In like manner: when the frequency of measured clock Clk_X is the nonterminating and non-recurring decimal times of reference clock Clk_R frequency, the number of the rising edge of Clk_X between the Clk_R high period: Then
C 1 ( T ) = T T r × D x + T T x × D r ............①
To signal Clk_M2=(Clk_X) ﹠amp; The counter 2 that Clk_R counts, obtaining count value is C 2(T).
In like manner can obtain:
C 2 ( T ) = T T r × ( 1 - D x ) + T T x × D r ............②
Here the precondition of Shang Mian 1. formula and 2. formula establishment is same condition in fact, promptly is:
The ratio of the frequency of two clocks be a nonterminating and non-recurring decimal doubly because the inverse of nonterminating and non-recurring decimal still be a nonterminating and non-recurring decimal, therefore, 1. formula is identical with the precondition of 2. formula establishment.And all be to satisfy such condition for the clock that any two clock crystal sources of occurring in nature generate.We claim that this condition is " irrelevance " of two clocks.
For 1. formula and 2. formula, we suppose:
A ( T ) = C 1 ( T ) C 2 ( T ) , Then have:
A ( T ) = T T r × D x + T T x × D r T T r × ( 1 - D x ) + T T x × D r = T x × D x + T r × D r T x × ( 1 - D x ) + T r × D r = T x × D x + T r × D r T x - T x × D x + T r × D r
............③
D x = A ( T ) + ( T r T x ) × [ A ( T ) - 1 ] × D r A ( T ) + 1 = A ( T ) + ( f x f r ) × [ A ( T ) - 1 ] × D r A ( T ) + 1
............④
Illustrate: 4. formula is our computed duty cycle D xFundamental formular.
In order to access D accurately x, just must obtain T and A (T) accurately, according to " irrelevance " principle of clock, time T is non-existent, in other words T → ∞.However, in the test process of reality, owing to be not absolute 100% to the requirement of measuring accuracy, therefore, we can find an approximate T to realize test process according to different accuracy requirements.According to test philosophy, because two rising edge clocks all differ+T at every turn 0So no matter how counter is counted, A (T) is a constant A 0This is a perfect condition, and in the actual test, we can read the output valve of two counters and calculate by behind the period T of interval.
Two, test circuit of the present invention
Fig. 2 is a test circuit connection diagram of the present invention, and among the figure, input is: measured clock Clk_X and reference clock Clk_R, output is: the count value C of counter 1(T) and C 2(T), Reset is a reset signal, counts simultaneously in order to control counter 1 sum counter 2.Also include two logical AND gates and a logic inverter in the circuit, wherein first meet measured clock Clk_X and reference clock Clk_R respectively, should be connected to first counter with output terminal of door with two input ends of door; The input termination measured clock of logic inverter, output terminal be connected to second with the door an input end; Second with another input termination reference clock of door, output terminal is connected to second counter.
The course of work of foregoing circuit is: two clocks (reference clock and measured clock) of input are delivered to counter 1 after directly carrying out the logical operation.After simultaneously measured clock being carried out the logic NOT operation earlier, carry out the logical operation with reference clock again, deliver to counter 2.Two counters are counted under extra reset signal Reset control simultaneously, and output count value C 1(T) and C 2(T).
In the circuit, counter can adopt the rising edge of clock to count, and also can adopt the negative edge of clock to count.
Three, method of testing of the present invention
According to test circuit figure of the present invention, method of testing flow process of the present invention as shown in Figure 3.
After the test beginning, input measured clock and reference clock;
Two counters are unified to reset, make two counters begin counting simultaneously;
After waiting for a period of time, read the count value of two counters;
With the above-mentioned formula of count value substitution 4., can try to achieve the dutycycle of measured clock.
Wherein, the length of stand-by period can be estimated according to the size and the clock frequency of counter, and is as far as possible big, overflows but should guarantee that counter is unlikely.
Wherein, the size of counter also can be selected according to the requirement of measuring accuracy.When measuring accuracy is had relatively high expectations, can select bigger counter; When measuring accuracy requires to hang down, can select less relatively counter to test.
In addition, for formula computing method 4., can adopt software algorithm to realize; Also can adopt hardware circuit to realize, can also adopt logical device and logic software to realize.The implementation method of soft, hardware all belongs to prior art, so no longer describe in detail.

Claims (6)

1, a kind of method of testing of clock duty cycle comprises:
After measured clock and reference clock carried out the logical operation, obtain first signal, this first signal is delivered to first counter;
After measured clock carried out the logic NOT operation, carry out the logical operation with reference clock again, obtain secondary signal, this secondary signal is delivered to second counter;
First counter and second counter are counted first signal and secondary signal under same reset signal control simultaneously;
After waiting for a period of time, read the count value of first counter and second counter, the following formula of substitution calculates:
D x = A ( T ) + ( T r T x ) × [ A ( T ) - 1 ] × D r A ( T ) + 1 = A ( T ) + ( f x f r ) × [ A ( T ) - 1 ] × D r A ( T ) + 1
In the formula, D xBe the dutycycle of asking measured clock, A (T) is the ratio of the count value of the count value of first counter and second counter, T rBe the cycle of reference clock, T xBe the cycle of measured clock, f rBe the frequency of reference clock, D rBe the dutycycle of reference clock, f xFrequency for measured clock.
2, the method for testing of clock duty cycle as claimed in claim 1 is characterized in that: the described stand-by period, can calculate the time value of the maximum when getting counter and can not overflow according to the size and the clock frequency of counter.
3, the method for testing of clock duty cycle as claimed in claim 2 is characterized in that: the big I of described counter is selected according to the requirement of measuring accuracy.
4, a kind of test circuit of clock duty cycle is characterized in that comprising: first with door, second and door, not gate, first counter and second counter:
Described first with the door two input ends connect measured clock and reference clock respectively, its output terminal is connected to first counter;
The input termination measured clock of described not gate, output terminal be connected to second with the door an input end;
Described second with another input termination reference clock of door, output terminal is connected to second counter;
Described first and second counters are connected with same reseting controling signal, under the control of this reseting controling signal, begin counting simultaneously, the output count value;
Behind the certain interval of time, read the count value of first counter and second counter, can try to achieve the dutycycle of measured clock according to following formula:
D x = A ( T ) + ( T r T x ) × [ A ( T ) - 1 ] × D r A ( T ) + 1 = A ( T ) + ( f x f r ) × [ A ( T ) - 1 ] × D r A ( T ) + 1
In the formula, D xBe the dutycycle of asking measured clock, A (T) is the ratio of the count value of the count value of first counter and second counter, T rBe the cycle of reference clock, T xBe the cycle of measured clock, f rBe the frequency of reference clock, D rBe the dutycycle of reference clock, f xFrequency for measured clock.
5, the test circuit of clock duty cycle as claimed in claim 4 is characterized in that: described counter can adopt the rising edge of clock to count.
6, the test circuit of clock duty cycle as claimed in claim 4 is characterized in that: described counter can adopt the negative edge of clock to count.
CNB031500153A 2003-07-29 2003-07-29 Method for testing clock duty cycle and test circuit Active CN100354636C (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7260491B2 (en) * 2005-10-27 2007-08-21 International Business Machines Corporation Duty cycle measurement apparatus and method
US7595675B2 (en) * 2006-05-01 2009-09-29 International Business Machines Corporation Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
CN102638307B (en) * 2012-05-09 2014-12-03 北京理工大学 High-speed optical return-to-zero code duty cycle measuring method and device thereof

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US4330751A (en) * 1979-12-03 1982-05-18 Norlin Industries, Inc. Programmable frequency and duty cycle tone signal generator
US4475086A (en) * 1982-03-31 1984-10-02 Eastman Kodak Company Duty cycle detector
US6449200B1 (en) * 2001-07-17 2002-09-10 International Business Machines Corporation Duty-cycle-efficient SRAM cell test
CN1412947A (en) * 2002-10-30 2003-04-23 威盛电子股份有限公司 Buffer capable of regulating work period and its operation method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330751A (en) * 1979-12-03 1982-05-18 Norlin Industries, Inc. Programmable frequency and duty cycle tone signal generator
US4475086A (en) * 1982-03-31 1984-10-02 Eastman Kodak Company Duty cycle detector
US6449200B1 (en) * 2001-07-17 2002-09-10 International Business Machines Corporation Duty-cycle-efficient SRAM cell test
CN1412947A (en) * 2002-10-30 2003-04-23 威盛电子股份有限公司 Buffer capable of regulating work period and its operation method

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精密低频信号频率与占空比测量电路的设计与应用 汤黎明,常本康,刘铁兵,吴敏,凌刚.医学研究生学报,第15卷第4期 2002 *

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Patentee after: Glory Terminal Ltd.

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Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd.