CN115425091B - Semiconductor device film structure and preparation method - Google Patents
Semiconductor device film structure and preparation method Download PDFInfo
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- CN115425091B CN115425091B CN202211225080.1A CN202211225080A CN115425091B CN 115425091 B CN115425091 B CN 115425091B CN 202211225080 A CN202211225080 A CN 202211225080A CN 115425091 B CN115425091 B CN 115425091B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 261
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 261
- 239000010408 film Substances 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 108091006146 Channels Proteins 0.000 claims abstract description 97
- 238000000034 method Methods 0.000 claims abstract description 97
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 84
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 84
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims abstract description 64
- 239000010409 thin film Substances 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 238000001451 molecular beam epitaxy Methods 0.000 claims abstract description 45
- QGVYLCICHZYPJA-UHFFFAOYSA-N [Cr].[Cu].[Au] Chemical compound [Cr].[Cu].[Au] QGVYLCICHZYPJA-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 38
- 238000009713 electroplating Methods 0.000 claims abstract description 27
- 238000005192 partition Methods 0.000 claims abstract description 20
- 238000005520 cutting process Methods 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 238000005459 micromachining Methods 0.000 claims abstract description 12
- 238000001704 evaporation Methods 0.000 claims abstract description 11
- 230000008020 evaporation Effects 0.000 claims abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 34
- 239000010931 gold Substances 0.000 claims description 34
- 229910052737 gold Inorganic materials 0.000 claims description 34
- 239000012535 impurity Substances 0.000 claims description 33
- 230000001276 controlling effect Effects 0.000 claims description 26
- 230000008832 photodamage Effects 0.000 claims description 26
- 230000011218 segmentation Effects 0.000 claims description 26
- 238000000992 sputter etching Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 13
- 239000012159 carrier gas Substances 0.000 claims description 13
- 230000007797 corrosion Effects 0.000 claims description 13
- 238000005260 corrosion Methods 0.000 claims description 13
- 238000000407 epitaxy Methods 0.000 claims description 13
- 238000001465 metallisation Methods 0.000 claims description 13
- 238000012544 monitoring process Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000012495 reaction gas Substances 0.000 claims description 13
- 230000001105 regulatory effect Effects 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000003466 welding Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000009286 beneficial effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
- H01L29/454—Ohmic electrodes on AIII-BV compounds on thin film AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
- H01L29/66909—Vertical transistors, e.g. tecnetrons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66924—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8086—Thin film JFET's
Abstract
The invention provides a semiconductor device film structure and a preparation method thereof, comprising the following steps: gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer; gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method; longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed; metal electrode thin film layer: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the thin film structure of the chromium-copper-gold multilayer thin film metallized semiconductor device.
Description
Technical Field
The invention relates to the technical field of manufacturing of innovative intelligent structures of semiconductors, in particular to a thin film structure of a semiconductor device and a preparation method thereof.
Background
At present, the manufacture of the intelligent structure of the thin film of the semiconductor device is still to be improved in a large scale; problems exist including: how to form the longitudinal groove area and the transverse partition area; how to grow a gallium nitride growth layer; how to grow the P-type gallium nitride channel and form a longitudinal P-type channel and an N-type gate layer; how to form a plurality of conductive layers and finally form a thin film structure of the multi-layer thin film metallized semiconductor device; therefore, there is a need for a thin film structure of a semiconductor device and a method for fabricating the same that at least partially solve the problems of the prior art.
Disclosure of Invention
A series of concepts in simplified form are introduced in the summary section, which will be described in further detail in the detailed description section; the summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
To at least partially solve the above problems, the present invention provides a semiconductor device thin film structure, including:
gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
Gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
metal electrode thin film layer: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
Preferably, the gallium arsenide substrate layer comprises:
substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
Lateral partition: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
Preferably, the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps:
doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
gallium nitride growth region: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
Preferably, the longitudinal P-type channel and the N-type gate layer include:
p-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
Preferably, the metal electrode thin film layer includes:
gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The invention provides a preparation method of a semiconductor device film, which comprises the following steps:
s100: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
s200: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
s300: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
S400: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
Preferably, the step S100 includes:
s101: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
s102: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
s103: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
Preferably, the step S200 includes:
s201: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
s202: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
S203: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
Preferably, the step S300 includes:
s301: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
s302: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
s303: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
Preferably, the step S400 includes:
s401: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
s402: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
s403: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
Compared with the prior art, the invention at least comprises the following beneficial effects:
the invention provides a semiconductor device film structure, which comprises: gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer; gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method; longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed; metal electrode thin film layer: depositing and electroplating a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer by vacuum evaporation to obtain a metal electrode film layer; and finally forming a chromium-copper-gold multilayer thin film metallized semiconductor device thin film structure; the gallium arsenide substrate layer comprises: substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished; longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching; lateral partition: according to the design size, device segmentation is performed transversely to form a transverse segmentation area; the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps: doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded; impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded; gallium nitride growth region: taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method; the longitudinal P-type channel and N-type gate layer comprises: p-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove; ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method; longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; the longitudinal P-type channel and the N-type gate layer are finally formed by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss; the metal electrode thin film layer comprises: gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer; infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength; multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
fig. 1 is a block diagram of a semiconductor device film structure according to the present invention.
Fig. 2 is a flowchart of a method for manufacturing a semiconductor device film according to the present invention.
Fig. 3 is a diagram illustrating a method for manufacturing a thin film of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below with reference to the drawings and examples to enable those skilled in the art to practice the same and to refer to the description; as shown in fig. 1 to 3, the present invention provides a semiconductor device thin film structure comprising:
gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
Gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
metal electrode thin film layer: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The working principle of the technical scheme is as follows: the invention provides a semiconductor device film structure, which comprises:
gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
Metal electrode thin film layer: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The beneficial effects of the technical scheme are as follows: the invention provides a semiconductor device film structure, which comprises: gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer; gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method; longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed; metal electrode thin film layer: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming a chromium-copper-gold multilayer thin film metallized semiconductor device thin film structure; the gallium arsenide substrate layer comprises: substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished; longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching; lateral partition: according to the design size, device segmentation is performed transversely to form a transverse segmentation area; the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps: doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded; impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded; gallium nitride growth region: taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method; the longitudinal P-type channel and N-type gate layer comprises: p-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove; ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method; longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; the longitudinal P-type channel and the N-type gate layer are finally formed by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss; the metal electrode thin film layer comprises: gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer; infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength; multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
In one embodiment, the gallium arsenide substrate layer comprises:
substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
lateral partition: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
The working principle of the technical scheme is as follows: the gallium arsenide substrate layer comprises:
substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
Lateral partition: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
The beneficial effects of the technical scheme are as follows: the gallium arsenide substrate layer comprises: substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished; longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching; lateral partition: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
In one embodiment, the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps:
doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
Impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
gallium nitride growth region: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
The working principle of the technical scheme is as follows: the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps:
doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
gallium nitride growth region: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
The beneficial effects of the technical scheme are as follows: the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps: doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded; impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded; gallium nitride growth region: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
In one embodiment, the longitudinal P-type channel and N-type gate layer comprises:
p-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
The working principle of the technical scheme is as follows: the longitudinal P-type channel and N-type gate layer comprises:
p-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; the longitudinal P-type channel and the N-type gate layer are finally formed by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss; the selective area growth comprises the following steps: forming an N-type gallium nitride layer on the gallium nitride growth layer, wherein the N-type gallium nitride layer is formed on the gallium nitride growth layer; preparing a boss edge of the N-type gallium nitride layer in a nano-imprinting mode, wherein the distance between the bottom of the boss edge and the upper surface of the gallium nitride growth layer is as follows Protruding by over-etchingThe N-type gallium nitride layer at the bottom of the table edge is corroded.
The beneficial effects of the technical scheme are as follows: the longitudinal P-type channel and N-type gate layer comprises: p-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove; ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method; longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
In one embodiment, the metal electrode thin film layer includes:
gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
Multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The working principle of the technical scheme is as follows: the metal electrode thin film layer comprises:
gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength; the electroplating deposition comprises the steps of adopting an electroplating process to deposit a gold film;
multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The beneficial effects of the technical scheme are as follows: the metal electrode thin film layer comprises: gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer; infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength; multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The invention provides a preparation method of a semiconductor device film, which comprises the following steps:
s100: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
s200: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
s300: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
s400: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The working principle of the technical scheme is as follows: the invention provides a preparation method of a semiconductor device film, which comprises the following steps:
s100: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
S200: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
s300: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
s400: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The beneficial effects of the technical scheme are as follows: the invention provides a preparation method of a semiconductor device film, which comprises the following steps: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer; growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method; p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed; forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming a chromium-copper-gold multilayer thin film metallized semiconductor device thin film structure; according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished; on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching; according to the design size, device segmentation is performed transversely to form a transverse segmentation area; setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded; setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded; taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method; the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove; etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method; depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; the longitudinal P-type channel and the N-type gate layer are finally formed by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss; electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer; infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength; completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
In one embodiment, the step S100 includes:
s101: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
s102: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
s103: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
The working principle of the technical scheme is as follows: the step S100 includes:
s101: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
s102: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
S103: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
The beneficial effects of the technical scheme are as follows: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished; on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching; and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
In one embodiment, the step S200 includes:
s201: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
s202: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
s203: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
The working principle of the technical scheme is as follows: the step S200 includes:
s201: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
s202: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
s203: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
The beneficial effects of the technical scheme are as follows: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded; setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded; and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
In one embodiment, the step S300 includes:
s301: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
s302: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
S303: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
The working principle of the technical scheme is as follows: the step S300 includes:
s301: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
s302: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
s303: through homogeneous molecular beam epitaxy and selective growth, one longitudinal N-type gallium nitride boss is deposited on two sides of longitudinal P-type gallium nitride channel to form two sides of N-type gridThe method comprises the steps of carrying out a first treatment on the surface of the The longitudinal P-type channel and the N-type gate layer are finally formed by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss; the selective area growth comprises the following steps: forming an N-type gallium nitride layer on the gallium nitride growth layer, wherein the N-type gallium nitride layer is formed on the gallium nitride growth layer; preparing a boss edge of the N-type gallium nitride layer in a nano-imprinting mode, wherein the distance between the bottom of the boss edge and the upper surface of the gallium nitride growth layer is as follows And etching the N-type gallium nitride layer at the bottom of the lug boss edge through over-etching.
The beneficial effects of the technical scheme are as follows: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove; etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method; depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
In one embodiment, the step S400 includes:
s401: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
s402: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
s403: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The working principle of the technical scheme is as follows: the step S400 includes:
s401: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
s402: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
s403: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
The beneficial effects of the technical scheme are as follows: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer; infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength; completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (8)
1. A semiconductor device thin film structure, comprising:
gallium arsenide substrate layer: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
longitudinal P-type channel and N-type gate layer: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
metal electrode thin film layer: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming a chromium-copper-gold multilayer thin film metallized semiconductor device thin film structure;
the gallium arsenide substrate layer comprises:
substrate groove control region: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
Longitudinal groove forming region: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
lateral partition: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
2. The semiconductor device thin film structure of claim 1, wherein the gallium nitride growth layer: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method, wherein the method comprises the following steps:
doping the epitaxial growth region: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
impurity doped region: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
gallium nitride growth region: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
3. The thin film structure of a semiconductor device of claim 1, wherein the longitudinal P-channel and N-gate layer comprises:
P-type gallium nitride channel region: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
ion etching surface area: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
longitudinal N-type gallium nitride region: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
4. The thin film structure of a semiconductor device according to claim 1, wherein the metal electrode thin film layer comprises:
gold conductive region: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
infiltrating the conductive area: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
multilayer thin film metal region: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
5. A method for manufacturing a thin film of a semiconductor device, comprising:
s100: forming a longitudinal groove region on the bottommost layer of the semiconductor device film structure through femtosecond laser longitudinal micromachining, and forming a transverse partition region through transverse cutting to obtain a gallium arsenide substrate layer;
s200: growing a gallium nitride growth layer on the surface of the gallium arsenide substrate layer by a heterogeneous molecular beam epitaxy method;
s300: p-type gallium nitride channel growth is carried out in the longitudinal groove on the gallium nitride growth layer, a longitudinal N-type gallium nitride boss is respectively deposited on two sides of the longitudinal P-type gallium nitride channel surface, and finally a longitudinal P-type channel and an N-type gate layer are formed;
s400: forming a chromium-copper-Jin Duoceng conductive layer on the longitudinal P-type channel and the N-type grid layer through vacuum environment evaporation deposition and electroplating process to obtain a metal electrode film layer; and finally forming a chromium-copper-gold multilayer thin film metallized semiconductor device thin film structure;
the step S100 includes:
s101: according to the thickness of the gallium arsenide substrate layer and the depth of the designed longitudinal groove, regulating and controlling femtosecond laser pulse acting on the gallium nitride surface; the substrate groove regulation and control region is used for customizing accurate intelligent regulation and control of micro-size, and finally dividing and discarding after regulation and control are finished;
S102: on the bottommost gallium arsenide substrate layer of the semiconductor device film structure, femtosecond laser generates a light damage area on the gallium nitride surface, and the light damage area forms a longitudinal groove according to a preset longitudinal groove by longitudinal photoetching;
s103: and according to the design size, device segmentation is performed in the transverse direction to form a transverse segmentation area.
6. The method for manufacturing a thin film of a semiconductor device according to claim 5, wherein the step S200 comprises:
s201: setting nitrogen ion doping concentration, epitaxy temperature and growth pressure; the doped epitaxial growth region with non-uniform edges is finally discarded;
s202: setting a reaction gas, a carrier gas and an impurity source; the impurity doped region with non-uniform edges is finally discarded;
s203: and (3) taking a core uniform area on the surface of the gallium arsenide substrate layer, and growing a gallium nitride growth layer by a heterogeneous molecular beam epitaxy method.
7. The method for manufacturing a thin film of a semiconductor device according to claim 5, wherein the step S300 comprises:
s301: the mask shields the edge of the longitudinal groove on the groove gallium nitride growth layer, and P-type gallium nitride channel growth is carried out in the longitudinal groove;
s302: etching the edge of the P-type gallium nitride channel into a steep longitudinal P-type gallium nitride channel surface by an ion etching method;
S303: depositing a longitudinal N-type gallium nitride boss on each side of the longitudinal P-type gallium nitride channel surface by a homogeneous molecular beam epitaxy method and selective growth to form N-type grids on both sides; and finally forming a longitudinal P-type channel and an N-type gate layer by controlling the growth of the P-type gallium nitride channel and the size of the longitudinal N-type gallium nitride boss.
8. The method for manufacturing a thin film of a semiconductor device according to claim 5, wherein the step S400 comprises:
s401: electroplating and depositing a gold conductive region with the thickness of 0.8-3.2 microns on the longitudinal P-type channel and the N-type grid layer;
s402: infiltrating the gold conductive area with low-temperature solder based on lead and tin to obtain a second conductive area, and automatically monitoring the tensile strength;
s403: completing the subsequent welding of the point-to-point element and providing corrosion resistance in the use process of the device, obtaining a chromium-copper-gold multilayer film metallization structure and obtaining a metal electrode film layer; and finally forming the film structure of the chromium-copper-gold multilayer film metallized semiconductor device.
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| CN1279733A (en) * | 1997-10-20 | 2001-01-10 | 国家科研中心 | Method for producing a gallium nitride epitaxial layer |
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| CN113838816A (en) * | 2021-09-29 | 2021-12-24 | 太原理工大学 | Preparation method of gallium nitride-based diode device with diamond passivation layer |
| CN114864686A (en) * | 2022-03-31 | 2022-08-05 | 深圳智芯微电子科技有限公司 | Gallium nitride device and preparation method thereof |
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