CN115424924A - Manufacturing and etching method of polysilicon gate for manufacturing MOS (metal oxide semiconductor) tube gate - Google Patents
Manufacturing and etching method of polysilicon gate for manufacturing MOS (metal oxide semiconductor) tube gate Download PDFInfo
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- CN115424924A CN115424924A CN202211309826.7A CN202211309826A CN115424924A CN 115424924 A CN115424924 A CN 115424924A CN 202211309826 A CN202211309826 A CN 202211309826A CN 115424924 A CN115424924 A CN 115424924A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 151
- 238000005530 etching Methods 0.000 title claims abstract description 148
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 148
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title description 4
- 229910044991 metal oxide Inorganic materials 0.000 title description 3
- 150000004706 metal oxides Chemical class 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
Abstract
The invention relates to the technical field of MOS tube grid manufacturing, and discloses a method for manufacturing and etching a polysilicon gate for manufacturing the MOS tube grid, wherein the manufacturing method comprises the steps of manufacturing a first polysilicon gate layer, an etching stop layer and a second polysilicon gate layer on a substrate in sequence, and the etching method comprises the step of etching the second polysilicon gate layer, the etching stop layer and the first polysilicon gate layer in sequence for three times.
Description
Technical Field
The invention relates to the technical field of MOS (metal oxide semiconductor) tube grid manufacturing, in particular to a method for manufacturing and etching a polysilicon gate for manufacturing an MOS tube grid.
Background
In the semiconductor process technology, as the line width of a CMOS circuit is continuously reduced, a key index of a transistor, namely, the thickness of a gate oxide layer, is also continuously reduced, but the thickness of the gate oxide layer of the transistor cannot be infinitely reduced, otherwise, an obvious tunneling effect occurs, and the tunneling effect is exponentially increased along with the reduction of the thickness of the gate oxide layer. Based on this, HK is currently used in the technology node below 28nm to replace silicon dioxide as the dielectric layer, and then the gate material is replaced by a metal gate in order to improve the gate depletion problem, and the polysilicon gate originally fabricated on the gate oxide layer needs to be removed in the manufacturing process.
At present, a polysilicon Gate is usually etched by a dry etching and wet etching method or a wet etching method, an etching stop layer is on a Gate Oxide layer below the polysilicon Gate, and an over-etching amount is required in the etching process in order to completely remove the polysilicon Gate, so that the etching process can generate certain damage to the Gate Oxide layer or the side wall of the Gate Oxide layer, thereby affecting the reliability evaluation of Gate Oxide Integration (GOI). In addition, because the types of the MOS tubes are different, the lengths of the gates of the MOS tubes are different, and the etching rates of different MOS tubes are different, when the polysilicon gates at different positions are etched simultaneously, when the etching rates of the polysilicon gates at different positions are different, the positions of etching end points on the gate oxide layers on different MOS tubes are also different, and some polysilicon gates are etched too much on the gate oxide layers, so that the reliability evaluation of GOI is influenced, and the overall performance of a device is influenced.
Disclosure of Invention
In view of the shortcomings of the background art, the present invention provides a method for manufacturing and etching a polysilicon gate for manufacturing a gate of a MOS transistor, so as to reduce the etching amount of a gate oxide layer below the polysilicon gate when the polysilicon gate of the MOS transistor is manufactured and etched.
In order to solve the above technical problems, a first aspect of the present invention provides a method for manufacturing a polysilicon gate used for manufacturing a MOS transistor gate, including the following steps:
s1: manufacturing a first polysilicon gate layer with a first thickness on a substrate;
s2: manufacturing an etching stop layer with a second thickness on the first polysilicon gate layer;
s3: and manufacturing a second polysilicon gate layer with a second thickness on the first etching stop layer, wherein the etching selection ratio of the second polysilicon gate layer is greater than that of the etching stop layer.
In one embodiment of the first aspect, in step S2, the first polysilicon gate layer is oxidized, and an oxide layer with a second thickness is grown on top of the first polysilicon gate layer, where the oxide layer is the etching stop layer.
In one embodiment of the first aspect, the material of the etch stop layer is SIN or SION.
In one embodiment, the ratio of the thickness of the second polysilicon gate layer to the thickness of the first polysilicon gate layer is between 9 and 11.
In a certain embodiment of the first aspect, the first polysilicon gate layer, the etch stop layer, and the second polysilicon gate layer are fabricated in steps S1, S2, and S3 using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, respectively.
In one embodiment of the first aspect, the etch stop layer has a thickness between 9A and 11A.
In a second aspect, the present invention provides a method for etching a polysilicon gate used for MOS transistor gate fabrication, where the method for etching a polysilicon gate used for MOS transistor gate fabrication includes the following steps:
s1: manufacturing a mask plate above the second polycrystalline silicon layer;
s2: exposing a region corresponding to the polysilicon gate on the mask;
s3: etching the second polysilicon gate layer by using a first etching process;
s4: etching the etch stop layer using a second etch process;
s5: the first polysilicon gate layer is etched using a third etch process.
In one embodiment of the second aspect, in step S3, an etching selectivity of the etching material used in the first etching process to the second polysilicon gate layer is greater than an etching selectivity to the etch stop layer.
In one embodiment of the second aspect, in step S4, an etching selectivity of the etching material used in the second etching process to the etching stop layer is greater than an etching selectivity to the first polysilicon gate layer.
Compared with the prior art, the invention has the following beneficial effects: when the polysilicon gate of the MOS tube is manufactured, a first polysilicon gate layer with a first thickness is manufactured on a substrate, then an etching stop layer and a second polysilicon gate layer with a second thickness are sequentially manufactured, when the second polysilicon gate layer is etched, the etching selection ratio of the second polysilicon gate layer is larger than that of the etching stop layer, so that the etching end point when the second polysilicon layer is etched is on the etching stop layer by setting the thickness of the etching stop layer, when the etching stop layer is etched, the etching selection ratio of the etching stop layer is larger than that of the first polysilicon gate layer, so that the etching end point when the etching stop layer is etched is on the first polysilicon gate layer, and finally, the first polysilicon gate layer is etched, when the thickness of the first polysilicon gate layer is very small, such as below 50A, no matter how much thickness of the first polysilicon gate layer is etched when the etching stop layer is etched, the maximum thickness of the gate oxide layer is etched when the first polysilicon gate layer is etched, so that the maximum thickness of the gate oxide layer is not more than 50A when a plurality of MOS tubes are etched, and the gate oxide of the MOS tube is not over-etched at the same gate oxide length.
Drawings
FIG. 1 is a schematic thickness diagram of a gate oxide layer after etching a polysilicon gate on a conventional substrate;
FIG. 2 is a flow chart of a method of making the present invention in an embodiment;
FIG. 3 is a schematic view of a structure of a substrate in the embodiment;
FIG. 4 is a schematic diagram of the structure of FIG. 3 after a first polysilicon gate layer is formed thereon;
FIG. 5 is a schematic diagram of a completed etch stop layer formed over the structure of FIG. 4;
FIG. 6 is a schematic diagram of the structure of FIG. 5 after a second polysilicon gate layer has been formed thereon;
FIG. 7 is a flow chart of an etching method of the present invention;
FIG. 8 is a schematic diagram of the structure of FIG. 6 after etching a second polysilicon gate layer;
FIG. 9 is a schematic diagram of the structure of FIG. 8 after an etch stop layer has been etched over the structure;
fig. 10 is a schematic diagram of the structure of fig. 9 after etching the first polysilicon gate layer.
Detailed Description
Illustrative embodiments of the present application include, but are not limited to, a method of fabricating and etching a polysilicon gate for MOS transistor gate fabrication.
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The word "comprising" or "comprises", and the like, means that the element or item listed after "comprises" or "comprising" is inclusive of the element or item listed after "comprising" or "comprises", and the equivalent thereof, and does not exclude additional elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if," as used herein, may be interpreted as "when or" responsive to a determination, "depending on the context.
As shown in fig. 1, because the MOS transistors on the existing substrate have different types and different channel lengths, when polysilicon on the gate oxide layer is etched at the same time, the gate oxide layer is etched too much or too little due to different etching rates, and the reliability and performance of the gate oxide layer are affected after the polysilicon gate is etched.
In order to solve the above problem, as shown in fig. 2, the present embodiment provides a method for manufacturing a polysilicon gate for MOS transistor gate fabrication, including the following steps:
s1: manufacturing a first polysilicon gate layer 3 with a first thickness on a substrate 1;
s2: manufacturing an etching stop layer 4 with a second thickness on the first polysilicon gate layer 3;
s3: and manufacturing a second polysilicon gate layer 5 with a second thickness on the first etching stop layer 4, wherein the etching selection ratio of the second polysilicon gate layer 5 is greater than that of the etching stop layer 4.
In actual use, the substrate 1 may be an SOI substrate or a bulk silicon substrate. In one embodiment, the present invention may be employed to fabricate and etch polysilicon gates in other types of substrates.
Taking the structure of the substrate 1 in fig. 3 as an example, the substrate in fig. 3 is provided with an NMOS transistor, a PMOS transistor, and an IO NMOS transistor for IO, when a first polysilicon gate layer is grown on the substrate 1 in fig. 3, the first polysilicon gate layer 3 with a first thickness is grown on the gate oxide layer 2 on the NMOS transistor, the gate oxide layer 2 on the PMOS transistor, and the gate oxide layer on the IO NMOS transistor, respectively, and a schematic diagram after the first polysilicon gate layer 3 is manufactured is shown in fig. 4. In practical use, in order to facilitate the fabrication of the etching stop layer 4, after the fabrication of the first polysilicon gate layer 3 is completed, the top surface of the first polysilicon gate layer 3 is polished by a CMP (chemical mechanical polishing) process, so that the top surface of the first polysilicon gate layer 3 is flush.
After the first polysilicon gate layer 3 is manufactured, the etching stop layer 4 is respectively manufactured on the first polysilicon gate layer 3, and a schematic structural diagram after the etching stop layer 4 is manufactured is shown in fig. 5, and similarly, in order to facilitate the manufacturing of the second polysilicon gate layer 5, after the etching stop layer 4 is manufactured, the top surface of the etching stop layer 4 is polished by a CMP (chemical mechanical polishing) process, so that the top surface of the etching stop layer 4 is flush.
After the etching stop layer 4 is formed, a second polysilicon gate layer 5 is formed on the etching stop layer 4, and a schematic structural diagram of the second polysilicon gate layer 5 after the formation is shown in fig. 6, and similarly, in order to facilitate a subsequent etching process, after the formation of the second polysilicon gate layer 5, a CMP (chemical mechanical polishing) process is performed to polish the top surface of the second polysilicon gate layer 5, so that the top surface of the second polysilicon gate layer 5 is flush.
In practical use, the etching stopper layer 2 can be produced in the following two ways. The first method is as follows: in the step S2, the first polysilicon gate layer 3 is oxidized, and an oxide layer with a second thickness is grown on the top of the first polysilicon gate layer 3, wherein the oxide layer is an etching stop layer 4; the second method comprises the following steps: and depositing an SIN film or an SION film with a second thickness on the top of the first polysilicon gate layer 3, wherein the SIN film or the SION film is an etching stop layer 4.
Specifically, in the present embodiment, the thickness of the etching stopper layer 4 is between 9A and 11A.
Specifically, in the present embodiment, the ratio of the thickness of the second polysilicon gate layer 5 to the thickness of the first polysilicon gate layer 3 is between 9 and 11.
Specifically, in this embodiment, when the first polysilicon gate layer 3 is not oxidized in step S2, the first polysilicon gate layer, the etch stop layer, and the second polysilicon gate layer are respectively fabricated by using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process in steps S1, S2, and S3, and when the first polysilicon gate layer 3 is oxidized in step S2, the first polysilicon gate layer, the etch stop layer, and the second polysilicon gate layer are respectively fabricated by using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process in steps S1 and S3.
As shown in fig. 2, the present invention provides a method for etching a polysilicon gate used for manufacturing a MOS transistor gate, where the method for etching a polysilicon gate manufactured by the above method for manufacturing a polysilicon gate used for manufacturing a MOS transistor gate includes the following steps:
s1: manufacturing a mask above the second polycrystalline silicon layer 5;
s2: exposing a region corresponding to the polysilicon gate on the mask;
s3: etching the second polysilicon gate layer 5 using a first etching process;
s4: etching the etch stop layer 4 using a second etch process;
s5: the first polysilicon gate layer 3 is etched using a third etch process.
The polysilicon gate in step S2 includes a first polysilicon gate layer 3, an etch stop layer 4, and a second polysilicon gate layer 5. The photoresist on the mask manufactured in the step S1 may be a positive photoresist or a negative photoresist, and simultaneously, an ultraviolet photoresist, a deep ultraviolet photoresist, an X-ray photoresist, an electron beam photoresist or an ion beam photoresist may be adopted according to the difference between the exposure light source and the radiation source. In the step S2, according to different types of the photoresist, ultraviolet light, electron beams, ion beams, or X-rays may be used for irradiation or radiation during exposure to achieve exposure.
Taking the structure in fig. 6 as an example, when the first etching process is used to etch the second polysilicon gate layer 5, because the etching rates of the second polysilicon gate layers 5 in MOS transistors of different types and different trench lengths are different, the MOS transistor etched first in the second polysilicon gate layer 5 will continue to etch the etching stop layer 4, and by setting the thickness of the etching stop layer 4 and the etching selection ratio of the etching stop layer 4, the etching end point when etching the second polysilicon gate layers 5 of MOS transistors of different types and different trench lengths can be all on the etching stop layer 4, so that in actual use, the etching selection ratio of the etching material used in the first etching process to the second polysilicon gate layer 5 is greater than the etching selection ratio to the etching stop layer 4, and the structure schematic diagram of the structure in fig. 6 after the step S3 is executed is shown in fig. 8.
Specifically, in etching the second polysilicon gate layer 5, the second polysilicon gate layer is etched with the etching gas HBR or Cl2 in an environment close to vacuum, for example, an environment of 5 to 10mTorr atmospheric pressure within 1 to 2 minutes.
After the second polysilicon gate layer 5 is etched, the etching stop layer 4 is etched by using a second etching process, because in step S3, the MOS transistor of which the second polysilicon gate layer 5 is etched first, and a part of the etching stop layer 4 is also etched first, the thicknesses of the etching stop layers 4 of different MOS transistors in step S4 are different, and in order to make the etching end point in step S4 on the first polysilicon gate layer 3, the etching selection ratio of the etching material used in the second etching process to the etching stop layer 4 is greater than the etching selection ratio to the first polysilicon gate layer 3.
Specifically, in an environment close to vacuum, for example, an environment of 5 to 10mTorr atmospheric pressure, the etching stop layer 4 is etched using CHF3/CF4/O2 as an etching gas for 10 to 20 seconds, and a schematic view of the structure in which step S4 is performed on the structure in fig. 8 is shown in fig. 9.
When the etching device is in actual use, the etching influence on the polysilicon gate due to the category of the MOS tube and the difference of the trench length of the MOS tube can be reduced through the step S3 and the step S4, so that the thickness of the etched first polysilicon gate layer 3 in the step S5 is closer to each other, and the difference is small, therefore, when the first polysilicon gate layers 3 of different MOS tubes on the substrate 1 are etched simultaneously, the maximum etched gate oxide layer 2 does not exceed the thickness of the first polysilicon gate layer 3, and further, when the polysilicon gates of different types of MOS tubes and different trench lengths are etched simultaneously, the maximum etched gate oxide layer 2 of the MOS tubes does not exceed the thickness of the first polysilicon gate layer 3, and the gate oxide layer 2 is not etched excessively.
Specifically, the third etching process is to etch the first polysilicon gate layer 3 by using HBR/Cl2 in a near vacuum environment (e.g., an environment of 5 to 10mTorr atmospheric pressure), and the schematic structure diagram of the structure in fig. 9 after step S5 is performed is shown in fig. 10. The etching time for the third etching process to etch the first polysilicon gate layer is 30 seconds in practical use.
In summary, when manufacturing a polysilicon gate of a MOS transistor, the present invention manufactures a first polysilicon gate layer 3 with a first thickness on a substrate 1, and then sequentially manufactures an etching stop layer 4 and a second polysilicon gate layer 5 with a second thickness, when etching the second polysilicon gate layer 5, since the etching selection ratio of the second polysilicon gate layer 5 is greater than that of the etching stop layer 4, the etching end point when etching the second polysilicon layer 5 can be on the etching stop layer 4 by setting the thickness of the etching stop layer 4, and when etching the etching stop layer 4, since the etching selection ratio of the etching stop layer 4 is greater than that of the first polysilicon gate layer 5, the etching end point when etching the etching stop layer 4 is on the first polysilicon gate layer 3, and finally, by etching the first polysilicon gate layer 3, when the thickness of the first polysilicon gate layer is very small, for example, below 50A, no matter how much of the first polysilicon gate layer 3 is etched when etching the etching stop layer 4, the maximum etching end point of the polysilicon gate 2 is not greater than the etching end point of the first polysilicon gate, and the maximum etching gate oxide of the polysilicon gate 2 can not exceed the gate oxide length of the MOS transistor, thereby preventing the gate oxide from being over-etching the gate oxide of the MOS transistor.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (9)
1. A method for manufacturing a polysilicon gate for manufacturing a MOS tube gate is characterized by comprising the following steps:
s1: manufacturing a first polysilicon gate layer with a first thickness on a substrate;
s2: manufacturing an etching stop layer with a second thickness on the first polysilicon gate layer;
s3: and manufacturing a second polysilicon gate layer with a second thickness on the first etching stop layer, wherein the etching selection ratio of the second polysilicon gate layer is greater than that of the etching stop layer.
2. The method as claimed in claim 1, wherein in step S2, the first polysilicon gate layer is oxidized, and an oxide layer of a second thickness is grown on top of the first polysilicon gate layer, wherein the oxide layer is the etch stop layer.
3. The method as claimed in claim 1, wherein the etch stop layer is SIN or SION.
4. The method as claimed in claim 1, wherein the ratio of the thickness of the second polysilicon gate layer to the thickness of the first polysilicon gate layer is between 9 and 11.
5. The method as claimed in claim 1, wherein the first polysilicon gate layer, the etch stop layer and the second polysilicon gate layer are formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process in steps S1, S2 and S3, respectively.
6. The method as claimed in claim 1, wherein the thickness of the etch stop layer is between 9A and 11A.
7. A method for etching a polysilicon gate for manufacturing a MOS transistor gate, which is characterized in that the polysilicon gate manufactured by the method for manufacturing the polysilicon gate for manufacturing the MOS transistor gate according to any one of claims 1 to 6 is etched, and the method comprises the following steps:
s1: manufacturing a mask plate above the second polycrystalline silicon layer;
s2: exposing a region corresponding to the polysilicon gate on the mask;
s3: etching the second polysilicon gate layer by using a first etching process;
s4: etching the etch stop layer using a second etch process;
s5: the first polysilicon gate layer is etched using a third etch process.
8. The method as claimed in claim 7, wherein in step S3, the etching selectivity of the etching material used in the first etching process to the second polysilicon gate layer is greater than the etching selectivity to the etching stop layer.
9. The method as claimed in claim 7, wherein in step S4, the etching selectivity of the etching material used in the second etching process to the etching stop layer is greater than that to the first polysilicon gate layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210467654 | 2022-04-29 | ||
| CN202210467654X | 2022-04-29 |
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| CN115424924A true CN115424924A (en) | 2022-12-02 |
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| CN202211309826.7A Pending CN115424924A (en) | 2022-04-29 | 2022-10-25 | Manufacturing and etching method of polysilicon gate for manufacturing MOS (metal oxide semiconductor) tube gate |
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| CN (1) | CN115424924A (en) |
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