CN115424552B - Display substrate, aging control method of display substrate and display device - Google Patents
Display substrate, aging control method of display substrate and display deviceInfo
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- CN115424552B CN115424552B CN202211170311.3A CN202211170311A CN115424552B CN 115424552 B CN115424552 B CN 115424552B CN 202211170311 A CN202211170311 A CN 202211170311A CN 115424552 B CN115424552 B CN 115424552B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
- G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
本发明涉及显示控制技术领域，公开了一种显示基板、显示基板的老化控制方法及显示装置，上述显示基板包括：显示区域和包围显示区域的周边区域，显示区域包括至少两个显示分区，每个显示分区内具有多条电源电压信号线，周边区域包括与各显示分区一一对应的选通器件，各选通器件的输入端均与电源电压总线相连接，各选通器件的输出端与对应的显示分区中的多条电源电压信号线相连接，各选通器件用于分时导通显示分区中的各条电源电压信号线和电源电压总线，这样，不同显示分区中的发光器件就能够分时导通，避免了显示基板中所有像素对应的发光器件同时进行老化时会造成电流过大的情况出现，提高了显示产品的合格率。
The present invention relates to the field of display control technology, and discloses a display substrate, an aging control method for a display substrate, and a display device. The display substrate comprises: a display area and a peripheral area surrounding the display area, the display area comprises at least two display partitions, each display partition has a plurality of power supply voltage signal lines, the peripheral area comprises gating devices corresponding to each display partition one by one, the input end of each gating device is connected to a power supply voltage bus, the output end of each gating device is connected to a plurality of power supply voltage signal lines in the corresponding display partition, and each gating device is used to time-share conduct each power supply voltage signal line and the power supply voltage bus in the display partition, so that the light-emitting devices in different display partitions can be time-sharedly conducted, avoiding the situation that the current is too large when the light-emitting devices corresponding to all pixels in the display substrate are aged at the same time, thereby improving the qualified rate of the display product.
Description
Technical Field
The present invention relates to the field of display control technologies, and in particular, to a display substrate, an aging control method for the display substrate, and a display device.
Background
In the display industry, an Organic Light-Emitting Diode (OLED) product is subjected to Aging treatment before leaving the factory, that is, a life-time-Aging process is used for Aging the Light-Emitting device in advance, and the inherent rapid decay stage of the Light-Emitting device is consumed in advance, so that the service life of the Light-Emitting device is prolonged, and the factory qualification rate of the product is ensured.
At present, when a large-size OLED display panel is subjected to a life-time-Aging process, the problem that the life-time-Aging current (namely Aging current) is generally larger than the normal lighting current of pixels is caused, and because the size of the display panel is larger, all pixels are lightened during the life-time-Aging process, the current of the display panel is overlarge during the life-time-Aging process, and even a power line is burnt when serious.
Disclosure of Invention
The embodiment of the invention provides a display substrate, an aging control method of the display substrate and a display device, which are used for solving the problem that aging current is overlarge when all pixels of a display panel are subjected to aging simultaneously in the prior art.
The embodiment of the invention provides a display substrate, a display area and a peripheral area surrounding the display area;
the display area comprises at least two display subareas, and each display subarea is internally provided with a plurality of power supply voltage signal lines;
the peripheral area comprises gating devices which are in one-to-one correspondence with the display subareas, wherein the input ends of the gating devices are connected with the power voltage buses, the output ends of the gating devices are connected with a plurality of power voltage signal lines in the corresponding display subareas, and the gating devices are used for conducting the power voltage signal lines and the power voltage buses in the display subareas in a time-sharing mode.
Optionally, the control ends of the gating devices are respectively connected with different external control lines.
Optionally, the control ends of part of the gating devices in all the gating devices are connected with different external control lines after being short-circuited.
Optionally, display subareas corresponding to the gating devices with short-circuited control ends are arranged at intervals.
Optionally, the number of supply voltage signal lines within each display section is the same.
Optionally, the gating device is a P-type transistor and/or an N-type transistor.
Alternatively, the supply voltage bus is a high level supply bus, the supply voltage signal line is a high level supply signal line, and/or,
The power supply voltage bus is a low-level power supply bus, and the power supply voltage signal line is a low-level power supply signal line.
Optionally, the peripheral region has a bending region, and the gating device and the power voltage bus are both disposed on a side of the bending region facing away from the display region.
Correspondingly, the embodiment of the invention also provides an aging control method of the display substrate, which comprises the following steps:
All gating devices are controlled to conduct in a time sharing mode, and other gating devices are controlled to be disconnected when part of gating devices conduct, so that aging treatment is conducted on each display partition in a time sharing mode.
Correspondingly, the embodiment of the invention also provides a display device, which comprises the display substrate.
The invention has the following beneficial effects:
The display substrate comprises a display area and a peripheral area surrounding the display area, wherein the display area comprises at least two display subareas, each display subarea is internally provided with a plurality of power supply voltage signal lines, the peripheral area comprises gating devices which are in one-to-one correspondence with the display subareas, the input ends of the gating devices are connected with a power supply voltage bus, the output ends of the gating devices are connected with the power supply voltage signal lines in the corresponding display subareas, and the gating devices are used for conducting the power supply voltage signal lines and the power supply voltage bus in the display subareas in a time-sharing manner, so that the light-emitting devices in different display subareas can be conducted in a time-sharing manner, the occurrence of overlarge current caused by the simultaneous ageing of the light-emitting devices corresponding to all pixels in the display substrate is avoided, and the qualification rate of display products is improved.
Drawings
FIG. 1 is a schematic diagram of a display substrate in the prior art;
fig. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a display substrate controlled by a high-level power bus for partition burn-in according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a low-level power bus controlling a display substrate for partition burn-in according to an embodiment of the present application;
fig. 5 is a schematic diagram of a display substrate controlled by a high-level power bus and a low-level power bus for partition burn-in according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. It will be apparent that the described embodiments are some, but not all, embodiments of the application. And embodiments of the application and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present application fall within the protection scope of the present application.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the dimensions and shapes of the figures in the drawings do not reflect true proportions, and are intended to illustrate the present application only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
First, a display substrate commonly used in the prior art is introduced, and as shown in fig. 1, a display area of the display substrate includes a plurality of power voltage signal lines, wherein some of the power voltage signal lines are arranged transversely, the rest of the power voltage signal lines are arranged longitudinally, and the power voltage signal lines meet in a pad area below the display area.
In the normal light emitting process, the power voltage signal lines are respectively connected with a power voltage bus VDD and a power voltage bus VSS to trigger the light emitting devices corresponding to the pixel units to emit light, and normally, the VDD voltage is 4.6V and the VSS voltage is-2.4V in the normal light emitting process. In the life-Aging process, the voltage corresponding to the power voltage bus VDD connected to each power voltage signal line is increased, the voltage corresponding to VSS is reduced, and further an Aging voltage is determined, and the Aging voltage further triggers the light emitting device corresponding to the pixel unit to perform Aging processing. Obviously, each light emitting device in the whole display substrate is subjected to the burn-in treatment at the same time.
An embodiment of the application provides a display substrate, which is shown in fig. 2, and comprises a display area and a peripheral area surrounding the display area.
The display area comprises at least two display subareas, and each display subarea is internally provided with a plurality of power supply voltage signal lines.
The display area specifically refers to an area covered by all power supply voltage signal lines in the display substrate, part of the power supply voltage signal lines in all the power supply voltage signal lines are transversely arranged, and the rest of the power supply voltage signal lines are longitudinally arranged, and it is noted that the transverse distances between any two power supply voltage signal lines in the transverse arrangement may be equal or unequal, and the longitudinal distances between any two power supply voltage signal lines in the longitudinal arrangement may be equal or unequal.
In the embodiment of the application, the display area is divided into a plurality of display areas, and the plurality of display areas do not carry out the life-Aging process at the same time, namely the time-sharing Aging of each display area is realized. Accordingly, each display partition comprises at least one power supply voltage signal line, and the number of the power supply voltage signal lines in each display partition can be equal or equal.
The peripheral area comprises gating devices which are in one-to-one correspondence with the display subareas, wherein the input ends of the gating devices are connected with the power voltage buses, the output ends of the gating devices are connected with a plurality of power voltage signal lines in the corresponding display subareas, and the gating devices are used for conducting the power voltage signal lines and the power voltage buses in the display subareas in a time-sharing mode.
The peripheral area surrounds the display area, specifically, a power supply voltage bus connected with the power supply voltage signal lines in the peripheral area surrounds the periphery of the display area, and gating devices are further arranged in the peripheral area, wherein the number of the gating devices is consistent with that of the display area. The input end of the gating device corresponding to each display partition is connected with the power voltage bus in the display partition, and the output end of the gating device corresponding to each display partition is connected with a plurality of power voltage signal lines in the display partition.
When the gating device is turned on, each power voltage signal line in the display partition is communicated with the power voltage bus, so that aging current is generated in the pixel units in the display partition, and when the gating device is turned off, each power voltage signal line in the display partition is not communicated with the power voltage bus, so that the aging current cannot be generated in the pixel units in the display partition.
In order to make the aging effect of the display substrate more uniform, the number of power supply voltage signal lines in each display area is the same.
In one embodiment, the number of the horizontally arranged power supply voltage signal lines included in each of the display sections in the display area is the same, and the number of the vertically arranged power supply voltage signal lines included in each of the display sections in the display area is also the same, so that the number of the pixels covered in the display sections is the same, and each pixel can be subjected to the balanced aging process under the same aging current.
In the embodiment of the application, the control ends of the gating devices are respectively connected with different external control lines. In order to independently control each display area, the control end of the gating device can be controlled by different external control lines. In general, the different external control lines are arranged in the wiring terminal and are connected with different gating devices through different pins, and in the aging process, different voltage values are applied to different pins in the wiring terminal, so that the gating devices can be turned on and off.
Optionally, the gating device is a P-type transistor and/or an N-type transistor.
In the first case, when the gating device is a P-type transistor, the control end of the gating device is the G pole of the P-type transistor, the input end of the gating device is the S pole of the P-type transistor, and the output end of the gating device is the D pole of the P-type transistor.
In the second case, when the gating device is an N-type transistor, the control end of the gating device is the G pole of the N-type transistor, the input end of the gating device is the D pole of the N-type transistor, and the output end of the gating device is the S pole of the N-type transistor.
In one embodiment, some of the all gate devices are P-type transistors and the remaining gate devices of the all gate devices are N-type transistors, without undue restriction herein.
In consideration of the possible large number of display areas in the display area, the corresponding gate devices are also large in number, and in order to facilitate control, in the embodiment of the application, control ends of part of gate devices in all gate devices are connected with different external control lines after being short-circuited. That is, part of gating devices are controlled by the same external control line, so that the gating devices are convenient to control when the number of the gating devices is large in the implementation process.
Optionally, display subareas corresponding to the gating devices with short-circuited control ends are arranged at intervals.
Because the pixels in the display area can influence the surrounding pixels under the control of the aging current, in order to eliminate the influence (such as heat dissipation influence and the like), in the implementation process, the display area intervals corresponding to the gating devices with short-circuited control ends are arranged, so that the pixels in the whole display area can be aged uniformly under the control of the aging current, the aging current in the display area is balanced, and the influence of the aging current on the service life of the light emitting device is reduced.
Alternatively, the supply voltage bus is a high level supply bus, the supply voltage signal line is a high level supply signal line, and/or,
The power supply voltage bus is a low-level power supply bus, and the power supply voltage signal line is a low-level power supply signal line.
In the first case, the power supply voltage bus is a high-level power supply bus, and the power supply voltage signal line is a high-level power supply signal line.
In the implementation process, the power voltage bus is a high-level power bus, namely VDD, correspondingly, the power voltage bus is connected with the input end of the gating device and is a high-level power signal line, and the power voltage bus is connected with the output end of the gating device, so that the high-level control of the light emitting device is realized.
In the second case, the power supply voltage bus is a low-level power supply bus, and the power supply voltage signal line is a low-level power supply signal line.
In the implementation process, the power voltage bus is a low-level power bus, namely VSS, correspondingly, the power voltage bus is connected with the input end of the gating device and is a low-level power signal wire connected with the output end of the gating device, so that the low-level control of the light emitting device is realized.
In order to make the display effect of the display area better, the peripheral area in the embodiment of the application is provided with a bending area, and the gating device and the power voltage bus are arranged on one side of the bending area, which is away from the display area. Specifically, the gate devices for controlling the display sections are provided separately from the display area, and the power supply voltage bus and the like are also provided separately from the display area. Preferably, the gating device and the power voltage bus are both arranged in the bending area, so that the display effect of the display area is not affected while the display areas are conducted in a time-sharing manner for ageing.
The above is merely an example of a specific structure of each circuit in the calibration system provided in the embodiment of the present application, and the specific structure of the circuit is not limited to the above structure provided in the embodiment of the present application, but may be other structures known to those skilled in the art, which are all within the protection scope of the present application, and are not limited herein in particular.
The embodiment of the invention also provides an aging control method of the display substrate, which can comprise the following steps:
All gating devices are controlled to conduct in a time sharing mode, and other gating devices are controlled to be disconnected when part of gating devices conduct, so that aging treatment is conducted on each display partition in a time sharing mode.
In the aging process, only part of the display partitions in the display area are conducted at the same time, and the rest of the display partitions are not conducted, and whether the display partitions are conducted or not in the aging process is controlled by corresponding gating devices, namely, all the gating devices are conducted in a time-sharing mode under the control of different external control lines, so that all the display partitions in the display area are conducted correspondingly and aging is conducted.
The following two examples will be used to explain the present invention specifically.
In example 1, the display area in the display substrate includes four display sections arranged in sequence, and it is assumed that the four display sections are, from left to right, a display section a, a display section b, a display section c, and a display section d, respectively, and each display section has a plurality of power supply voltage signal lines (two power supply voltage signal lines arranged in a longitudinal direction).
The periphery of the display area is provided with a peripheral area, and four gating devices are included in the peripheral area, and as shown in fig. 3, the input ends of the four gating devices are connected with a power voltage bus VDD, and the output ends of the four gating devices are connected with a plurality of power voltage signal lines in the display partition. It is also assumed that the four gating devices are P-type transistor T1, P-type transistor T2, P-type transistor T3, and P-type transistor T4, respectively. The display area a corresponds to the P-type transistor T1, the display area b corresponds to the P-type transistor T2, the display area c corresponds to the P-type transistor T3, and the display area d corresponds to the P-type transistor T4.
In the following, referring to fig. 3 for example, during the life-time-Aging process, the input terminal of each gating device is connected to the high-level power bus VDD (e.g., any voltage value between 5V and 8V), and the output terminal of each gating device is connected to a plurality of power voltage signal lines in the corresponding display area, in which case the low-level power bus VSS is typically-2.4V.
In the first aging period, the P-type transistor T1 is turned on under the voltage control of the external control line VG1, the P-type transistor T3 is turned on under the voltage control of the external control line VG3, the P-type transistor T2 is turned off under the voltage control of the corresponding external control line VG2, and the P-type transistor T4 is turned off under the voltage control of the corresponding external control line VG 4. The display partition a conducts the high-level power bus VDD and the power voltage signal lines included in the display partition a under the condition that the P-type transistor T1 is conducted, the display partition c conducts the high-level power bus VDD and the power voltage signal lines included in the display partition c under the condition that the P-type transistor T3 is conducted, namely, the display partition a and the display partition c age under the voltage trigger of VDD, and meanwhile, the display partition b and the display partition d do not age.
In the second aging period, the P-type transistor T2 is turned on under the voltage control of the external control line VG2, the P-type transistor T4 is turned on under the voltage control of the external control line VG4, the P-type transistor T1 is turned off under the voltage control of the corresponding external control line VG1, and the P-type transistor T3 is turned off under the voltage control of the corresponding external control line VG 3. The display partition b turns on the high-level power bus VDD and the power voltage signal lines included in the display partition b under the condition that the P-type transistor T2 is turned on, and the display partition d turns on the high-level power bus VDD and the power voltage signal lines included in the display partition d under the condition that the P-type transistor T4 is turned on, that is, the display partition b and the display partition d age under the voltage trigger of VDD, and meanwhile the display partition a and the display partition c do not age.
In example 2, the display area in the display substrate includes four display sections arranged in sequence, and it is assumed that the four display sections are, from left to right, a display section a, a display section b, a display section c, and a display section d, respectively, and each display section has a plurality of power supply voltage signal lines (two power supply voltage signal lines arranged in a longitudinal direction).
The periphery of the display area is provided with a peripheral area, and four gating devices are included in the peripheral area, as shown in fig. 4 and 5, the input ends of the four gating devices are connected with a power voltage bus VSS, and the output ends of the four gating devices are connected with a plurality of power voltage signal lines in the display partition. It is also assumed that the four gating devices are P-type transistor T1, P-type transistor T2, P-type transistor T3, and P-type transistor T4, respectively. The display area a corresponds to the P-type transistor T1, the display area b corresponds to the P-type transistor T2, the display area c corresponds to the P-type transistor T3, and the display area d corresponds to the P-type transistor T4.
In the following, as will be described in detail with reference to fig. 4, during the life-time-Aging process, the input terminals of the gating devices are connected to the low-level power bus VSS (e.g., any voltage value between-3V and-8V), and the output terminals of the gating devices are connected to the power voltage signal lines in the corresponding display areas.
In the first aging period, the P-type transistor T1 is turned on under the voltage control of the external control line VG1, the P-type transistor T3 is turned on under the voltage control of the external control line VG3, the P-type transistor T2 is turned off under the voltage control of the corresponding external control line VG2, and the P-type transistor T4 is turned off under the voltage control of the corresponding external control line VG 4. The display section a turns on the low-level power bus VSS and the power voltage signal lines included in the display section a under the condition that the P-type transistor T1 is turned on, and the display section c turns on the low-level power bus VSS and the power voltage signal lines included in the display section c under the condition that the P-type transistor T3 is turned on, and in this case, VDD is a normal lighting current (for example, 4.6V), that is, the display section a and the display section c are aged under the voltage trigger of VDD and VSS, and the display section b and the display section d are not aged.
In the second aging period, the P-type transistor T2 is turned on under the voltage control of the external control line VG2, the P-type transistor T4 is turned on under the voltage control of the external control line VG4, the P-type transistor T1 is turned off under the voltage control of the corresponding external control line VG1, and the P-type transistor T3 is turned off under the voltage control of the corresponding external control line VG 3. The display section b turns on the low-level power bus VSS and the power voltage signal lines included in the display section b under the condition that the P-type transistor T2 is turned on, and the display section d turns on the low-level power bus VSS and the power voltage signal lines included in the display section d under the condition that the P-type transistor T4 is turned on, and in this case, VDD is a normal lighting current (for example, 4.6V), that is, the display section b and the display section d are aged under the voltage trigger of VDD and VSS, and the display section a and the display section c are not aged.
The embodiment of the invention also provides a display device, which comprises the display substrate.
The display substrate included in the display device can be subjected to a life-time-Aging process under the time-sharing conduction control of each gating device, namely different display partitions of the display substrate are respectively aged at different moments, so that the situation that the current of the display device is overlarge during Aging is avoided.
The display substrate comprises a display area and a peripheral area surrounding the display area, wherein the display area comprises at least two display subareas, each display subarea is internally provided with a plurality of power supply voltage signal lines, the peripheral area comprises gating devices which are in one-to-one correspondence with the display subareas, the input ends of the gating devices are connected with a power supply voltage bus, the output ends of the gating devices are connected with the power supply voltage signal lines in the corresponding display subareas, and the gating devices are used for conducting the power supply voltage signal lines and the power supply voltage bus in the display subareas in a time-sharing manner, so that the light-emitting devices in different display subareas can be conducted in a time-sharing manner, the occurrence of overlarge current caused by the simultaneous ageing of the light-emitting devices corresponding to all pixels in the display substrate is avoided, and the qualification rate of display products is improved.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211170311.3A CN115424552B (en) | 2022-09-23 | 2022-09-23 | Display substrate, aging control method of display substrate and display device |
Applications Claiming Priority (1)
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