CN115410902A - 一种改善铁电mos电容性能的方法 - Google Patents

一种改善铁电mos电容性能的方法 Download PDF

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CN115410902A
CN115410902A CN202211112656.3A CN202211112656A CN115410902A CN 115410902 A CN115410902 A CN 115410902A CN 202211112656 A CN202211112656 A CN 202211112656A CN 115410902 A CN115410902 A CN 115410902A
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ferroelectric
bottom electrode
improving
hafnium
dielectric layer
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陈琳
李振海
孟佳琳
王天宇
孙清清
张卫
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Fudan University
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Abstract

本发明公开一种改善铁电MOS电容性能的方法。该方法包括以下步骤：在Si衬底形成TiN底电极；在室温下采用氨等离子体对所述TiN底电极进行处理，使TiN底电极富N；在经处理后的所述TiN底电极上形成铪基铁电介质层；在所述铪基铁电介质层上形成TiN顶电极；在氮气氛围下进行快速热退火处理。

Description

一种改善铁电MOS电容性能的方法
技术领域
本发明涉及半导体技术领域，具体涉及一种改善铁电MOS电容性能的方法。
背景技术
2011年T.S.Boscke发现HfO2掺杂Si具有铁电性，之后Al、Zr和La等元素与HfO2掺杂均观测到铁电特性。随之，研究转向了与主流CMOS兼容的铪基铁电器件。与此同时，铪基铁电器件拥有较大的矫顽场(1-2MV/cm)这使得器件相较于传统的铁电材料(如钙钛矿、铌酸锂和PVDF)器件拥有较好的保持性。
然而，铪基铁电器件存在着严重的印记效用这将使器件的保持性严重下降。且铪基铁电的相结构为混合相并不是单一相结构，这使铪基铁电薄膜的铁电性能较弱，有待进一步的提高。现在通常用的方法是通过施加应力、元素的掺杂和改变氧化的条件提升薄膜的铁电性能。但是，通过改变氧化条件调控氧空位提升铁电相比例的同时，也增加了器件的印记效用。这使铪基铁电的发展陷入了两难的境地。
发明内容
本发明公开一种改善铁电MOS电容性能的方法，包括以下步骤：在Si衬底形成TiN底电极；在室温下采用氨等离子体对所述TiN底电极进行处理，使TiN底电极富N；在经处理后的所述TiN底电极上形成铪基铁电介质层；在所述铪基铁电介质层上形成TiN顶电极；在氮气氛围下进行快速热退火处理。
本发明的改善铁电MOS电容性能的方法中，优选为，所述铪基铁电介质层的掺杂元素为Si、Al、Zr或La。
本发明的改善铁电MOS电容性能的方法中，优选为，所述快速热退火的温度为500℃～900℃，时间为30s～45s。
本发明的改善铁电MOS电容性能的方法中，优选为，采用等离子增强原子层沉积方法形成铪基铁电介质层。
本发明的改善铁电MOS电容性能的方法中，优选为，采用氨等离子体对所述TiN底电极进行处理的步骤中，氨气的流速为30～70sccm，工作气压为1×10-2～8×10-2Torr，等离子体的电源功率为60～120W。
有益效果：
采用氨等离子体处理TiN底电极使其富N，提升了器件的界面质量增强了器件的铁电性能的同时避免了大量氧空位的产生，避免了器件的印记效应从而提升了器件的保持性。
采用原子层淀积技术生长介质薄膜，可以精确地控制薄膜的厚度，得到高保形性高质量的介质薄膜。
选择铪基铁电介质材料，可以减小介质层上所承受的电场强度，提高介质层的工作寿命，保证器件工作的稳定性。
附图说明
图1是改善铁电MOS电容性能的方法的流程图。
图2～图5是改善铁电MOS电容性能的方法各阶段的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“垂直”“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
图1是改善铁电MOS电容性能的方法的流程图。如图1所示，改善铁电MOS电容性能的方法包括以下步骤：
步骤S1，采用传统的RCA清洗工艺清洗Si衬底100，并且用N2吹干。
步骤S2，采用PVD方法在Si衬底100上溅射形成30nm～60nm厚的TiN底电极101，如图2所示。
步骤S3，如图3所示，使用等离子增强化学气相沉积方法(PECVD)在室温下采用氨等离子体处理TiN底电极101，其中氨气的流速为30～70sccm，工作气压为1×10-2～8×10- 2Torr，等离子体的电源功率为60～120W。
步骤S4，使用等离子增强原子层沉积方法(PEALD)在经处理后的TiN底电极101上沉积10nm～12nm厚的铪基铁电介质层103，如图4所示。铪基铁电介质层为掺杂HfO2，掺杂的其它元素可以是Si、Al、Zr和La等。采用氨等离子体处理TiN底电极使其富N，避免了贫氮的TiN从掺杂HfO2薄膜中吸收氧离子产生大量的氧空位破坏HfO2的晶体结构，提升了器件的界面质量，从而增强了器件的铁电性能，同时避免了器件的印记效应，从而提升了器件的保持性。
步骤S5，采用剥离法(lift-off)或者硬掩膜(hard mask)，在掺杂HfO2薄膜103上采用PVD溅射形成30nm～60nm TiN顶电极104，如图5所示。
步骤S6，在N2氛围下以500℃～900℃的温度进行30s～45s的快速热退火处理。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。

Claims (5)

1.一种改善铁电MOS电容性能的方法，其特征在于，
包括以下步骤：
在Si衬底形成TiN底电极；
在室温下采用氨等离子体对所述TiN底电极进行处理，使TiN底电极富N；
在经处理后的所述TiN底电极上形成铪基铁电介质层；
在所述铪基铁电介质层上形成TiN顶电极；
在氮气氛围下进行快速热退火处理。
2.根据权利要求1所述的改善铁电MOS电容性能的方法，其特征在于，
所述铪基铁电介质层的掺杂元素为Si、Al、Zr或La。
3.根据权利要求1所述的改善铁电MOS电容性能的方法，其特征在于，
所述快速热退火的温度为500℃～900℃，时间为30s～45s。
4.根据权利要求1所述的改善铁电MOS电容性能的方法，其特征在于，
采用等离子增强原子层沉积方法形成铪基铁电介质层。
5.根据权利要求1所述的改善铁电MOS电容性能的方法，其特征在于，
采用氨等离子体对所述TiN底电极进行处理的步骤中，氨气的流速为30～70sccm，工作气压为1×10-2～8×10-2Torr，等离子体的电源功率为60～120W。
CN202211112656.3A 2022-09-14 2022-09-14 一种改善铁电mos电容性能的方法 Pending CN115410902A (zh)

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