CN115408981A - Layout self-checking method and storage device - Google Patents

Layout self-checking method and storage device Download PDF

Info

Publication number
CN115408981A
CN115408981A CN202210865534.5A CN202210865534A CN115408981A CN 115408981 A CN115408981 A CN 115408981A CN 202210865534 A CN202210865534 A CN 202210865534A CN 115408981 A CN115408981 A CN 115408981A
Authority
CN
China
Prior art keywords
self
layout
layer
checking
connecting block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210865534.5A
Other languages
Chinese (zh)
Inventor
黄倩滨
彭焱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Guangli Microelectronics Co ltd
Original Assignee
Hangzhou Guangli Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Guangli Microelectronics Co ltd filed Critical Hangzhou Guangli Microelectronics Co ltd
Publication of CN115408981A publication Critical patent/CN115408981A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/392Floor-planning or layout, e.g. partitioning or placement

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention provides a layout self-checking method, which comprises the steps of obtaining all or part of winding path information to be self-checked in a layout and preset layout coloring layer rules; utilize preset territory dyed layer rule is right respectively treat the dyed layer information on the wire winding route of self-checking carries out the self-checking, include: and traversing and checking whether the coloring layer of each connecting block in the winding path to be self-checked is correct or not to obtain a self-checking result. By adopting the self-checking method, the colored layer of the layout can be quickly verified after the automatic winding is finished, and the problem can be found as early as possible; and for various connection conditions of the metal layer path, the correctness of the coloring layer covered on the metal layer can be automatically and quickly verified, the chip design efficiency is improved, and the process is further optimized. The invention also provides a storage device with corresponding advantages.

Description

Layout self-checking method and storage device
Technical Field
The invention belongs to the technical field of semiconductor design and production, and particularly relates to a layout self-checking method and storage equipment.
Background
In the integrated circuit industry, with the continuous advance of the chip process, the further reduction of the transistor size process and the reduction of the half pitch between metals, one photomask cannot meet the requirement of the same metal layer, and sometimes two, three or more photomasks are required. In the GDSII layout, for example, different photomasks need to be correspondingly distinguished by covering different colored layers (color layers) on the same metal layer, which also increases the problem of colored layer (color layer) collision in the layout to some extent. Therefore, it is very important to verify the correctness of the colored layer (color layer) covered by the metal layer (metal layer) path in the GDSII layout.
At present, in a conventional method for inspecting a coloring layer covered on a metal layer in a layout, the problem of color layer conflict is generally inspected by running DRC (design control rule), but at this time, the problem is in the latter half of a chip design flow, even if the problem is found, the problem is found to be later, and after the problem is found, revising the problem of color layer conflict can increase a lot of extra work, thereby affecting the whole production flow.
Therefore, a method for verifying the correctness of the color layer covered by the metal layer path in the GDSII layout at any time in the early stage of the chip design process or the whole design process needs to be researched, so that the method can be suitable for checking the colored layer covered by the metal layer in the layout, and the problems that the problem is found to be delayed and the production efficiency is influenced because the verification can be performed only in the second half stage in the current method are solved, thereby bringing convenience to the chip design and further promoting the deep development and the wide application of the semiconductor design and production technology.
Disclosure of Invention
The invention aims to solve all or part of the problems in the prior art, and provides a layout self-checking method which can check whether a color layer covered by a metal layer winding path of an integrated circuit layout is correct or not. Another aspect of the present invention provides a storage device storing instructions capable of executing the layout self-inspection method of the present invention.
The invention provides a layout self-checking method on one hand, which comprises the following steps: acquiring all or part of winding path information to be self-checked in a layout and a preset layout coloring layer (color layer) rule; wherein, the winding path is composed of a plurality of connecting blocks (paths) which are directly connected or connected by through holes (via) and contact holes (contact); the connecting block is of a polygonal structure in the connecting layer; the winding path information comprises coloring layer information; the preset layout coloring layer rule is configuration information and represents information of coloring layers which can be selected by a connecting layer in the layout; utilize predetermined territory dyed layer rule is right respectively treat that the dyed layer information of the wire winding route of self-checking carries out the self-checking, include: and traversing and checking whether the coloring layer of each connecting block in the winding path to be self-checked is correct or not to obtain a self-checking result. In the exemplary case, the preset layout coloring layer rule obtains the setting of the coloring layer, i.e., the preset layout coloring layer rule, from the layout design tool. Through obtaining preset territory dyed layer (color layer) rule earlier, in earlier stage or whole territory design process of chip design flow, can utilize at any time preset territory dyed layer rule carries out the dyed layer information self-checking to the winding route footpath, and whether the dyed layer that the metal layer covered on the winding route in the inspection territory has the conflict problem, and then can in time discover whether to have the problem, brings very big facility for chip design, has broken through the restriction that discovery problem lags among the current way, provides feasible solution for effectively guiding follow-up territory modification and process optimization.
According to the layout self-inspection method, different colored layers correspondingly represent different photomasks. Taking the GDSII layout as an example, there may be one or several photomasks covered with several colored layers for the same metal layer, and the colored layers correspond to the photomasks. When different light covers are correspondingly distinguished by covering different colored layers (color layers) on the same metal layer, the problem of colored layer (color layer) conflict in the layout can be timely and accurately found through the layout self-checking method.
Checking whether the coloring layer of the connecting block is correct or not, including checking: whether the coloring layer of the connecting block is correct or not; whether the connecting block is the same as the coloring layer of the directly connected pin or not is judged; and whether the connecting block is the same as the coloring layers of other directly connected connecting blocks on the same layer or not. Various situations that colored layers conflict possibly occur in the winding path are checked, and the correctness situation of the color layer covered on the metal layer in the layout design can be reflected more comprehensively in the self-checking result.
After the preset rule of the layout coloring layer is obtained, setting a dictionary data structure for storage; the dictionary data structure refers to: storing the connection layers as keys, and storing coloring layers that can be selected for each connection layer as values; and the key corresponds to a number of the values. The dictionary data structure is arranged to store the rule of the layout coloring layer, so that the rule can be conveniently searched and compared, the self-checking process is conveniently carried out, and the high-efficiency implementation of the self-checking process is facilitated.
And after the dictionary data structure is set, traversing the dictionary data structure, and finishing the layout self-check if all the coloring layers corresponding to the connecting layers are empty. The prejudgment is carried out by traversing the dictionary data structure, if all coloring layers corresponding to the connecting layers are empty, subsequent steps are not needed, so that the layout self-checking mechanism is perfected, and the overall efficiency is improved.
In a general case, each connecting block of all or part of winding paths to be self-tested is obtained and recorded as a set P { P1, P2, …, pi, …, pn }, wherein Pi is a connecting block, i belongs to [1,n ]; setting an error information data set E, initializing the error information data set E to be null, and initializing i =1; the method for traversing and checking whether the coloring layer of each connecting block in the winding path to be self-checked is correct comprises the following steps: the method comprises the following steps: according to the preset layout coloring layer rule, judging whether the connecting block Pi corresponds to a correct coloring layer: if yes, continuing the subsequent steps; if not, adding the error information to an error information data set E, and directly executing the step four; step two: judging whether the connecting block Pi and the pin have a direct connection relation: if yes, then according to preset territory colouring layer rule, judge again whether the colouring layer of connecting block Pi with the colouring layer of pin is the same: if the two are the same, continuing the subsequent steps; if the error information is different, adding the error information to an error information data set E, and directly executing the step four; if not, directly continuing the subsequent steps; step three: judging whether the connection block Pi has a direct connection relation with other connection blocks on the same layer: if the connection block Pi exists, judging whether the coloring layer of the connection block Pi is the same as the coloring layer of the directly connected connection block on the same layer according to the preset layout coloring layer rule: if the two are the same, continuing the subsequent steps; if the error information is different, adding the error information to an error information data set E and then starting the step four; if not, directly starting the step four; step four: judging whether i is equal to n: if yes, completing self-checking of all or part of winding paths to be self-checked, and obtaining a self-checking result, namely an error information data set E; if not, making i = i +1, and returning to the first step to continue the traversal. Only the error information is added to the set E, and if correct, a label similar to a Pi coloring layer error may be added to the set E. And each judgment is added in time once an error occurs. All or part of winding paths to be self-checked are self-checked in a mode of traversing the set P, so that error information data sets containing different types of error data information can be obtained to reflect specific problems, subsequent analysis and improvement are facilitated, and self-checking efficiency is higher.
After the self-checking of the winding path to be self-checked is completed, if the obtained error information data set E is empty, the verification of the winding path to be self-checked is passed, and if the obtained error information data set E is not empty, the verification of the winding path to be self-checked is not passed. And the self-checking result comprises whether the error information data set E is empty or not, and whether the winding path verification to be self-checked passes or not is intuitively judged through whether the data set is empty or not.
In other cases, after all the winding paths to be self-checked are self-checked, if all the winding paths to be self-checked pass the verification, the verification of the coloring layer of the layout is passed; if not, outputting a self-checking report for layout modification reference. The self-checking report can be automatically generated by utilizing the error information set and a preset report template.
Another aspect of the present invention provides a storage device having a plurality of instructions stored therein, the instructions being adapted to be loaded and executed by a processor to: the invention discloses a layout self-checking method.
Compared with the prior art, the invention has the main beneficial effects that:
1. the layout self-checking method has simple and efficient steps, can quickly verify the coloring layer (color layer) of the layout in the layout design process or at the end of automatic winding based on the preset rule of the coloring layer of the layout, can find problems in time, avoids the adverse effect of discovery lag on the whole production process, and provides an effective solution for further optimizing the process. And for various connection conditions of the winding path in the metal layer, the correctness of the color layer of the metal layer in the layout design can be automatically and quickly verified, the obtained self-checking result is comprehensive and reliable, the improvement of the subsequent layout design is greatly facilitated to be guided, and great convenience is brought to the chip design work.
2. The storage device stores instructions capable of executing the layout self-checking method.
Drawings
Fig. 1 is a schematic process diagram of a self-inspection method according to a first embodiment of the present invention.
Fig. 2 is a schematic view of a traversal procedure according to a first embodiment of the present invention.
Fig. 3 is a layout diagram of a second embodiment of the present invention.
Detailed Description
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings. The operations of the embodiments are depicted in the following embodiments in a particular order, which is provided for a better understanding of the details of the embodiments so as to provide a thorough understanding of the present invention, and are not intended to limit the scope of the invention. Hereinafter, a metal layer, a color layer, as an exemplary connection layer.
Example one
In the first embodiment of the present invention, the GDSII layout is taken as an example for easy understanding, but the specific situations of the layout design tool and the layout file format are not limited. As shown in fig. 1, the layout self-inspection method includes: step S1: acquiring color layer settings related to a metal layer in a layout design tool (acquiring preset layout coloring layer rules), and storing the color layer settings as a dictionary data structure, wherein the metal layer is used as a key, and correspondingly, color layer information selectable by the metal layer is used as a value. Step S2: and traversing the dictionary data structure in the step S1, if all color layers corresponding to the metal layers are empty, ending the self-checking process, otherwise, entering the step S3. And step S3: reading layout data, collecting the winding paths of all metal layers in the layout, respectively storing the winding paths to a data set, and respectively carrying out self-checking on the coloring layer information of each winding path to obtain and output a self-checking result. In this embodiment, the winding path to be self-checked is composed of a plurality of directly connected connection blocks or connection blocks connected by using through holes (via) and contact holes (contact), and the connection blocks are in a polygonal structure in a metal layer; in the present embodiment, the self-inspection is performed only on the colored layer of the connection block in the metal layer, that is, the self-inspection is not performed on the through hole and the contact hole, but the embodiment in which the self-inspection is also required on the through hole and the contact hole is not excluded, and the present invention is not limited thereto. The preset layout coloring layer rule of the example is configuration information which represents information of coloring layers selectable by a connecting layer in the layout.
In some implementations, when the self-checking result indicates that the layer photomask verification of the layout fails, in addition to outputting a failure conclusion, a self-checking report is formed and output by using error information obtained in the self-checking process, and the self-checking report is used as a reference for subsequent layout modification. The specific procedure is not limited herein.
It should be noted that the preset layout coloring layer rule obtained and the dictionary data structure are stored as an example of the self-inspection process facilitating in this embodiment, and in some implementation cases, other types of data structures are set for the self-inspection process, or a specific data structure is not set for storage, which is not limited to the specific implementation.
In this embodiment, a specific way of performing self-check on the metal path of the metal layer with reference to fig. 2 is as follows. Collecting all winding paths metal path in the layout, recording all connection blocks of all winding paths to be self-tested as a data set P { P1, P2, P3, …, pi, …, pn }, initializing an error information data set E, and initializing i =1:
judging one: and judging whether the connecting block Pi covers the color layer corresponding to the metal layer or not according to a preset layout coloring layer rule, if so, judging a second judgment, otherwise, adding error information Ej obtained through the first judgment to the set E, and directly judging a fourth judgment. And judging whether the color layer covered on the winding path metal path is consistent with the set color layer or not in the first process.
And II, judging: judging whether the connecting block Pi is connected with a pin of a unit structure (such as a transistor) in the layout, if not, judging a third judgment, if so, checking whether a color layer covered on the connecting block Pi is consistent with a color layer covered by the pin according to a preset layout coloring layer rule, if not, adding error information Em obtained by the second judgment to a set E, and directly judging a fourth judgment. And checking whether the color layer on the path of the first segment is consistent with the color layer of the pin or not by judging the second segment.
Judging three: judging whether the connecting block Pi is directly connected with other connecting blocks of the same metal layer on the periphery or not, if so, continuously judging whether the color layer of the connecting block Pi is consistent with the color layers of other connecting blocks of the same metal layer directly connected with the same metal layer according to a preset layout coloring layer rule, if not, adding error information Ek obtained by the judgment of the third step to a set E, and then entering a judgment of the fourth step; if the situation that the connection blocks are directly connected with other connection blocks of the same metal layer on the periphery does not exist, the fourth judgment is directly carried out. And checking whether the coloring color of the winding path metal path and the sharing path share path is consistent or not by judging whether the winding path metal path has the sharing path share path or not.
And (4) judging: judging whether the connecting block Pi is the last unverified connecting block (i.e. whether i is equal to n), and if so, judging five; and if not, returning to judge one after i = i + 1. And judging whether the connection block in the data set P is completely traversed or not by judging four.
And fifthly, judging: and judging whether the error information set E is empty, if so, judging that the verification result is pass, otherwise, judging that the verification result is failure, finishing self-checking and outputting the error information set E. In this embodiment, the error information set E can contain different types of error information, such as a coloring layer error Ej of the connection block itself, a coloring layer error Em of the connection block and a pin directly connected to the connection block, and a coloring layer error Ek of the connection block and another connection block in the same layer directly connected to the connection block.
In the example case, all the winding path information to be self-checked in the layout is obtained, and all the connection blocks of all the winding paths to be self-checked form a set P. In some implementation cases, only part of information of the winding paths to be self-checked in the layout can be acquired, the acquired winding paths to be self-checked are self-checked, and all the connecting blocks of the acquired winding paths to be self-checked are combined into a set. In other implementation cases, all the connection blocks of one winding path to be self-checked are used as a data set, and the connection blocks are traversed for each winding path to be self-checked, without limiting the specific implementation.
Example two
The present invention will be more fully understood by those skilled in the art from the following examples, which are not intended to limit the invention in any way. The embodiment takes the simple GDSII file shown in fig. 3 as an example to specifically exemplify the layout self-inspection method.
Firstly, reading a GDSII file to obtain a layout, and obtaining the setting of a color layer from a layout design tool to store as a dictionary data structure, namely { "M1_ drawing": M1CA _ drawing, M1CB _ drawing "," M2_ drawing ": M2CA _ drawing, M2CB _ drawing" }.
Reading winding paths of metal layer graphics on M1_ winding and M2_ winding in the GDSII file, wherein all connection blocks of all the winding paths are stored as a set P { P1, P2, P3, P4, P5}, and information stored in each connection block comprises the map layer, the path width and the coordinates of points. And initializes the error information set E. The exemplary routing path consists of a connection block, where the via pattern is illustrated by V1_ drawing in FIG. 3.
Traversing the set P, reading the first connection block P1, locating in the M1_ drawing layer, and determining that the layer is in one of color layer settings of the M1_ drawing, that is, M1CA _ drawing or M1CB _ drawing, where in the example shown in fig. 3, M1CA _ drawing meets the requirement. And then, judging whether a pin of the M1_ drawing layer intersects with the connecting block P1, wherein the P1 intersects with the pin I1, and the P1 and the pin I1 cover the same color layer, namely M1CA _ drawing, and the requirement is met. And the connection block P1 passes the verification because other connection blocks are not connected with the P1.
And reading a second connecting block P2, locating the second connecting block in the M2_ drawing layer, and skipping the check if the pin of the M2_ drawing layer does not intersect with the P2. And judging whether the M2_ drawing connecting block is intersected with the P2 or not, and finding out a connecting block P4. The connection block P4 is also located in the M2_ drawing layer, and it covers the color layer with the same coordinate, that is, M2CA _ drawing, and is consistent with the color layer of P2, and the connection block P2 passes the verification.
And reading a third connecting block P3, locating the third connecting block P3 in the M1_ drawing layer, and judging whether an M1_ drawing pin is intersected with the P3, wherein the P3 is intersected with the pin I12, and the layers with color layer of M1CA _ drawing are covered, so that the requirement is met. Since there is no M1_ drawing connection block to connect to P3, this check is skipped and connection block P3 verifies.
Reading a fourth connecting block P4, locating the fourth connecting block P4 in the M2_ drawing layer, covering the connecting block P4 with a layer with a color layer being M2CA _ drawing, and covering the connecting block P2 intersected with the fourth connecting block P4 with a color layer also being M2CA _ drawing, so that the connecting block P4 passes the verification.
And reading a fifth connecting block P5, locating the fifth connecting block P5 in the M1_ drawing layer, covering the connecting block P5 with the layer with the color layer being M1CB _ drawing, wherein the connecting block P5 has a pin I2 with the same layer, the color layer is M1CB _ drawing and is consistent with the connecting block P5, and the connecting block P5 passes the verification.
According to the self-checking mode, after all the connecting blocks are traversed, whether the final error information set is empty is judged, and if the final error information set is empty, information that the layout color layer verification passes is output; and if the routing path is not empty, outputting information such as a layer, a coordinate point, a color layer and the like of the routing path. The error types generally include that a winding path is covered with an error color layer, or the path is inconsistent with a pin color layer, and a winding path and a sharing path have color layer conflicts.
For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (9)

1. A layout self-checking method is characterized in that: the method comprises the following steps:
acquiring all or part of winding path information to be self-checked in the layout and preset layout coloring layer rules;
the winding path is composed of a plurality of connecting blocks which are directly connected or connected by using through holes and contact holes; the connecting block is of a polygonal structure in the connecting layer; the winding path information comprises coloring layer information; the preset layout coloring layer rule is configuration information and represents information of coloring layers which can be selected by a connecting layer in the layout;
utilize preset territory dyed layer rule is right respectively treat the dyed layer information on the wire winding route of self-checking carries out the self-checking, include: and traversing and checking whether the coloring layer of each connecting block in the winding path to be self-checked is correct or not to obtain a self-checking result.
2. The layout self-inspection method according to claim 1, characterized in that: different color layers correspond to different photomasks.
3. The layout self-inspection method according to claim 1, characterized in that: checking whether the coloring layer of the connecting block is correct or not, including checking: whether the coloring layer of the connecting block is correct or not; whether the connecting block is the same as the coloring layer of the directly connected pin or not is judged; and whether the connecting block is the same as the coloring layers of other directly connected connecting blocks on the same layer.
4. The layout self-inspection method according to claim 1, characterized in that: after the preset domain coloring layer rule is obtained, setting a dictionary data structure for storage; the dictionary data structure refers to: storing the connection layers as keys, and storing coloring layers that can be selected for each connection layer as values; and the key corresponds to a number of the values.
5. The layout self-inspection method according to claim 4, wherein: and after the dictionary data structure is set, traversing the dictionary data structure, and finishing the layout self-check if all the coloring layers corresponding to the connecting layers are empty.
6. The layout self-inspection method according to any one of claims 1 to 5, characterized in that: acquiring all or part of connecting blocks of a winding path to be self-tested and recording the connecting blocks as a set P { P1, P2, …, pi, …, pn }, wherein Pi is a connecting block, and i belongs to [1,n ]; setting an error information data set E, initializing the error information data set E to be null, and initializing i =1;
the method for ergodically checking whether the coloring layer of each connecting block in the winding path to be self-checked is correct comprises the following steps:
the method comprises the following steps: according to the preset layout coloring layer rule, judging whether the connecting block Pi corresponds to a correct coloring layer: if yes, continuing the subsequent steps; if not, adding the error information to an error information data set E, and directly executing the step four;
step two: judging whether the connecting block Pi and the pin have a direct connection relation:
if yes, then again according to preset territory colouring layer rule, judge whether the colouring layer of connecting block Pi with the colouring layer of pin is the same: if the two are the same, continuing the subsequent steps; if not, adding the error information to an error information data set E, and directly executing the step four;
if not, directly continuing the subsequent steps;
step three: judging whether the connecting block Pi has a direct connection relation with other connecting blocks on the same layer:
if the connection block Pi exists, judging whether the coloring layer of the connection block Pi is the same as the coloring layer of the directly connected connection block on the same layer according to the preset layout coloring layer rule: if the two are the same, continuing the subsequent steps; if the error information is different, adding the error information to an error information data set E and then starting the step four;
if not, directly starting the step four;
step four: judging whether i is equal to n: if yes, completing self-checking of all or part of winding paths to be self-checked, and obtaining a self-checking result, namely an error information data set E; if not, making i = i +1, and returning to the first step to continue the traversal.
7. The layout self-inspection method according to claim 6, wherein: after the self-checking of the winding path to be self-checked is completed, if the obtained error information data set E is empty, the verification of the winding path to be self-checked is passed, and if the obtained error information data set E is not empty, the verification of the winding path to be self-checked is not passed.
8. The layout self-inspection method according to claim 1, characterized in that: after the self-checking of all the winding paths to be self-checked is completed, if all the winding paths to be self-checked pass the verification, the verification of the coloring layer of the layout is passed; if not, outputting a self-checking report for layout modification reference.
9. A storage device having stored therein a plurality of instructions adapted to be loaded and executed by a processor: the layout self-inspection method according to any one of claims 1 to 8.
CN202210865534.5A 2021-12-31 2022-07-21 Layout self-checking method and storage device Pending CN115408981A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111657227 2021-12-31
CN202111657227X 2021-12-31

Publications (1)

Publication Number Publication Date
CN115408981A true CN115408981A (en) 2022-11-29

Family

ID=84157999

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210865534.5A Pending CN115408981A (en) 2021-12-31 2022-07-21 Layout self-checking method and storage device

Country Status (1)

Country Link
CN (1) CN115408981A (en)

Similar Documents

Publication Publication Date Title
US8086980B2 (en) Efficient power region checking of multi-supply voltage microprocessors
US8543965B1 (en) Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
US8832621B1 (en) Topology design using squish patterns
US9251299B1 (en) Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs
US9117052B1 (en) Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns
US8775979B2 (en) Failure analysis using design rules
US20080115102A1 (en) System and method for automatic elimination of connectivity mismatches during construction of a mask layout block, maintaining process design rule correctness
JP4602004B2 (en) Test pattern creation device, test pattern creation method, and test pattern creation program
US8472695B2 (en) Method and apparatus for failure analysis of semiconductor integrated circuit devices
WO2021249129A1 (en) Integrated circuit layout design rule deck check tool and check method
KR20200050427A (en) Systems and methods for systematic physical failure analysis (pfa) fault localization
US7013247B2 (en) Method of designing forms of cable clamp and cables using three-dimensional CAD system, and computer readable storage medium storing relevant processes
US9684748B1 (en) System and method for identifying an electrical short in an electronic design
CN115408981A (en) Layout self-checking method and storage device
JP2003086689A (en) Cad tool for failure analysis of semiconductor and failure analysis method of semiconductor
CN116245076A (en) Automatic construction method of DRC test version gallery, DRC method, DRC system and readable storage medium
US20230039473A1 (en) Wiring quality test method and apparatus and storage medium
US7353479B2 (en) Method for placing probing pad and computer readable recording medium for storing program thereof
US9983264B2 (en) Multiple defect diagnosis method and machine readable media
CN114139489A (en) Sequencing method for verifying unit layout in layout comparison
US9202001B1 (en) System and method for electronic design routing between terminals
US11586799B1 (en) Systems and methods of eliminating connectivity mismatches in a mask layout block
CN115270694B (en) Method for realizing wiring based on bus topology mode
CN118228682A (en) Chip power supply network integrity checking method, device, equipment and storage medium
CN118068235B (en) Detection method for wafer test structure, electronic equipment and storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination