CN118068235B - Detection method for wafer test structure, electronic equipment and storage medium - Google Patents
Detection method for wafer test structure, electronic equipment and storage medium Download PDFInfo
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- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/02—Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
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Abstract
Example embodiments of the present disclosure relate to a detection method for a wafer test structure, an electronic device, and a storage medium. The wafer test structure includes at least two ports adapted to connect with corresponding pads adapted to receive a test signal, the method comprising: generating a layout based on a preset connection relation between each port and the corresponding gasket; determining the position information of each port and the first position information of the corresponding gasket in the layout; starting from each port with the position information determined, searching the graph in the layout based on the preset connection relation between the layers of the layout; comparing the second position information of the searched pattern with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not; and determining the connection state between each port and the corresponding gasket based on the comparison result. The scheme of the present disclosure can greatly improve the inspection efficiency of the connection state between the test structure and the gasket.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of semiconductors, and more particularly, to a method of inspecting a wafer test structure, an electronic device, and a storage medium.
Background
After wafer handling is completed in a chip manufacturing Factory (FAB), various tests are required before shipping, one of the very important tests is wafer acceptance testing (WAFER ACCEPTANCE TEST, WAT for short), i.e., the quality and process stability of the wafer are evaluated by measuring the electrical parameters of a specific test structure (testkey, also called a test device) to determine whether the wafer meets the electrical specification requirements of its process platform. The test is performed by a specific test probe being tied to a test PAD (PAD) to apply a voltage or current test signal to the test structure. Whether the test structure is connected with the PAD correctly or not determines whether the WAT test can be successful or not. The test structure therefore needs to have its ports electrically connected to the PAD correctly during the design layout process. If the connection is wrong, the test result of the subsequent WAT is wrong.
In the traditional scheme, whether the port is correctly connected with the PAD is checked by a manual human eye checking mode of a layout engineer. The scheme has the defects of low efficiency, high error rate and the like.
Disclosure of Invention
In accordance with example embodiments of the present disclosure, an inspection scheme for wafer test structures is provided to at least partially overcome the above-described and other potential drawbacks.
In a first aspect of the present disclosure, a method of inspection for a wafer test structure is provided. The wafer test structure includes at least two ports, wherein each port is adapted to be connected to a respective pad, and the pads are adapted to receive a test signal. The method comprises the following steps: generating a layout based on a preset connection relation between each port and the corresponding gasket; determining the position information of each port and the first position information of the corresponding gasket in the layout; starting from each port with the position information determined, searching the graph in the layout based on the preset connection relation between the layers of the layout; comparing the second position information of the searched pattern with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not; and determining a connection state between each port and the corresponding gasket based on the comparison result.
In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions. The actions include: generating a layout based on a predetermined connection relationship between each port of a wafer test structure and a corresponding pad, wherein the wafer test structure comprises at least two ports, each port is suitable for being respectively connected with the corresponding pad, and the pad is suitable for receiving a detection signal; determining the position information of each port and the first position information of the corresponding gasket in the layout; starting from each port for which the position information is determined, searching the graph in the layout based on a preset connection relation between the layers of the layout; comparing the second position information of the searched graph with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not; and determining a connection state between each of the ports and the corresponding gasket based on the comparison result.
In some embodiments, determining the location of each port and the first location information of the corresponding pad in the layout includes: determining coordinate information of the port based on identification information of the port in the layout, wherein the identification information identifies the coordinates of the port in a text format; and analyzing the frame coordinates of the gasket in the layout to determine the first position information of the gasket.
In some embodiments, looking up the graph in the layout based on the predetermined connectivity relationship between layers of the layout, starting from each port where the location information is determined, respectively, comprises: and (3) respectively searching graphs in corresponding layers with communication relations from the metal layer where the port is located.
In some embodiments, starting from the metal layer where the port is located, searching the graphics in the corresponding layers with the connection relationship respectively includes: the graphics are searched in the corresponding layers according to a specified direction, and the specified direction is consistent with a direction along the corresponding path determined based on the predetermined connection relation.
In some embodiments, comparing the second position information of the found graphic with the first position information of the corresponding pad to generate a comparison result includes: generating a first result indicating that the second position information is consistent with the first position information in response to the fact that the coordinate information of the frame of the graph is consistent with the coordinate information of the frame of the corresponding gasket; and generating a second result indicating that the second position information is inconsistent with the first position information in response to the coordinate information of the border of the graphic being inconsistent with the coordinate information of the border of the corresponding gasket.
In some embodiments, determining the connection status between each port and the gasket based on the comparison results includes: determining the graph as a corresponding gasket based on the first result, thereby determining that the port is connected with the corresponding gasket; and determining the pattern as a non-corresponding shim based on the second result, thereby determining that the port is not connected to the corresponding shim.
In some embodiments, the layout includes at least one wafer test structure, the at least one wafer test structure and the corresponding pad form a test structure bar, the layout includes at least one test structure bar, and the predetermined connection relationship is a predetermined connection relationship table indicating connection relationships between respective ports of the at least one wafer test structure and the corresponding pad, respectively, and the method further includes: generating a connection status table based on connection status between each port of each test structure strip of the at least one test structure strip and the corresponding pad; comparing the connection state table with each connection relation in the preset connection relation table; responding to the complete consistency of the connection relations, and determining that the connection relation between each port of each wafer test structure and the corresponding gasket is correct; and in response to the presence of an inconsistency in the respective connection relationships, determining that there is an erroneous connection relationship between the respective ports and the gasket that are inconsistent.
In some embodiments, the path is a metal layer in the layout.
In a third aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a method according to the first aspect of the present disclosure.
According to the scheme of the embodiment of the disclosure, the detection efficiency of the connection relation between the test structure and the PAD can be greatly improved, so that a large amount of manpower can be saved; meanwhile, the error rate of the detection result can be obviously reduced.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
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The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:
FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure may be implemented;
FIG. 2 illustrates a block schematic diagram of an inspection method for a wafer test structure, according to some embodiments of the present disclosure;
FIG. 3 illustrates a flow chart of a method of inspection for a wafer test structure, according to some embodiments of the present disclosure;
FIG. 4 illustrates a connection relationship of a port and a pad of a wafer test structure according to some embodiments of the present disclosure;
FIG. 5 illustrates a layout schematic of a wafer test structure according to some embodiments of the present disclosure;
FIG. 6 illustrates a layout schematic of a test structure strip according to some embodiments of the present disclosure;
FIG. 7 illustrates a partial enlarged view of a wafer test structure and pads in the test structure strip of FIG. 6;
FIG. 8 illustrates a flow chart of a method of inspection of a wafer test structure according to some embodiments of the present disclosure;
FIG. 9 illustrates port names and their coordinate information for a wafer test structure according to some embodiments of the present disclosure;
FIG. 10 illustrates a shim serial number and its coordinate information determined from a layout according to some embodiments of the present disclosure;
FIG. 11 illustrates connectivity between layers in a layout according to some embodiments of the present disclosure;
FIG. 12 illustrates a schematic diagram of path tracing in a layout according to some embodiments of the present disclosure;
FIG. 13 illustrates a layout of a test structure strip according to some embodiments of the present disclosure;
FIG. 14 illustrates a test result of a connection relationship between a port and a gasket according to some embodiments of the present disclosure;
FIG. 15 illustrates a layout of a test structure strip according to further embodiments of the present disclosure;
FIG. 16 shows the test results of the connection between the port and the gasket according to the test structure strip shown in FIG. 15;
FIG. 17 illustrates a comparison of time statistics of a conventional method and an inspection method according to some embodiments of the present disclosure;
FIG. 18 illustrates a layout of a test structure strip containing Openshort structures according to some embodiments of the present disclosure;
FIG. 19 shows a close-up view of a layout according to the Openshort structure shown in FIG. 18;
FIG. 20 illustrates a layout of Openshort structures according to some embodiments of the present disclosure;
FIG. 21 shows the result of an inspection of an unspecified tracking direction of the test structure strip according to FIG. 18;
FIG. 22 illustrates port routing directions of a wafer test structure according to some embodiments of the present disclosure;
FIG. 23 shows the result of an inspection with tracking of port trends according to the description of FIG. 22; and
FIG. 24 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As mentioned before, after the wafer flow is completed at the chip fabrication facility, various inspections are required before shipment. Wafer flow refers to the process of transferring a circuit pattern on a wafer to photoresist and transferring the circuit pattern to the wafer by process steps such as etching. Wafer acceptance testing is a very important test that is performed by a specific test probe being tied to a test PAD. The test structure is finally transferred from the layout onto the wafer. PAD is also formed on the wafer, and is also formed from the layout through a dicing process. Typically, the large metal layers are interconnected layer by layer, and finally the large metal layers formed on the wafer are interconnected, and then the probe is pricked to the PAD during WAT test, and the PAD is connected with the test structure. And applying a specific voltage or current signal to the PAD through a test machine to perform the test.
Therefore, in the process of designing a layout, a test structure needs to connect a port (terminal) thereof with a PAD through a metal wire (metal layer), so that the control of test conditions of the test structure is realized by applying current or voltage to the PAD in the test process. The same FAB typically has a uniform number of PADs and PAD spacing with test structures placed between the PADs. After the layout engineer completes the design of the test structure, the test structure and the corresponding PAD need to be connected by a metal wire, and this complete structure containing the test structure and PAD is referred to as a test structure strip (testline). Whether the test structure is connected with the PAD or not determines whether WAT test can be realized, so that it is important to ensure the connection accuracy of the test structure and the PAD. Wherein the test items may include front-end parameters and back-end parameters. The front channel parameters include, for example, the source-drain breakdown voltage, leakage current, etc. of the device; the subsequent parameters may include Metal resistance of resistor/capacitor, via resistance, dielectric breakdown voltage, etc.
In the process of designing the test structure strip in the traditional way, a layout engineer needs to perform metal connection work according to the placement positions (between which 2 PADs) of the test structures and the corresponding relation between the ports of the test structures and the PADs (for example, terminal1 and PAD1, terminal2 and PAD2 are connected) after all the test structures are drawn, and finally, the layout of the complete test structure strip is obtained. If the connection line is disconnected or short-circuited in the final test structure strip, the test fails, so that the correctness of the connection line between the test structure and the PAD is ensured by checking, and the final layout and the subsequent test can be realized according to a plan.
As technology nodes shrink gradually, process architecture and design rules become more and more complex, the types, numbers and complexity of test structures increase significantly, and a large number of test structures connected to PADs can produce tens or even hundreds of test structure strips. The correctness of the connection relation between the test structure and the PAD is checked by using the traditional manual human eye checking method by a layout engineer, a great deal of labor and time cost are required, various uncontrollable factors exist in the manual checking, and the risk of human errors is high.
The traditional winding correctness checking method is that a layout engineer sequentially compares whether an actual layout is consistent with a winding plan table or not through manual human eyes, and the method has the problems of long time consumption of manual checking and uncontrollable human errors.
In view of this, the present disclosure provides an improved solution.
According to an embodiment of the present disclosure, a method for inspecting a wafer test structure is provided. The wafer test structure includes at least two ports, wherein each port is adapted to be connected to a respective pad, and the pads are adapted to receive a test signal. The method comprises the following steps: a layout is generated based on predetermined connection relationships between each port and the corresponding pad, the predetermined connection relationships being specifiable by a user. Position information of each port and first position information of a corresponding gasket are determined in the layout. And respectively starting from each port for determining the position information, searching the graph in the layout based on the preset connection relation among the layers of the layout, wherein the preset connection relation indicates which layers are connected or are connected. Comparing the second position information of the searched pattern with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not. And determining the connection state between each port and the corresponding gasket based on the comparison result, and obtaining whether the ports are correctly connected with the gaskets or not through the connection state. According to the scheme of the embodiment of the disclosure, the connection relation between the port of the test structure and the gasket is extracted from the layout and compared with the preset connection relation, so that the inspection efficiency of the connection relation between the wafer test structure and the gasket can be greatly improved, and the error rate is remarkably reduced. Specifically, the scheme of the embodiment of the disclosure can meet the rapid and automatic inspection of the correctness of the connection relation between a large number of diverse test structures and the PAD, and compared with the traditional manual inspection, the efficiency can be improved by thousands of times.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Referring initially to FIG. 1, a schematic diagram of an example environment 100 in which various embodiments of the present disclosure can be implemented is shown. As shown in fig. 1, an example environment 100 includes a computing device 110, a client 120.
In some embodiments, computing device 110 may interact with client 120. For example, computing device 110 may receive an input message from client 120 and output a feedback message to client 120. In some embodiments, the input message from the client 120 may include, for example, a design file for generating a layout. The computing device 110 may perform layout design based on the design file and may perform subsequent detection processing. The computing device 110 may output the corresponding operation result to the client 120.
In some embodiments, computing device 110 may include, but is not limited to, personal computers, server computers, hand-held or laptop devices, mobile devices (such as mobile phones, personal digital assistants PDAs, media players, etc.), consumer electronics, minicomputers, mainframe computers, cloud computing resources, and the like.
It should be understood that the description of the structure and functionality of the example environment 100 is for illustrative purposes only and is not intended to limit the scope of the subject matter described herein. The subject matter described herein may be implemented in different structures and/or functions.
The technical solutions described above are only for example and not limiting the present disclosure. It should be appreciated that the example environment 100 may also have other various implementations. In order to more clearly explain the principles of the disclosed solution, a more detailed description will be made below with reference to the figures.
Referring first to fig. 2, fig. 2 illustrates a block schematic diagram of an inspection method for a wafer test structure according to some embodiments of the present disclosure. In some embodiments, a connection relationship is determined at block 202. The connection relationships may be presented in the form of a table, such as a connection relationship table. The present disclosure is not limited to the specific form thereof. The connection table may be provided by the user, in which connection table the connection between the port and the PAD is specified. A layout may be generated based on the connection relationship table. The connection of the port to the PAD may in turn be extracted from the layout, whereby a check generation table may be generated at block 204, describing the connection between the detected port and PAD. The connection relationship table is compared with the generated check generation table at block 206 to determine if the connection state between the ports in the two tables and the PAD are consistent. At block 208, based on the results of the comparison, a display is made of the correctness of the connection. The main concept of the detection method according to the embodiment of the present disclosure is briefly shown in fig. 2, and is described in detail with reference to fig. 3.
Fig. 3 illustrates a flow chart of an inspection method 300 for a wafer test structure according to some embodiments of the present disclosure. For example, the method 300 may be implemented by the computing device 110 as shown in fig. 1. It should be understood that method 300 may also include additional blocks not shown and/or that certain blocks shown may be omitted. The scope of the present disclosure is not limited in this respect.
At block 302, a layout is generated based on predetermined connection relationships between respective ports and corresponding shims. In some embodiments, the wafer test structure includes at least two ports, wherein each port is adapted to be connected with a respective pad, the pads being adapted to receive a detection signal, such as a signal from a probe, to perform performance testing of the test structure. The predetermined connection relationship may be provided in advance by the user, i.e. the layout engineer may make a layout based on the predetermined connection relationship provided by the user. The layout may include test structures and pads connected to ports of the test structures. The layout can comprise at least one wafer test structure, and the at least one wafer test structure and the corresponding pad form a test structure strip. At least one test structure strip may be included in the layout, and typically tens or hundreds of test structure strips may be included. In this case, the predetermined connection relationships may indicate the connection relationships between the respective ports of the wafer test structure and the corresponding pads, respectively, in the form of a table, as shown in fig. 4. The following description is made with reference to fig. 4.
Fig. 4 illustrates a connection relationship of a port and a pad of a wafer test structure according to some embodiments of the present disclosure. The connection is a connection between a port for specifying a test structure and a PAD, which is planned in advance by a user. In which the name of each test structure and the test structure strip in which it resides is written. The latter columns in fig. 4 are port names for the test structure. The number and name of ports for different test structures are not fixed and are typically set by the user. The most typical device transistors are illustrated in fig. 4 as 4 test ports, namely port 1 (G), port 2 (D), port 3 (S), and port 4 (B). The PAD serial number is filled in the content line shown in fig. 4, the first line means that the G end of the MOS1 test structure is connected to PAD1, the D end is connected to PAD2, the S end is connected to PAD3, the B end is connected to PAD4, and the test structure strip where the MOS1 is located is TL01. It should be understood that the format and contents shown in fig. 4 are merely illustrative, and various changes may be made as needed, and the present disclosure is not limited thereto.
Referring now to fig. 5, fig. 5 illustrates a layout schematic of a wafer test structure according to some embodiments of the present disclosure. As shown in fig. 5, the wafer test structure is a MOS transistor. It includes four ports, namely port 502 (G), port 504 (D), port 506 (S), and port 508 (B). Wherein G is the gate, D is the drain, S is the source, and B is the well. It should be understood that the test structure shown in fig. 5 is only an example, and it is obvious that the test structure may be other components with different structural forms, and the disclosure is not limited thereto.
Referring now to FIG. 6, FIG. 6 illustrates a layout schematic of a test structure strip TL01 in accordance with some embodiments of the disclosure. As shown in fig. 6, the test structure strip includes a plurality of test structures 602 and a plurality of pads 604. The test structure 602 and the pad 604 are connected by a wire 606. The number of test structures 602 and pads 604 in the test structure strip may vary according to actual needs.
With further reference to fig. 7, fig. 7 shows an enlarged view of a portion of a wafer test structure and pads in the test structure strip TL01 according to fig. 6. As best seen in fig. 7, four pads 604 (01, 02, 03, 04, respectively) are each connected to a corresponding port of the wafer test structure 602 via leads (wires) 606.
The description is continued with reference to fig. 3.
At block 304, position information for each port and corresponding pad is determined in the layout, which may be referred to as first position information. In some embodiments, the coordinate information of the port may be determined based on identification information of the port in the layout, wherein the identification information may identify the coordinates of the port in a text format. The connection of the port of the test structure to the PAD determines how the final probe gives the test conditions. As mentioned previously, a plurality of test structure strips may be included in the layout, and a plurality of test structure strips may be included in each test structure strip, each test structure comprising at least two ports. In some embodiments, to distinguish between the ports, the name of the test structure strip, the name of the test structure, the name of the port, etc. (described below with reference to fig. 9) may be resolved first, so that it is known which ports need to be connected to the PAD. It should be understood that the names of the analytical test structures strips, test structures, port names, etc. mentioned herein are not required, but may be selected depending on the particular situation. Usually, the name of the port is identified in the layout by a specific text, and can be extracted by layout parsing software. Then, based on the name of the port and according to the layout structure of the layout, the coordinates of the port, the coordinate information of the PAD and the like can be analyzed, and therefore the position of the port and the position of the PAD can be determined. The connected PAD may then be tracked from the location of the port.
In some embodiments, the frame coordinates of the pads in the layout may be parsed to determine the location information of the pads, i.e., the first location information. For example, it may be parsed by layout parsing software. The shape of the PAD in the layout is usually rectangular, and the coordinates of the lower left corner and the upper right corner of the rectangle can be resolved as the position coordinates of the PAD. It should be understood that the shape of the spacer is not limited to rectangular, but may be other shapes, for example, a polygonal-like shape, etc., and the present disclosure is not limited thereto. For PADs of other shapes, the coordinates thereof may be determined in a similar manner. For example, its location information is determined by determining the coordinates of a particular location point of its border.
Referring to fig. 9, fig. 9 illustrates port names and their coordinate information of a wafer test structure according to some embodiments of the present disclosure. The test structure names, test structure strip names, and individual ports G, D, S, B are shown in this figure. Wherein the test structure names include MOS1, MOS2, etc., and the test structure bar names include TL01, etc. The coordinates of the ports of the test structure are shown in this figure, expressed in coordinates of a point. In the layout, the ports are usually identified by text, which has two parts, one is the coordinate position (the intersection position of the cross) and the other is the text content. The location of the port may be determined by the intersection coordinates of the cross identified therein.
Referring to fig. 10, fig. 10 illustrates a pad serial number and its coordinate information determined from a layout according to some embodiments of the present disclosure. As shown in FIG. 10, the leftmost side is the PAD number, and PADs in the layout can be numbered sequentially in a predetermined order. XL/YL represents the lower left corner of the outer frame of the PAD; XR/YR indicates the coordinates of the upper right corner. In this way, correspondence information of the serial number of the PAD and the coordinates of the PAD can be obtained.
Returning to FIG. 3 for continued description, at block 306, the graphs in the layout are looked up based on predetermined connectivity relationships between layers of the layout, starting from the respective ports for which the location information was determined, respectively. The predetermined connectivity relationships between the layers typically exist prior to generating the layout, with design rules for each technology node and documents defining the mapping layer relationships, where the predetermined connectivity relationships between the layers are defined.
Referring to fig. 11, fig. 11 illustrates a connectivity relationship between layers in a layout according to some embodiments of the present disclosure. Each layer in the layout has its corresponding layer number. The layers may each correspond to a different process purpose, e.g. with layers representing active areas, layers representing metal layers, etc. As shown in fig. 11, the port layer, the metal layer, and the connection layer are shown. The layer representations of the same row are interlinked, connected. Wherein the layer number is represented by two digits, the two digits being identical before and after the same layer, otherwise different layers are represented. In this example, the port layer includes a layer 61:250 and a layer 62:250. The metal layers include layer 61:0 and layer 62:0. The connection layer includes layers 71:0 and 72:0. Wherein the connection layer 71:0 in a row in the table may be, for example, a via layer. It should be noted that the port layer is not an actually effective layer and does not function in the subsequent process. The corresponding relationship between the port layer and the metal layer in the same row in fig. 11 is, for example, 61:250 for the port layer, and the corresponding 61:0 layer graph of the coordinates is found at this time, so that the graph tracking starts. The third column of connection layers and the layer 61:0 are interconnected, and the connection layers and the layer 71:0 according to the next column are also interconnected, so that continuous tracking can be realized, namely the connection relation of the second column and the third column in the figure can be sequentially associated.
In some embodiments, from the metal layer where the port is located, the trace pattern is searched or called in the corresponding layer with the connection relation. The trace path is a metal layer in the layout. The metal layer is the layer that is primarily tracked and the connection layer is the layer associated with the metal layer.
In some embodiments, starting from the metal layer where the port is located, the next pattern can be found continuously as long as the layers are communicated, and the position of the pattern which is finally found is determined. The found frame coordinates of each graph can be compared with the frame coordinates of the PAD, and the graph is completely consistent with the frame coordinates of the PAD, so that the graph is considered as the PAD, namely the port is connected with the PAD.
Without specifying the tracking direction, the pattern is tracked along each direction. Typically, a graphic in a layout has its properties, and is identified based on its properties. In addition, whether the graphic is a rectangle (box) or a polygon (polygon), or other, e.g., a path (path) of uniform width, can be identified based on the attributes. Text labels in graphics and layouts are distinguished. It is thus determined whether the pattern is found on the trace path based on the properties of the pattern. In some embodiments, the trace path is a metal layer in the layout. The metal layer on the layout mentioned here is a metal line after being formed on the wafer, i.e. the wafer test structure and the pad are connected on the wafer by the metal line.
In some embodiments, the tracking direction may be specified. The graphics can thus be looked up in the respective layers in accordance with a specified tracking direction, which coincides with the direction along the respective path determined on the basis of the predetermined connectivity relationship. It is believed that the predetermined connectivity relationship may determine a unique path. However, if the tracking direction is not specified, the port is searched in each direction, which results in lower efficiency. If the tracking direction is specified, efficiency can be improved. To this end, in some embodiments, the methods of the disclosed embodiments may support path tracking in a specified direction at the time of tracking.
Described below in connection with fig. 12. Referring to fig. 12, fig. 12 illustrates a schematic diagram of path tracing in a layout according to some embodiments of the present disclosure. As shown in fig. 12, from port D of the test structure, a trace is performed along trace path 1204, and graph 1202 can be found. If the tracking direction is not specified, all the four directions are tracked, and when a certain tracking direction is specified, for example, the metal trace of the D port in fig. 12 is left, tracking only to the left, but not to the whole direction can be supported, so that the efficiency can be further improved. Meanwhile, judgment errors caused by the fact that the test structure is a communication structure can be avoided. This is further described below.
At block 308, the second location information of the found graphic is compared with the first location information of the corresponding pad to generate a comparison result indicating whether the second location information is consistent with the first location information.
In some embodiments, in case the coordinate information of the border of the graphic coincides with the coordinate information of the border of the corresponding PAD, for example, the coordinates of the lower left corner and the upper right corner of the rectangle coincide with the coordinates of the lower left corner and the upper right corner of the predetermined PAD, respectively, a first result is generated, which indicates that the second position information coincides with the first position information. In the case where the coordinate information of the frame of the graphic is inconsistent with the coordinate information of the frame of the corresponding PAD, for example, the coordinates of the lower left corner and the upper right corner of the rectangle are inconsistent with at least one of the coordinates of the lower left corner and the coordinates of the upper right corner of the predetermined PAD, a second result is generated indicating that the second position information is inconsistent with the first position information. A discrepancy means that the pattern is not the PAD to be found, a coincidence means that the pattern is the PAD to be found.
At block 310, a connection status between each port and the corresponding gasket is determined based on the comparison. In some embodiments, the pattern is determined to be the corresponding pad based on the first result (i.e., the second position information is consistent with the first position information), thereby determining that the port is connected to the corresponding pad. Based on the second result (i.e., the second position information is inconsistent with the first position information), the graphic is determined to be a non-corresponding gasket, thereby determining that the port is not connected to the corresponding gasket.
In some embodiments, a connection status table may be generated based on connection status between each port of each of the at least one test structure strip and the corresponding pad; comparing the connection state table with each connection relation in the preset connection relation table; under the condition that the connection relations are completely consistent, determining that the connection relation between each port of each wafer test structure and the corresponding gasket is correct; and under the condition that the inconsistent connection relations exist, determining that the inconsistent connection relation between the corresponding ports and the gaskets is wrong.
A method of inspection for a wafer test structure according to one embodiment of the present disclosure is further described below with reference to fig. 8. Fig. 8 illustrates a flow chart of a method of inspecting a wafer test structure according to some embodiments of the present disclosure.
At block 802, a test structure layout is generated, e.g., a layout may be generated based on predetermined connection relationships between respective ports and corresponding pads. The final test structure strip layout is multi-level, but mainly consists of 2 parts, one part is the cell (level) of the test structure, and the other part is the level of the PAD.
At block 804, the serial number and coordinate information of the PAD may be parsed from the cell name of the PAD, i.e., the name of the layer in which the PAD is located.
At block 806, the port name and port coordinates may be resolved from the name of the test structure. And then tracking based on the communication relation (or connection relation) between layers from the port. Where the connectivity relationship specifies which layers are connected (connected). Thereby searching in each layer of the communication.
At block 808, the graphic is found and its position is determined, for example, by determining the coordinates of the lower left corner and the upper right corner of the graphic.
Then, the position information (coordinate information) of the found pattern is compared with the position information of the PAD of the corresponding serial number. If the two are completely consistent, the found graph is the corresponding PAD, and then the port is connected with the PAD; otherwise, if the result of the comparison is that the two are not completely consistent, the found pattern is not the corresponding PAD, so that the port is not connected with the PAD.
At block 810, the status information for the determined connection or not may be filled into the inspection form. The check form can be compared with an original form showing a preset connection relation, and the connection states of the corresponding ports in the check form and the PAD are consistent, so that the connection is correct; otherwise, the connection is wrong.
Several common test structures are used as examples to illustrate aspects of embodiments of the present disclosure.
Referring to fig. 13, fig. 13 illustrates a layout of a test structure strip according to some embodiments of the present disclosure. The test structure 602 in this figure is a MOS transistor with 4 ports. As shown in fig. 13, a plurality of test structures 602 and a plurality of PADs 604 connected via leads 606 are included.
Fig. 14 shows a detection result of a connection relationship between a port of the MOS transistor shown in fig. 13 and a pad, and is specifically a software screenshot. As shown in fig. 14, TESTKEY NAME is the name of the test structure, and TESTLINE NAME is the name of the test structure strip. G. D, S and B are four ports thereof. Result is the Result of the comparison, pass indicates normal connection, and Pass is acceptable. It is clearly shown from this figure that all connections are correct.
Fig. 15 illustrates a layout of a test structure strip according to further embodiments of the present disclosure. The test structure in this figure is a bipolar junction transistor (Bipolar Junction Transistor-BJT, simply referred to as BJT). The test structure has three ports C, B and E, respectively.
Fig. 16 shows the detection result of the connection relationship between the port and the spacer according to the test structure strip shown in fig. 15. As shown in fig. 16, the structure of which is substantially the same as that of fig. 15, and detailed description will not be repeated, except that the number of ports is different. It can be seen that the detection results indicate that all ports are correctly connected to the PAD.
Fig. 17 illustrates time statistics versus results for a conventional method and an inspection method according to some embodiments of the present disclosure. As can be seen from FIG. 17, the columns from left to right are the total number of test structure strips, the total number of test structures, the manual inspection time, and the automatic inspection time.
According to the traditional manual comparison method, a minimum of tens of seconds is required for checking one test structure strip, some complex structures may take a few minutes, if statistics of 1 minute are required for checking one test structure strip according to a person, and a few hours are required for checking hundreds of test structure strips, but the method of the embodiment of the disclosure only needs 1-2 seconds. As can be seen by comparing the data in fig. 17, compared with the conventional manual inspection method, the method according to the embodiment of the present disclosure uses the technique according to the embodiment of the present disclosure to perform the wire connection (or winding) inspection, so that the inspection time can be greatly shortened, specifically, the efficiency can be improved by several thousand times, and the more numerous inspection works are performed, the more obvious the improvement efficiency is.
Fig. 18 illustrates a layout of a test structure strip containing Openshort structures, according to some embodiments of the present disclosure. FIG. 19 shows a layout of an enlarged view of the Openshort structure shown in FIG. 18; fig. 20 is a layout of the Openshort structure shown in fig. 18 and 19. Openshort structures, i.e., structures including short circuits and open circuit devices therein.
When the test structures themselves are interconnected (e.g., the structure includes a plurality of ports through which the terminals are connected), such as the Snake-combo structure of wires, the wires themselves are connected, primarily to simulate the open or shorted condition of the wires, as shown in fig. 20.
Fig. 21 illustrates inspection results for Openshort structures without specifying tracking directions, according to some embodiments of the present disclosure.
When the tracking direction is not specified, the checking result is shown in fig. 21, where two connected terminals CON1 and CON2 are displayed, and two connected PADs are provided, for example, the CON1 end of the first testkey P5_ Openshort _top (1) _split1_1 checks that the connected PADs 2,3, and the CON2 is also connected to the PADs 2,3, so that the comparison result is considered inconsistent with the original predetermined connection relationship table, and the result is Fail (disqualification). In practice, the result belongs to erroneous judgment.
FIG. 22 illustrates port routing directions of a wafer test structure according to some embodiments of the present disclosure; fig. 23 shows the result of the inspection with tracking of port orientation according to fig. 22. The direction of the connection of the ports of the test structure may be specified. As shown in fig. 22, when the trace inspection is performed, each port traces only along the port direction shown in the figure, for example, CON1 traces only to the left, CON2 traces only to the right, and so on. The result of the examination is that, as shown in FIG. 23, CON1 and PAD2 are connected, CON2 and PAD3 are connected, and the comparison result is correct. That is, in the test structure having the communication structure, by designating the tracking direction, it is possible to improve the detection efficiency and to avoid erroneous judgment.
In addition, the embodiment of the disclosure also discloses an electronic device. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions comprising: the actions include: generating a layout based on a predetermined connection relationship between each port of a wafer test structure and a corresponding pad, wherein the wafer test structure comprises at least two ports, each port is suitable for being respectively connected with the corresponding pad, and the pad is suitable for receiving a detection signal; determining the position information of each port and the first position information of the corresponding gasket in the layout; starting from each port for which the position information is determined, searching the graph in the layout based on a preset connection relation between the layers of the layout; comparing the second position information of the searched graph with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not; and determining a connection state between each of the ports and the corresponding gasket based on the comparison result.
Also disclosed in embodiments of the present disclosure is a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method for inspecting a wafer test structure according to embodiments of the present disclosure.
The embodiment of the disclosure provides a novel scheme for automatically checking the correctness of the connection relation between the test structure and the PAD. According to the scheme of the embodiment of the disclosure, the detection efficiency of the connection relation between the test structure and the PAD can be greatly improved, so that a large amount of manpower can be saved; meanwhile, the error rate of the detection result can be obviously reduced.
According to the scheme of the embodiment of the disclosure, the automatic verification of the connection relation between testkey and PAD can be realized through a layout path tracking (PATH TRACING) method, meanwhile, the multi-process running of a program is supported, the time for checking hundreds of testline is only a few seconds, and the checking efficiency is greatly improved. Therefore, the problem that the traditional manual inspection is low in efficiency and uncontrollable in human error can be avoided.
Fig. 24 shows a schematic block diagram of an example device 2400 that can be used to implement an embodiment of the present disclosure. For example, computing device 110 shown in fig. 1 may be implemented by apparatus 2400. As shown, device 2400 includes a Central Processing Unit (CPU) 2401 that can perform various suitable actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM) 2402 or loaded from a storage unit 2408 into a Random Access Memory (RAM) 2403. In the RAM 2403, various programs and data required for the operation of the device 2400 can also be stored. The CPU 2401, ROM 2402, and RAM 2403 are connected to each other through a bus 2404. An input/output (I/O) interface 2405 is also connected to bus 2404.
Various components in device 2400 are connected to I/O interface 2405, including: an input unit 2406 such as a keyboard, a mouse, or the like; an output unit 2407 such as various types of displays, speakers, and the like; a storage unit 2408 such as a magnetic disk, an optical disk, or the like; and a communication unit 2409 such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 2409 allows the device 2400 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The processing unit 2401 performs the various methods and processes described above, such as method 300. For example, in some embodiments, the method 300 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 2408. In some embodiments, some or all of the computer programs may be loaded and/or installed onto device 2400 via ROM 2402 and/or communications unit 2409. One or more of the steps of method 300 described above may be performed when a computer program is loaded into RAM 2403 and executed by CPU 2401. Alternatively, in other embodiments, CPU 2401 may be configured to perform method 300 by any other suitable means (e.g., by means of firmware).
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), etc.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (10)
1. A test method for a wafer test structure, the wafer test structure comprising at least two ports, wherein each of the ports is adapted to be connected with a respective pad, the pads being adapted to receive a test signal, the method comprising:
generating a layout based on a preset connection relation between each port and the corresponding gasket;
determining the position information of each port and the first position information of the corresponding gasket in the layout;
starting from each port for which the position information is determined, searching the graph in the layout based on a preset connection relation between the layers of the layout;
Comparing the second position information of the searched graph with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not; and
And determining the connection state between each port and the corresponding gasket based on the comparison result.
2. The method of claim 1, wherein determining the location of each of the ports and the first location information of the corresponding pad in the layout comprises:
Determining coordinate information of the port based on the identification information of the port in the layout, wherein the identification information identifies the coordinate of the port in a text format; and
And analyzing the frame coordinates of the gasket in the layout to determine the first position information of the gasket.
3. The method of claim 1, wherein, starting from each of the ports for which the location information is determined, finding a graphic in the layout based on a predetermined connectivity relationship between layers of the layout comprises:
and respectively searching the graphics in the corresponding layers with the communication relation from the metal layer where the port is located.
4. A method according to claim 3, wherein, starting from the metal layer in which the port is located, searching the graphics in the corresponding layers having a connectivity relationship, respectively, comprises:
And searching the graph in the corresponding graph layer according to a designated direction, wherein the designated direction is consistent with the direction along the corresponding path determined based on the preset communication relation.
5. The method of claim 2, wherein comparing the second positional information of the found graphic with the first positional information of the corresponding pad to generate a comparison result comprises:
generating a first result indicating that the second position information is consistent with the first position information in response to the coordinate information of the frame of the graph being consistent with the coordinate information of the frame of the corresponding gasket; and
And generating a second result indicating that the second position information is inconsistent with the first position information in response to the fact that the coordinate information of the frame of the graph is inconsistent with the corresponding coordinate information of the frame of the gasket.
6. The method of claim 5, wherein determining a connection status between each of the ports and the gasket based on the comparison result comprises:
determining the pattern as the corresponding gasket based on the first result, thereby determining that the port is connected with the corresponding gasket; and
Based on the second result, the graph is determined to be not the corresponding gasket, thereby determining that the port is not connected to the corresponding gasket.
7. The method of claim 1, wherein the layout includes at least one of the wafer test structures, the at least one wafer test structure and the corresponding pad comprising a test structure strip, the layout includes at least one of the test structure strips, wherein the predetermined connection relationship is a predetermined connection relationship table indicating connection relationships between each of the ports of the at least one wafer test structure and the corresponding pad, respectively, the method further comprising:
Generating a connection status table based on the connection status between each of the ports of each of the at least one test structure strip and the corresponding pad;
comparing the connection state table with each connection relation in the preset connection relation table; and
Responding to the complete coincidence of the connection relations, and determining that the connection relation between each port of each wafer test structure and the corresponding gasket is correct; and in response to the presence of an inconsistency in the respective connection relationships, determining that a connection relationship error between the respective ports and the gasket for which the inconsistency exists.
8. The method of claim 4, wherein the path is a metal layer in the layout.
9. An electronic device, comprising:
A processor; and
A memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions comprising:
Generating a layout based on a predetermined connection relationship between each port of a wafer test structure and a corresponding pad, wherein the wafer test structure comprises at least two ports, each port is suitable for being respectively connected with the corresponding pad, and the pad is suitable for receiving a detection signal;
determining the position information of each port and the first position information of the corresponding gasket in the layout;
starting from each port for which the position information is determined, searching the graph in the layout based on a preset connection relation between the layers of the layout;
Comparing the second position information of the searched graph with the first position information of the corresponding gasket to generate a comparison result, wherein the comparison result indicates whether the second position information is consistent with the first position information or not; and
And determining the connection state between each port and the corresponding gasket based on the comparison result.
10. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method according to any of claims 1-8.
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