CN116384329A - Wiring checking method, device, equipment and storage medium for chip layout design - Google Patents

Wiring checking method, device, equipment and storage medium for chip layout design Download PDF

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Publication number
CN116384329A
CN116384329A CN202310331732.8A CN202310331732A CN116384329A CN 116384329 A CN116384329 A CN 116384329A CN 202310331732 A CN202310331732 A CN 202310331732A CN 116384329 A CN116384329 A CN 116384329A
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layout design
chip layout
drc
inspection
power
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宋志勋
兰金保
张云福
陈建威
肖勇
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Shenzhen Qianhai Shenlei Semiconductor Co ltd
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Shenzhen Qianhai Shenlei Semiconductor Co ltd
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Priority to CN202310331732.8A priority Critical patent/CN116384329A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation

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Abstract

The application relates to a chip layout design technology, and discloses a wiring inspection method for chip layout design, which comprises the following steps: inquiring a power label corresponding to each power pin and a ground wire label corresponding to each ground wire pin in the chip layout design; starting Calibre DRC inspection of the imported preset DRC rule file, executing initialization setting, and writing a power tag and a ground wire tag into an inspection target of the preset DRC rule file, wherein the identification level of the metal resistor is ignored in the level connection relation defined in the preset DRC rule file; performing a Calibre DRC check; and generating a checking result of the chip layout design. The application also discloses an inspection device, a computer device and a computer readable storage medium. The method aims at reducing the situation of false alarm generated when the Calibre is utilized to check the chip layout design.

Description

Wiring checking method, device, equipment and storage medium for chip layout design
Technical Field
The present disclosure relates to the field of chip layout design, and in particular, to a wiring inspection method, an inspection apparatus, a computer device, and a computer readable storage medium for chip layout design.
Background
Layout engineers of current chip designs typically use Calibre physical verification tools from Mentor corporation to perform design rule checking (Design Rule Check, DRC) and circuit rule checking (Layout versus schematic, LVS). In chip design, in general, a power line is led into an internal module of a chip through a power PAD, and a ground line is led into an internal module of a chip through a ground line PAD, so that connection information of the power line and the ground line can enter the internal module of the chip through metal wiring, and whether a device substrate is connected correctly (for example, whether a P-type substrate is connected to the ground line or not and whether an N-type substrate is connected to the power line or not) can be checked by using Calibre LVS.
In some cases, to maintain good noise isolation and circuit performance, multiple sets of power pins of different names (respectively distinguished by different power labels, such as AVDD and DVDD) are connected to the same power PAD, and multiple sets of ground pins of different names (respectively distinguished by different ground labels, such as AVSS and DVSS) are also connected to the same ground PAD, and metal electrical barriers need to be used to separate the power pins and the ground pins of different names (as shown in fig. 1). However, this connection method may generate errors in the inspection of the Calibre LVS, because the metal resistor may block the connection relationship between the power line and the ground line, that is, if any power pin is connected to the power PAD through the metal resistor, a correct result (similar to the above) of the corresponding power connection will not be obtained in the inspection of the Calibre LVS, and thus, an error report may be generated.
For the fault reporting situation, the prior solution is to manually perform layering inspection and visual inspection by a layout engineer, which definitely greatly increases the cost of manual inspection, especially when the number of power pins or ground pins divided by a metal resistor is too large, thus greatly increasing the workload of the layout engineer, and possibly causing the situation that the layout engineer has missed inspection due to too much inspection work.
The foregoing is merely provided to facilitate an understanding of the principles of the present application and is not admitted to be prior art.
Disclosure of Invention
The main purpose of the present application is to provide a wiring inspection method, inspection device, computer equipment and computer readable storage medium for chip layout design, which aims to reduce the occurrence of false alarms when the chip layout design is inspected by Calibre.
In order to achieve the above purpose, the present application provides a wiring inspection method for chip layout design, which includes the following steps:
inquiring a power label corresponding to each power pin and a ground wire label corresponding to each ground wire pin in the chip layout design;
starting Calibre DRC inspection of the imported preset DRC rule file, and executing initialization setting, writing the power tag and the ground wire tag into an inspection target of the preset DRC rule file, wherein the identification level of the metal resistor is ignored in a level connection relation defined in the preset DRC rule file;
executing the Calibre DRC check to check whether the power pins corresponding to the power tags are correctly wired and whether the ground pins corresponding to the ground tags are correctly wired;
and generating an inspection result of the chip layout design.
Optionally, the step of performing the Calibre DRC check further includes:
inquiring an N-type substrate which is not connected with a power supply;
wherein, the check rule statement defined in the preset DRC rule file includes:
and if the source electrode or the drain electrode of the MOS tube connected with the N-type substrate is not connected with a power supply, ignoring the N-type substrate.
Optionally, the step of performing the Calibre DRC check further includes:
inquiring the P-type substrate which is not connected with the ground wire;
wherein, the check rule statement defined in the preset DRC rule file includes:
and if the source electrode or the drain electrode of the MOS tube connected with the P-type substrate is not connected with the ground wire, ignoring the P-type substrate.
Optionally, the step of generating the inspection result of the chip layout design further includes:
if the checking result has an error reporting item, outputting error reporting information;
if a confirmation response of the error reporting information is received and the updating of the chip layout design is detected, returning to execute the Calibre DRC check;
and if a cancellation response of the error reporting information is received, ignoring an error reporting item aimed at by the cancellation response.
Optionally, before the step of querying the power label corresponding to each power pin and the ground label corresponding to each ground pin in the chip layout design, the method further includes:
and after the chip layout design is generated, executing Calibre DRC check without importing the preset DRC rule file.
To achieve the above object, the present application further provides an inspection apparatus including:
the query module is used for querying power labels corresponding to all power pins and ground wire labels corresponding to all ground wire pins in the chip layout design;
the starting module is used for starting Calibre DRC inspection of the imported preset DRC rule file, executing initialization setting, and writing the power tag and the ground wire tag into an inspection target of the preset DRC rule file, wherein the identification level of the metal resistor is ignored in a level connection relation defined in the preset DRC rule file;
a checking module, configured to perform the Calibre DRC check to check whether the power pins corresponding to each of the power tags are correctly wired, and to check whether the ground pins corresponding to each of the ground tags are correctly wired;
and the generating module is used for generating the checking result of the chip layout design.
To achieve the above object, the present application further provides a computer apparatus, including: the wiring inspection device comprises a memory, a processor and a wiring inspection program of the chip layout design, wherein the wiring inspection program of the chip layout design is stored in the memory and can run on the processor, and the wiring inspection program of the chip layout design realizes the steps of the wiring inspection method of the chip layout design when being executed by the processor.
In order to achieve the above object, the present application further provides a computer readable storage medium, on which a wiring inspection program of a chip layout design is stored, which when executed by a processor, implements the steps of the wiring inspection method of the chip layout design.
According to the wiring inspection method, the inspection device, the computer equipment and the computer readable storage medium for the chip layout design, the identification hierarchy of the metal resistor is ignored in the hierarchy connection relation defined in the DRC rule file, so that when the Calibre performs DRC inspection on the chip layout design based on the DRC rule file, false alarm caused by connection of a power pin or a ground wire pin of the chip to the power or the ground wire through the metal resistor can be avoided, the occurrence of false alarm caused when the chip layout design is inspected by the Calibre is reduced, the workload of a layout engineer for inspecting the false alarm caused by the Calibre is reduced, the cost of manual participation is correspondingly reduced, and the condition that the layout engineer has missing inspection caused by too much inspection work can be avoided.
Drawings
FIG. 1 is a schematic diagram of a chip layout design;
FIG. 2 is a schematic diagram illustrating steps of a wiring inspection method of a chip layout design according to an embodiment of the present application;
FIG. 3 is a schematic view of an inspection apparatus according to an embodiment of the present application;
fig. 4 is a schematic block diagram of an internal structure of a computer device according to an embodiment of the present application.
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to explain the present application and should not be construed as limiting the present application, and all other embodiments obtained by persons of ordinary skill in the art without creative efforts based on the embodiments in the present application are within the scope of protection of the present application.
Furthermore, the description of "first," "second," and the like, when referred to in this application, is for descriptive purposes only (e.g., to distinguish between identical or similar elements) and is not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
Referring to fig. 2, in an embodiment, the wiring inspection method of the chip layout design includes:
step S10, inquiring a power label corresponding to each power pin and a ground wire label corresponding to each ground wire pin in the chip layout design;
step S20, starting Calibre DRC inspection of the imported preset DRC rule file, executing initialization setting, and writing the power tag and the ground wire tag into an inspection target of the preset DRC rule file, wherein the identification level of the metal resistor is ignored in a level connection relation defined in the preset DRC rule file;
step S30, executing the Calibre DRC check to check whether the power pins corresponding to the power labels are correctly wired and check whether the ground pins corresponding to the ground labels are correctly wired;
and S40, generating a checking result of the chip layout design.
In this embodiment, the execution terminal of the embodiment may be a computer device, or may be an inspection device for chip layout design.
Optionally, a layout engineer completes the corresponding chip layout design according to the chip design requirement. After the chip layout design is completed, the terminal may query the power Label (i.e., power Label) of each power pin on the top layer of the chip layout design, and query the ground Label (i.e., ground Label) of each ground pin on the top layer of the chip layout design.
In addition, the terminal is loaded with a Calibre physical verification tool, and the related engineer can rewrite a preset DRC rule file according to the DRC rule file provided by the chip manufacturer and the format of grammar thereof, and can import the written preset DRC rule file into the Calibre DRC checking function.
Optionally, when the preset DRC rule file is written, a sentence of a new Comamnd file is created, added variables power_name and group_name (these variables are targets for inspection) are added, and then information of all layers to be used (such as the layer definition of the GDS used), identification layer information of connection relations between the layers and PINs thereof, identification layers of devices required for definition, and logic operation layers required for definition are defined.
Wherein, the recognition hierarchy of the metal resistor is ignored in the hierarchy connection relation defined in the preset DRC rule file. It should be noted that, since the DRC file provided by the integrated circuit manufacturer checks the connection relationship of the power line or the ground line, which is originally determined according to the hierarchy, and does not need to compare the netlist like the LVS file, it is only necessary to do not process the identification hierarchy of the metal resistor when defining the hierarchical connection relationship, so that the connection relationship of the power line or the ground line can be prevented from being blocked by the metal resistor.
Optionally, after the preset DRC rule file is written and imported, the terminal starts a Calibre DRC check, performs initial setting on the Calibre tool, performs initial setting on the preset DRC rule file, and writes the POWER label of the POWER pin and the GROUND label of the GROUND pin queried in step S10 into the power_name and the group_name parameters of the preset DRC rule file, respectively. The POWER tag is written into the power_name, and checking for the power_name, namely checking whether a POWER pin corresponding to the POWER tag is connected to a POWER supply or not; the GROUND tag is written into the ground_name, and a check is made for the ground_name, i.e., whether the GROUND pin corresponding to the GROUND tag is connected to GROUND.
Thus, when the terminal performs the Calibre DRC check, it can check whether the power pins corresponding to each of the power labels are properly wired, i.e., whether each power pin is connected to a power source (e.g., a power PAD); and checking whether the ground wire pins corresponding to the ground wire labels are correctly wired, namely checking whether the ground wire pins are connected to the ground wire (such as the ground wire PAD).
The identification level of the metal resistor is ignored in the level connection relation defined in the preset DRC rule file, so that even if the power supply pin is actually connected with the power supply through the metal resistor, calibre can identify the situation as that the power supply pin is correctly connected (i.e. the power supply pin is not incorrectly judged to be incorrectly connected); similarly, even if the ground pin is actually connected to the ground via a metal resistor, calibre can recognize this as the ground pin is connected correctly (i.e., the ground pin is not misjudged to be connected incorrectly).
Optionally, after performing Calibre DRC inspection on the chip layout design, a corresponding inspection result may be generated according to the inspection condition output by Calibre, for review by a layout engineer. The inspection result of the chip layout design comprises a result of whether each power pin on the top layer of the chip layout design is correctly wired or not and a result of whether each ground wire pin is correctly wired or not.
In an embodiment, the identification hierarchy of the metal resistor is ignored in the hierarchy connection relation defined in the DRC rule file, so that when the Calibre performs DRC inspection on the chip layout design based on the DRC rule file, false alarm generated by the Calibre due to the fact that a power pin or a ground wire pin of the chip is connected with a power source or a ground wire through the metal resistor can be avoided, the occurrence of false alarm generated when the chip layout design is inspected by the Calibre is reduced, the workload of a layout engineer for inspecting the false alarm of the Calibre is further reduced, the cost of manual participation is correspondingly reduced, and the condition that the layout engineer has missing inspection due to too much inspection work can be avoided.
In an embodiment, based on the above embodiment, the step of performing the Calibre DRC check further includes:
inquiring an N-type substrate which is not connected with a power supply;
wherein, the check rule statement defined in the preset DRC rule file includes:
and if the source electrode or the drain electrode of the MOS tube connected with the N-type substrate is not connected with a power supply, ignoring the N-type substrate.
In this embodiment, the identification hierarchy of the metal resistor is ignored in the hierarchical connection relationship defined in the preset DRC rule file, so that even if the metal resistor is arranged between the power supply pin and the power supply of the chip internal module or the metal resistor is arranged between the ground wire pin and the ground wire, the connection relationship generated by the power supply and the ground wire can still be transferred to the chip internal module, and then the wiring of the chip internal module is not blocked by the metal resistor, so that the error reporting of the Calibre on the special wiring conditions is avoided. Moreover, all of the on-chip modules can add inspection functionality to the substrate connection.
Optionally, when the related engineer compiles the preset DRC rule file, a corresponding check rule sentence may be defined in the preset DRC rule file.
Wherein the check rule statement includes:
and inquiring an N-type substrate (Ntap) which is not connected with a power supply, wherein if the inquired N-type substrate is connected with a source electrode or a drain electrode of the MOS tube and the source electrode or the drain electrode of the MOS tube is not connected with the power supply, the N-type substrate is ignored.
And when the terminal performs Calibre DRC check, the N-type substrate which is not connected with the power supply in the chip layout design is also queried according to the check rule statement. When an N-type substrate which is not connected with a power supply is inquired, if the N-type substrate is further detected to be provided with a source electrode or a drain electrode which is connected with an MOS tube and the source electrode or the drain electrode of the MOS tube is not connected with the power supply, the N-type substrate is ignored (namely, error reporting to the N-type substrate is ignored); otherwise, if the N-type substrate is not connected with the power supply and is not connected with the source electrode or the drain electrode of the MOS tube which is not connected with the power supply, the N-type substrate is subjected to normal error reporting.
It should be noted that, in the circuit design at present, in order to ensure that the threshold voltage (Vth) of the MOS transistor is fixed, a lining bias effect is not generated, the source electrode of the MOS transistor and the Bulk terminal are generally required to be connected, and the part of the connecting wire is not connected to a power line or a ground line, and the existing Calibre LVS inspection rule recognizes the special condition as a wiring error, so that the output inspection result is increased with an error reporting (i.e. a false error is increased), and the false error at present needs to be inspected one by one and ignored by a layout engineer, which not only takes a lot of time and effort but also is low in efficiency.
In this embodiment, through the inspection rule statement defined in the preset DRC rule file, the N-type substrate which is not connected with the power supply and is not connected with the source or the drain of the connected MOS transistor is ignored, so that the error reporting on the N-type substrate is not performed when the Calibre DRC inspection is performed, and thus, the error reporting on the situation that the Calibre connects the source and the Bulk terminal of the MOS transistor (that is, the situation that the Calibre connects the source and the Bulk terminal of the MOS transistor can be corrected to have correct wiring) is not generated (that is, the situation that the wiring is correct is equivalent to the situation that the Calibre connects the source and the Bulk terminal of the MOS transistor), thereby reducing the occurrence of false reporting when the Calibre inspection chip layout is used, further reducing the workload of a layout engineer to inspect the Calibre inspection error reporting, not only correspondingly reducing the cost of labor participation, but also avoiding the occurrence of the situation that the layout engineer has errors due to too much inspection work.
In an embodiment, based on the above embodiment, the step of performing the Calibre DRC check further includes:
inquiring the P-type substrate which is not connected with the ground wire;
wherein, the check rule statement defined in the preset DRC rule file includes:
and if the source electrode or the drain electrode of the MOS tube connected with the P-type substrate is not connected with the ground wire, ignoring the P-type substrate.
In this embodiment, the identification hierarchy of the metal resistor is ignored in the hierarchical connection relationship defined in the preset DRC rule file, so that even if the metal resistor is arranged between the power supply pin and the power supply of the chip internal module or the metal resistor is arranged between the ground wire pin and the ground wire, the connection relationship generated by the power supply and the ground wire can still be transferred to the chip internal module, and then the wiring of the chip internal module is not blocked by the metal resistor, so that the error reporting of the Calibre on the special wiring conditions is avoided. Moreover, all of the on-chip modules can add inspection functionality to the substrate connection.
Optionally, when the related engineer compiles the preset DRC rule file, a corresponding check rule sentence may be defined in the preset DRC rule file.
Wherein the check rule statement includes:
and inquiring a P-type substrate (Ptap) which is not connected with the ground wire, wherein if the inquired P-type substrate is connected with a source electrode or a drain electrode of the MOS tube and the source electrode or the drain electrode of the MOS tube is not connected with the ground wire, the P-type substrate is ignored.
And when the terminal performs Calibre DRC check, the terminal also queries the P-type substrate which is not connected with the ground wire in the chip layout design according to the check rule statement. When a P-type substrate with an unconnected ground wire is inquired, if the P-type substrate is further detected to have a source electrode or a drain electrode connected with an MOS tube, and the source electrode or the drain electrode of the MOS tube is not connected with the ground wire, the P-type substrate is ignored (i.e. error report to the P-type substrate is ignored); otherwise, if the P-type substrate is not connected with the ground wire and is not connected with the source electrode or the drain electrode of the MOS tube which is not connected with the ground wire, the P-type substrate is subjected to normal error reporting.
According to the embodiment, through the inspection rule statement defined in the preset DRC rule file, the P-type substrate which is not connected with the ground wire and is not connected with the source electrode or the drain electrode of the connected MOS tube is ignored, so that error reporting can not be carried out on the P-type substrate when the Calibre DRC inspection is carried out, error reporting can not be generated when the Calibre is connected with the source electrode and the Bulk end of the MOS tube (namely, the situation that the Calibre is connected with the source electrode and the Bulk end of the MOS tube and the correct wiring can be corrected), the occurrence of error reporting when the Calibre inspection chip layout is utilized is reduced, the workload of a layout engineer for checking error reporting is reduced, the cost of labor participation is correspondingly reduced, and the situation that a layout engineer can cause missing inspection due to too much checking work can be avoided.
In an embodiment, on the basis of the foregoing embodiment, the step of generating the inspection result of the chip layout design further includes:
if the checking result has an error reporting item, outputting error reporting information;
if a confirmation response of the error reporting information is received and the updating of the chip layout design is detected, returning to execute the Calibre DRC check;
and if a cancellation response of the error reporting information is received, ignoring an error reporting item aimed at by the cancellation response.
In this embodiment, when the terminal generates the inspection result of the chip layout design, if the inspection result has an error reporting item, the error reporting information corresponding to the error reporting item may be output to the associated device of the related engineer (e.g., layout engineer).
The fault reporting item comprises at least one of a power pin which is not connected with a power supply, a power pin which is not connected with a ground wire, an N-type substrate which is not connected with the power supply (the N-type substrate which does not comprise a source electrode or a drain electrode which is connected with a MOS tube and is not connected with the power supply), and a P-type substrate which is not connected with the ground wire (the P-type substrate which does not comprise a source electrode or a drain electrode which is connected with the MOS tube and is not connected with the ground wire).
Optionally, when the layout engineer receives the error reporting information through the association equipment, the chip layout design can be manually checked for the error reporting item in the error reporting information.
Optionally, if the layout engineer confirms that the error reporting item is not wrong, a confirmation response corresponding to the error reporting information can be sent to the terminal through the association equipment, the chip layout design is corrected and updated (such as wiring errors in the corrected chip layout design) according to the error reporting item, and after the terminal detects that the chip layout design is updated, the Calibre DRC inspection can be executed again. Thus, the wiring engineer is facilitated to quickly correct wiring errors in the chip layout design.
Optionally, if the layout engineer confirms that the error reporting item is wrong, the error reporting item is considered to belong to error reporting, and a cancellation response corresponding to the error reporting information can be sent to the terminal through the association equipment, so that the terminal ignores the error reporting item for which the cancellation response is aimed. Thus, the method is beneficial for a layout engineer to quickly eliminate the false alarm condition in the inspection result.
Optionally, if the finally obtained inspection result has no error item, the inspection is ended.
In an embodiment, due to the fact that the occurrence of false alarm generated when the Calibre is used for checking the chip layout design is reduced, when the follow-up layout engineer checks the error reporting information, the time for checking the error reporting information and the manual checking cost can be greatly reduced, the occurrence of the condition that the layout engineer can cause missed checking due to too much checking work can be avoided, the success rate and the yield of chip research and development are improved, and the time from the chip research and development to the chip before the chip is shortened (namely, the efficiency of chip research and development is correspondingly improved).
In an embodiment, based on the foregoing embodiment, before the step of querying a power tag corresponding to each power pin and a ground tag corresponding to each ground pin in the chip layout design, the method further includes:
and after the chip layout design is generated, executing Calibre DRC check without importing the preset DRC rule file.
In this embodiment, after the chip layout design is completed, the Calibre DRC inspection may be performed on the chip layout design by using Calibre without importing the preset DRC rule file, and the result of the wiring inspection on the power supply pins, the N-type substrate, and the ground wire pins and the P-type substrate, which are not connected to the power supply, may be eliminated.
Therefore, the terminal can utilize the existing Calibre tool to perform wiring inspection on other parts of the chip layout except the power supply pins, the N-type substrate, the ground wire pins and the P-type substrate, then the written preset DRC rule file is imported into the Calibre tool to perform Calibre DRC inspection on the power supply pins, the N-type substrate, the ground wire pins and the P-type substrate in the chip layout, so that the scheme of the embodiment can be compatible with the function of the existing Calibre tool for performing wiring inspection on other parts of the chip layout except the power supply pins, the N-type substrate, the ground wire pins and the P-type substrate, and the occurrence of false alarms generated when the Calibre DRC is utilized to perform wiring inspection on the power supply pins, the N-type substrate, the ground wire pins and the P-type substrate in the chip layout can be reduced.
Referring to fig. 3, there is also provided an inspection apparatus Z10 according to an embodiment of the present application, including:
the query module Z11 is used for querying power labels corresponding to all power pins and ground wire labels corresponding to all ground wire pins in the chip layout design;
a starting module Z12, configured to start Calibre DRC inspection, into which a preset DRC rule file has been imported, and perform initialization setting, and write the power tag and the ground tag into an inspection target of the preset DRC rule file, where an identification level of a metal resistor is ignored in a level connection relationship defined in the preset DRC rule file;
a checking module Z13, configured to perform the Calibre DRC check to check whether the power pins corresponding to each of the power tags are correctly wired, and to check whether the ground pins corresponding to each of the ground tags are correctly wired;
and the generating module Z14 is used for generating the checking result of the chip layout design.
Alternatively, the inspection device may be a virtual control device.
Referring to fig. 4, a computer device is further provided in an embodiment of the present application, and the internal structure of the computer device may be as shown in fig. 4. The computer device includes a processor, a memory, a communication interface, and a database connected by a system bus. Wherein the processor is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used for storing wiring checking programs of chip layout design. The communication interface of the computer device is used for data communication with an external terminal. The input device of the computer device is used for receiving signals input by external equipment. The computer program, when executed by a processor, implements a wiring inspection method of a chip layout design as described in the above embodiments.
Those skilled in the art will appreciate that the architecture shown in fig. 4 is merely a block diagram of a portion of the architecture in connection with the present application and is not intended to limit the computer device to which the present application is applied.
Furthermore, the present application proposes a computer readable storage medium comprising a wiring inspection program of a chip layout design, which when executed by a processor implements the steps of the wiring inspection method of a chip layout design as described in the above embodiments. It is understood that the computer readable storage medium in this embodiment may be a volatile readable storage medium or a nonvolatile readable storage medium.
In summary, in the wiring inspection method, the inspection device, the computer device and the computer readable storage medium for chip layout design provided in the embodiments of the present application, through ignoring the identification hierarchy of the metal resistor in the hierarchical connection relation defined in the DRC rule file, when the Calibre performs DRC inspection on the chip layout design based on the DRC rule file, the Calibre can be prevented from generating false alarm due to the fact that the power pin or the ground wire pin of the chip is connected to the power or the ground wire through the metal resistor, so that the occurrence of the false alarm generated when the chip layout design is inspected by the Calibre is reduced, the workload of a layout engineer for inspecting the Calibre is reduced, the cost of manual participation is correspondingly reduced, and the situation that the layout engineer has missed inspection due to too much inspection work can be avoided.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium provided herein and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus, article or method that comprises the element.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.

Claims (8)

1. The wiring inspection method for the chip layout design is characterized by comprising the following steps of:
inquiring a power label corresponding to each power pin and a ground wire label corresponding to each ground wire pin in the chip layout design;
starting Calibre DRC inspection of the imported preset DRC rule file, and executing initialization setting, writing the power tag and the ground wire tag into an inspection target of the preset DRC rule file, wherein the identification level of the metal resistor is ignored in a level connection relation defined in the preset DRC rule file;
executing the Calibre DRC check to check whether the power pins corresponding to the power tags are correctly wired and whether the ground pins corresponding to the ground tags are correctly wired;
and generating an inspection result of the chip layout design.
2. The wire inspection method of chip layout design according to claim 1, wherein said step of performing said Calibre DRC inspection further comprises:
inquiring an N-type substrate which is not connected with a power supply;
wherein, the check rule statement defined in the preset DRC rule file includes:
and if the source electrode or the drain electrode of the MOS tube connected with the N-type substrate is not connected with a power supply, ignoring the N-type substrate.
3. The wire inspection method of chip layout design according to claim 1, wherein said step of performing said Calibre DRC inspection further comprises:
inquiring the P-type substrate which is not connected with the ground wire;
wherein, the check rule statement defined in the preset DRC rule file includes:
and if the source electrode or the drain electrode of the MOS tube connected with the P-type substrate is not connected with the ground wire, ignoring the P-type substrate.
4. The wiring inspection method of a chip layout design according to claim 1, wherein the step of generating an inspection result of the chip layout design further comprises:
if the checking result has an error reporting item, outputting error reporting information;
if a confirmation response of the error reporting information is received and the updating of the chip layout design is detected, returning to execute the Calibre DRC check;
and if a cancellation response of the error reporting information is received, ignoring an error reporting item aimed at by the cancellation response.
5. The method for checking the wiring of a chip layout design according to any one of claims 1 to 4, wherein before the step of querying the power label corresponding to each power pin and the ground label corresponding to each ground pin in the chip layout design, the method further comprises:
and after the chip layout design is generated, executing Calibre DRC check without importing the preset DRC rule file.
6. An inspection apparatus, comprising:
the query module is used for querying power labels corresponding to all power pins and ground wire labels corresponding to all ground wire pins in the chip layout design;
the starting module is used for starting Calibre DRC inspection of the imported preset DRC rule file, executing initialization setting, and writing the power tag and the ground wire tag into an inspection target of the preset DRC rule file, wherein the identification level of the metal resistor is ignored in a level connection relation defined in the preset DRC rule file;
a checking module, configured to perform the Calibre DRC check to check whether the power pins corresponding to each of the power tags are correctly wired, and to check whether the ground pins corresponding to each of the ground tags are correctly wired;
and the generating module is used for generating the checking result of the chip layout design.
7. A computer device, characterized in that it comprises a memory, a processor and a wiring inspection program of a chip layout design stored on the memory and executable on the processor, which wiring inspection program of a chip layout design, when being executed by the processor, implements the steps of the wiring inspection method of a chip layout design according to any one of claims 1 to 5.
8. A computer-readable storage medium, on which a wiring inspection program of a chip layout design is stored, which when executed by a processor implements the steps of the wiring inspection method of a chip layout design as claimed in any one of claims 1 to 5.
CN202310331732.8A 2023-03-31 2023-03-31 Wiring checking method, device, equipment and storage medium for chip layout design Pending CN116384329A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118068235A (en) * 2024-04-19 2024-05-24 全芯智造技术有限公司 Detection method for wafer test structure, electronic equipment and storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118068235A (en) * 2024-04-19 2024-05-24 全芯智造技术有限公司 Detection method for wafer test structure, electronic equipment and storage medium

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