CN115395977A - Integrated radio frequency processing circuit - Google Patents
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- CN115395977A CN115395977A CN202211018365.8A CN202211018365A CN115395977A CN 115395977 A CN115395977 A CN 115395977A CN 202211018365 A CN202211018365 A CN 202211018365A CN 115395977 A CN115395977 A CN 115395977A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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Abstract
The invention provides an integrated radio frequency processing circuit, and relates to the field of radio frequency processing. The integrated radio frequency processing circuit comprises an AD9361 configuration module, 1090MHz signals, 40MHz clock signals, SPI interface signals, 10bit digital signals and power supply signals, wherein an internal receiving link of the AD9361 configuration module mainly comprises a preposed low noise amplifier, a mixer, an amplifier, a low-pass filter, an ADC, a digital filtering amplifier group, a control interface and a power supply interface. The hardware circuit can be integrated on the information processing board to form a whole, the size of the equipment is effectively reduced, the power consumption of the equipment is reduced, the popularization to a wider application scene is facilitated, the adopted integrated radio frequency processing circuit takes an AD9361 integrated chip as a core, peripheral devices are fewer, the debugging difficulty is lower, the consistency of the product is better, the use of discrete components is greatly reduced, the manufacturing cost of the product is reduced, and the economic benefit is higher.
Description
Technical Field
The invention relates to the technical field of radio frequency processing, in particular to an integrated radio frequency processing circuit.
Background
At present, radio equipment of L wave band is widely applied to carriers of airplanes, vehicles, ships and the like, relates to the fields of navigation, communication, detection and the like, is an indispensable important component part of carrier functions, 2 receiving channels of L wave band are required to be designed in a situation monitoring system and are used as receiving paths of aerial signals, a new channel design scheme is adopted during design, success is achieved, and meanwhile, the radio equipment can be popularized to other products.
In the design of airborne radio equipment, a radio frequency channel is inevitably required to be designed no matter a receiving channel or a transmitting channel, and the traditional design scheme adopts classified basic components to build various functional modules (an amplifier, a filter, a frequency converter and the like) required by the radio frequency channel, so that the problems of high cost, large volume, large power consumption, difficulty in production and the like exist in the scheme.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides an integrated radio frequency processing circuit, which solves the problems of high cost, large volume, large power consumption and difficult production.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: an integrated radio frequency processing circuit comprises an AD9361 configuration module, 1090MHz signals, 40MHz clock signals, SPI interface signals, 10bit digital signals and power supply signals, wherein an internal receiving link of the AD9361 configuration module mainly comprises a preposed low noise amplifier, a mixer, an amplifier, a low pass filter, an ADC, a digital filter amplifier group, a control interface and a power supply interface.
Preferably, the receiving link is divided into two down-conversions, and the integrated radio frequency processing circuit completes one down-conversion; the baseband signal processing circuit completes secondary down conversion, wherein the radio frequency local oscillator of primary down conversion is set to 1080MHz, the radio frequency local oscillator is input by an external 40MHz crystal oscillator and is obtained by frequency multiplication of an internal phase-locked loop circuit, an analog 10MHz intermediate frequency signal is formed after primary down conversion and is output to a digital-to-analog conversion part, the sampling rate of the analog-to-digital conversion part is 40MHz, so that an FPGA in the digital processing circuit can obtain an effective signal with the central frequency of 10MHz, and DDC secondary down conversion and matched filtering are realized inside the FPGA to complete demodulation of PPM signals.
Preferably, the situation monitoring signal of the gain control is a burst pulse signal, and the gain inside the AD9361 is fixed by adopting a manual gain control mode.
Preferably, the LS0C1410 internal analog amplifier gain chain is composed of radio frequency front end LMT amplifier simulation and LPF amplifier simulation, the maximum can be set to 76dB, and the gain of the analog amplifier is determined to be 43dB by the analysis and design of the front gain space built-in.
Preferably, the low-pass filter is used for frequency-selective filtering of the mixed signal, the parameters of the low-pass filter are related to the signal characteristics of the ADS-B, the bandwidth of the ADS-B signal is 2MHz +/-1 MHz, and the-3 dB bandwidth of the low-pass filter is selected to be 20MHz in order to keep the leading edge of pulse modulation as much as possible.
Preferably, the gain distribution is according to the design requirement of the total gain of 43dB of the AD9361 internal channel, the LMT amplifier, the mixer, the low pass filter and the LPF amplifier in the front-end link provide 43dB of gain together, the noise figure of the first stage amplifier of the AD9361 is not more than 1.0dB, the noise figure of the later stage mixer is not more than 0.5dB, and therefore the total noise figure of the integrated rf processing circuit can be controlled below 1.5 dB.
Preferably, the AD9361 is connected to the CPU core through an LVDS serial data interface and an SPI control interface, and all internal register read and write are configured and read through the SPI interface, and the functional unit may be divided into: SPL read and write, interface configuration, clock configuration, gain configuration, and filter configuration.
Preferably, the LSOC1410 further has a flexible manual gain mode, supports external control, carries two high dynamic range analog-to-digital converters ADCs per channel, digitizes the received I and Q signals, then passes through a configurable decimation filter and a 128-tap Finite Impulse Response (FIR) filter, and generates a 12-bit output signal at a corresponding sampling rate as a result, the core of the LSOC1410 can be directly powered by a 1.3V voltage regulator, and the IC is controlled by a standard four-wire serial port and four real-time input/output control pins.
Preferably, the circuit needs two types of direct current power supplies, namely +1.8V and +1.3V, and each type of direct current power supply consists of multiple paths of power supplies with the same voltage so as to meet the power supply requirement of the core chip AD9361 of the circuit; the power supply signals are all from the third power conversion circuit.
(III) advantageous effects
The invention provides an integrated radio frequency processing circuit. The method has the following beneficial effects:
1. in the invention, by adopting the radio frequency front-end channel, a hardware circuit can be integrated on the information processing board to form a whole, thereby effectively reducing the volume of the equipment, reducing the power consumption of the equipment and being beneficial to being popularized to wider application scenes.
2. In the invention, the adopted integrated radio frequency processing circuit takes an AD9361 integrated chip as a core, has fewer peripheral devices, has smaller debugging difficulty and has better product consistency.
3. In the invention, the application of the integrated chip greatly reduces the use of discrete components, further reduces the manufacturing cost of products and has higher economic benefit.
Drawings
FIG. 1 is a block diagram of the overall design of an integrated RF processing circuit according to the present invention;
FIG. 2 is a signal flow diagram of the overall system of the present invention;
FIG. 3 is a block diagram of the basic link of the RF receive path of the present invention;
FIG. 4 is a diagram of gain distribution for the RF channels of the present invention;
FIG. 5 is a structural composition diagram of a configuration flow in the present invention;
FIG. 6 is a flow chart of software configuration in the present invention;
fig. 7 is an overall circuit block diagram of a receiver using an integrated rf processing circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1 to 7, an embodiment of the present invention provides an integrated radio frequency processing circuit, which includes an AD9361 configuration module, 1090MHz signals, 40MHz clock signals, SPI interface signals, 10bit digital signals, and power supply signals, and an internal receiving link of the AD9361 configuration module, which mainly includes a pre-low noise amplifier, a mixer, an amplifier, a low pass filter, an ADC, and a digital filter amplifier bank, a control interface, and a power supply interface, where functions of each part are introduced as follows: 1090MHz signal: two paths of 1090MHz are input by an antenna and then output to the circuit; 40MHz clock signal: the clock signal is generated by the baseband signal processing circuit, and one path of the clock signal is output to the circuit after level matching and clock distribution, and the clock signal is homologous with the baseband signal processing circuit; SPI interface signal: the signal realizes data cross-linking between the circuit and the FPGA, and completes the setting of the internal working parameters of the circuit and the control of the working state; 10bit digital signal: the two paths of 10-bit digital signals are final output signals of the circuit, are output to a rear-stage baseband signal processing circuit and are received by an FPGA chip; power supply signals: the circuit needs two direct current power supplies of +1.8V and +1.3V, each of which is composed of multiple paths of power supplies with the same voltage, so as to meet the power supply requirement of the core chip AD9361 of the circuit; the power supply signals are all from the third power conversion circuit.
The receiving link is divided into two down-conversions, and the integrated radio frequency processing circuit completes one down-conversion; the secondary down-conversion is completed by a baseband signal processing circuit, wherein a radio frequency local oscillator of the primary down-conversion is set to be 1080MHz, the radio frequency local oscillator is input by an external 40MHz crystal oscillator and is obtained by frequency multiplication through an internal phase-locked loop circuit, a simulated 10MHz intermediate frequency signal is formed after the primary down-conversion and is output to a digital-to-analog conversion part, the sampling rate is 40MHz is selected in the analog-to-digital conversion part, so that an FPGA in the digital processing circuit can obtain an effective signal with the central frequency of 10MHz, DDC secondary down-conversion and matched filtering are realized in the FPGA to complete demodulation work of a PPM signal, a situation monitoring signal of gain control is a burst pulse signal, a manual gain control mode is adopted, the gain in an AD9361 is fixed, a gain chain of an internal analog amplifier of an LS0C1410 is composed of simulation of a radio frequency front-end LMT amplifier and simulation of an LPF amplifier, 76dB can be set to the maximum, the gain of the analog amplifier is determined by analysis and design of the front gain space, the low-pass filter is used for frequency selection and filtering of the mixed signal, parameters of the leading edge-B are related to the characteristics of ADS-B signal, the ADS-B signal is adjusted to be +/-1 MHz, the possible bandwidth is reserved, and the leading edge of the pulse filter is 20-3 MHz.
Gain distribution is according to the design requirement of AD9361 internal channel total gain 43dB, LMT amplifier, mixer, low pass filter, LPF amplifier in the front end link provide 43dB gain altogether, AD9361 first stage amplifier's noise factor is not more than 1.0dB, the noise factor of later stage mixer is not more than 0.5dB, therefore integrated radio frequency processing circuit's total noise factor can be controlled below 1.5dB, AD9361 passes through LVDS serial data interface and SPI control interface with CPU, all internal register reads and writes and disposes and reads through SPI interface, this functional unit can divide into as required: SPL read-write, interface configuration, clock configuration, gain configuration and filter configuration, LSOC1410 also has flexible manual gain mode, supports external control, each channel carries two high dynamic range analog-to-digital converters (ADC), firstly digitalizes the received I signal and Q signal, then makes it pass through configurable decimation filter and 128-tap Finite Impulse Response (FIR) filter, the result generates 12-bit output signal output with corresponding sampling rate, the core of LSOC1410 can be directly powered by 1.3V voltage stabilizer, IC is controlled by a standard four-wire serial port and four real-time input/output control pins.
The receiver designed according to the invention consists of an information board and a receiving board, wherein the related circuits are designed on the information board, and the AD9361 and an embedded CPU are as follows: the connection between ZYNQ includes: clock interface difference signal, two-way 12 bit data interface digital signal, SPI interface control command deliver the interface, include with other circuit between be connected: power input interface 4 kinds of matching coil circuit of power input, receiving and transmitting interface.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. The utility model provides an integrated radio frequency processing circuit, includes AD9361 configuration module, 1090MHz signal, 40MHz clock signal, SPI interface signal, 10bit digital signal and power supply signal, its characterized in that: the AD9361 configures an internal receiving link of the module, which mainly comprises a preposed low noise amplifier, a mixer, an amplifier, a low pass filter, an ADC, a digital filtering amplifier group, a control interface and a power interface.
2. An integrated radio frequency processing circuit according to claim 1, wherein: the receiving link is divided into two down-conversions, and the integrated radio frequency processing circuit completes the one down-conversion; the baseband signal processing circuit completes secondary down conversion, wherein the radio frequency local oscillator of primary down conversion is set to 1080MHz, the radio frequency local oscillator is input by an external 40MHz crystal oscillator and is obtained by frequency multiplication of an internal phase-locked loop circuit, an analog 10MHz intermediate frequency signal is formed after primary down conversion and is output to a digital-to-analog conversion part, the sampling rate of the analog-to-digital conversion part is 40MHz, so that an FPGA in the digital processing circuit can obtain an effective signal with the central frequency of 10MHz, and DDC secondary down conversion and matched filtering are realized inside the FPGA to complete demodulation of PPM signals.
3. An integrated radio frequency processing circuit according to claim 1, wherein: the situation monitoring signal of gain control is a burst pulse signal, and the gain inside the AD9361 is fixed by adopting a manual gain control mode.
4. An integrated radio frequency processing circuit according to claim 1, wherein: the gain chain of the analog amplifier in the LS0C1410 is composed of radio frequency front end LMT amplifier simulation and LPF amplifier simulation, the maximum can be set to 76dB, and the gain of the analog amplifier is determined to be 43dB by the analysis and design of the gain space built-in.
5. An integrated radio frequency processing circuit according to claim 1, wherein: the low-pass filter is used for carrying out frequency-selective filtering on the mixed signals, the parameters of the low-pass filter are related to the signal characteristics of the ADS-B, the bandwidth of the ADS-B signal is 2MHz +/-1 MHz, and the-3 dB bandwidth of the low-pass filter is selected to be 20MHz in order to keep the leading edge of pulse modulation as far as possible.
6. An integrated radio frequency processing circuit according to claim 1, wherein: according to the design requirement of the total gain 43dB of an AD9361 internal channel, the LMT amplifier, the mixer, the low-pass filter and the LPF amplifier in a front-end link provide the gain of 43dB, the noise coefficient of the first-stage amplifier of the AD9361 is not more than 1.0dB, the noise coefficient of the later-stage mixer is not more than 0.5dB, and therefore the total noise coefficient of the integrated radio frequency processing circuit can be controlled below 1.5 dB.
7. An integrated radio frequency processing circuit according to claim 1, wherein: AD9361 and CPU kernel pass through LVDS serial data interface and SPI control interface and link to each other, and all internal register read and write all dispose and read through the SPI interface, and this functional unit can divide into as required: SPL read and write, interface configuration, clock configuration, gain configuration, and filter configuration.
8. An integrated radio frequency processing circuit according to claim 1, wherein: the LSOC1410 also has a flexible manual gain mode and supports external control, each channel carries two high dynamic range analog-to-digital converters (ADC), received I signals and Q signals are firstly processed in a digital mode, then the signals pass through a configurable decimation filter and a 128-tap Finite Impulse Response (FIR) filter, and a 12-bit output signal is generated and output at a corresponding sampling rate as a result, the core of the LSOC1410 can be directly powered by a 1.3V voltage stabilizer, and the IC is controlled by a standard four-wire serial port and four real-time input/output control pins.
9. An integrated radio frequency processing circuit according to claim 1, wherein: the circuit needs two direct current power supplies of +1.8V and +1.3V, and each direct current power supply consists of a plurality of paths of power supplies with the same voltage so as to meet the power supply requirement of the core chip AD9361 of the circuit; the power supply signals are all from the third power conversion circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211018365.8A CN115395977A (en) | 2022-08-24 | 2022-08-24 | Integrated radio frequency processing circuit |
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| CN202211018365.8A CN115395977A (en) | 2022-08-24 | 2022-08-24 | Integrated radio frequency processing circuit |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209982489U (en) * | 2019-06-03 | 2020-01-21 | 西安思丹德信息技术有限公司 | Integrated ground data chain equipment |
| CN113114291A (en) * | 2021-04-01 | 2021-07-13 | 中国空空导弹研究院 | Reconfigurable dual-channel digital receiver radio frequency front-end device |
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- 2022-08-24 CN CN202211018365.8A patent/CN115395977A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209982489U (en) * | 2019-06-03 | 2020-01-21 | 西安思丹德信息技术有限公司 | Integrated ground data chain equipment |
| CN113114291A (en) * | 2021-04-01 | 2021-07-13 | 中国空空导弹研究院 | Reconfigurable dual-channel digital receiver radio frequency front-end device |
Non-Patent Citations (1)
| Title |
|---|
| 百度文库: "《AD9361_datasheet》", 31 May 2016, pages: 1 - 35 * |
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